CN102569356A - Semiconductor device having guard ring structure, display driver circuit, and display apparatus - Google Patents
Semiconductor device having guard ring structure, display driver circuit, and display apparatus Download PDFInfo
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- CN102569356A CN102569356A CN2011104318857A CN201110431885A CN102569356A CN 102569356 A CN102569356 A CN 102569356A CN 2011104318857 A CN2011104318857 A CN 2011104318857A CN 201110431885 A CN201110431885 A CN 201110431885A CN 102569356 A CN102569356 A CN 102569356A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000005856 abnormality Effects 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 8
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 2
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 2
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 2
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device with a guard ring structure, a display driver circuit, and a display device are provided to the abnormality of logic by emitting an electric charge using a ESD(Electro Static Discharge) tester to a display panel. A first well areas(103,104) are formed in a semiconductor substrate(10) in a predetermined depth. A second well areas(101,102) are formed in the first well area in a predetermined depth. The guard ring area(110) of a second conductive type is formed in a predetermined depth by being separately placed between the first well areas. The guard ring area is connected to a ground voltage.
Description
The application requires to be submitted on December 29th, 2010 rights and interests of the 10-2010-0138259 korean patent application of Korea S Department of Intellectual Property, and its disclosed full content is contained in this by reference.
Technical field
The present invention relates to a kind of semiconductor device, display driver and display device with guard ring (guard ring); More particularly, relate to and a kind ofly have the semiconductor device that is used for electric charge is discharged into systematically the guard ring of (system ground), comprise the display driver of this semiconductor device and comprise the display device of this display driver.
Background technology
Equipment based on display port need pass through International Electrotechnical Commission (International Electrotechnical Commission, the electrostatic discharge (ESD) of IEC) stipulating in 61000-4-2 standard test.For example, the mobile phone that often contacts with hand must be through the test of the 4th grade (level 4) or higher level.When test period use test machine is transmitted into target device with electric charge, electric charge is injected into the semiconductor device in the display driver in the equipment of being included in.At this moment, semiconductor device possibly caused permanent damages or suffered logic unusual by the electric charge that injects usually because of its structure.
Summary of the invention
Some embodiments of the present invention provide a kind of and have the semiconductor device that is used to make permanent damages or unusual minimized structure, comprise the display driving circuit of this semiconductor device and comprise the display device of this display driving circuit.
According to some embodiments of the present invention, a kind of semiconductor device is provided, said semiconductor device comprises: the semiconductor-based end, have first conduction type; At least two first well areas have second conduction type and desired depth in the semiconductor-based end; At least one second well area has first conduction type and desired depth in each first well area; The guard ring zone has second conduction type and desired depth, and between first well area, to separate predetermined distance with first well area.The guard ring zone can be connected to ground voltage.
The guard ring zone can be darker than first well area.Each first well area can be included in the lip-deep N+ layer of each first well area.Second well area can be included in the lip-deep P+ layer of second well area.The guard ring zone can be included in the lip-deep N+ layer in guard ring zone.
Said semiconductor device can also be included on the surface at the semiconductor-based end and the P+ layer between first well area and guard ring zone.
The lip-deep N+ layer in the lip-deep N+ layer of each first well area, the lip-deep P+ layer of second well area and guard ring zone can be connected respectively to electrode.The electrode that is connected to the lip-deep N+ layer in guard ring zone can be connected to ground voltage.Electric charge can be injected into one of electrode that is connected with the lip-deep N+ layer of each first well area.
First conduction type can be the P type, and second conduction type can be the N type.
According to other embodiment of the present invention, a kind of method of making semiconductor device is provided.The following operation of said method: first well area of at least two second conduction types formed apart from the surface at the semiconductor-based end of first conduction type reach desired depth; In each first well area, form second well area of at least one first conduction type with desired depth; Between first well area, form the guard ring zone that separates predetermined second conduction type distance and that have desired depth with first well area; The guard ring zone is connected to ground voltage.
The operation that forms the guard ring zone can comprise and forms the guard ring zone darker than first well area.
According to other embodiment of the present invention, a kind of display driving circuit that comprises aforesaid semiconductor device is provided.
According to other embodiment of the present invention, a kind of aforesaid display driving circuit display device that comprises is provided.
According to other embodiment of the present invention, a kind of semiconductor device is provided, said semiconductor device comprises: first circuit region; The second circuit zone; Guard ring zone is arranged between first circuit region and the second circuit zone separating the distance of being scheduled to first circuit region and second circuit zone, and forms and have desired depth, and wherein, the guard ring zone is connected to ground voltage.
Description of drawings
Through with reference to accompanying drawing exemplary embodiment of the present invention being described in detail, the top feature and advantage with other of the present invention will become more obvious, in the accompanying drawings:
Fig. 1 is the diagrammatic sketch according to the semiconductor device of some embodiments of the present invention;
Fig. 2 is the diagrammatic sketch according to the semiconductor device of other embodiment of the present invention;
Fig. 3 is the curve chart that the voltage change in time of the electrode with the regional semiconductor device of guard ring is shown;
Fig. 4 is the curve chart that the voltage change in time of the electrode with the regional semiconductor device of guard ring is shown;
Fig. 5 is the flow chart according to the method for the manufacturing semiconductor device of some embodiments of the present invention;
Fig. 6 A is the diagrammatic sketch according to the display device of some embodiments of the present invention;
Fig. 6 B is the diagrammatic sketch that comprises the system of the display device shown in Fig. 6 A;
Fig. 6 C illustrates the diagrammatic sketch of charge transfer to the process of the semiconductor device shown in Fig. 1 or Fig. 2;
Fig. 7 is the diagrammatic sketch according to the semiconductor chip of some embodiments of the present invention;
Fig. 8 A and Fig. 8 B are the diagrammatic sketch that is used to realize the semiconductor device of the semiconductor chip shown in Fig. 7.
Embodiment
Now, will come more fully to have described the present invention with reference to accompanying drawing hereinafter, embodiments of the invention shown in the drawings.Yet the present invention can implement with many different forms, and should not be construed as limited to the embodiment that sets forth here.On the contrary, provide these exemplary embodiments to make that the disclosure will be thorough with completely, and will convey to those skilled in the art to scope of the present invention fully.In the accompanying drawings, for clarity, can exaggerate the layer with the zone size and relative size.Same numeral is indicated similar elements all the time.
It should be understood that when element was known as " being connected to " another element and perhaps " is attached to " another element, this element can be directly connected to another element or directly be attached to another element, perhaps can have intermediary element.On the contrary, perhaps " directly be attached to " another element, do not have intermediary element when element is known as " being directly connected to " another element.As used herein, term " and/or " comprise the combination in any and all combinations of one or more relevant Listed Items, and can be abbreviated as "/".
Though it should be understood that to use a technical term here that first, second waits and describes various elements, these elements are not limited by these terms should.These terms only are used for an element and another element are made a distinction.For example, under the situation that does not break away from instruction of the present disclosure, first signal can be called as secondary signal, and similarly, secondary signal can be called as first signal.
Term used herein has been merely and has described the purpose of particular example embodiment, and is not intended to limit the present invention.As used herein, only if context spells out in addition, otherwise singulative also is intended to comprise plural form.It will also be understood that; When using a technical term " comprising " and/or " comprising " in this manual; Explain to have said characteristic, zone, integral body, step, operation, element and/or assembly, do not exist or additional one or more further features, zone, integral body, step, operation, element, assembly and/or its combination but do not get rid of.
Only if definition is arranged in addition, otherwise all terms used herein (comprising technical term and scientific terminology) have the meaning equivalent in meaning with those skilled in the art institute common sense.What will be further understood that is; Only if clearly definition here; Otherwise term (term that for example in general dictionary, defines) should be interpreted as in the context that has with the application and/or association area their the corresponding to meaning of the meaning, rather than explains their meaning ideally or too formally.
Fig. 1 is the diagrammatic sketch according to the semiconductor device 100 of some embodiments of the present invention.Semiconductor device 100 comprises P type semiconductor substrate 10.N type first well area 103 and 104 with desired depth forms the predetermined distance that is separated from each other on the surface of P type semiconductor substrate 10. N+ layer 113 and 114 is respectively formed on the surface of first well area 103 and 104.
When using the machine of carrying out the electrostatic discharge (ESD) test that electric charge is transmitted into display device (for example, display floater), electric charge is injected into the node N1 that is connected with panel, and therefore, the voltage of electrode A VDD raises.As a result, occur puncturing, and the hole moves to the semiconductor-based end 10 from first well area 104.Yet, comprise that the semiconductor device 100 in the guard ring zone 110 of desired depth has prevented that the hole from moving to the rising of the voltage of first well area 103 and electrode VDD.
If guard ring zone 110 is not set; Then semiconductor device 100 will have the parasitic NPN bipolar junction transistor; This parasitic NPN bipolar junction transistor with first well area 103 as emitter, with the semiconductor-based end 10 as base stage, and with first well area 104 as collector electrode.When occur puncturing, the charge movement that is injected into semiconductor device 100 by the ESD test machine is to first well area 103, and the voltage of electrode VDD is raise, thereby in semiconductor device 100, causes permanent damages or unusual.
Fig. 2 be according to other embodiment of the present invention semiconductor device 100 ' diagrammatic sketch.Semiconductor device 100 ' comprise P type semiconductor substrate 10 '.Have desired depth N type first well area 203 and 204 P type semiconductor substrate 10 ' the surface on form the predetermined distance that is separated from each other.N+ layer 213 and 214 is respectively formed on the surface of first well area 203 and 203.
Semiconductor device 100 ' be included in the N type guard ring zone 210 between first well area 203 and 204 with desired depth.Guard ring zone 210 separates the distance of being scheduled to each well area in first well area 203 and 204.Guard ring zone 210 is included in its lip-deep N+ layer 220.N+ layer 220 is connected to the VGND that is connected with voltage systematically.
Its lip- deep P+ layer 230 and 240 of the semiconductor-based end 10 ' be included in.P+ layer 230 is between 210 and first well area 203 of guard ring zone, and P+ layer 240 is between 210 and first well area 204 of guard ring zone.P+ layer 230 and 240 can and be opened predetermined distance in 204 minutes with guard ring zone 210 and first well area 203.
When using the ESD test machine that electric charge is transmitted into display device (for example, display floater), electric charge is injected into the node N2 that is connected with panel, and therefore, the voltage of electrode A VDD raises.As a result, occur to puncture, and the hole from first well area 204 move to the semiconductor-based end 10 '.Yet, comprise the semiconductor device 100 in the guard ring zone 210 of desired depth ' prevented that the hole from moving to the rising of the voltage of first well area 203 and electrode VDD.
If guard ring zone 210 is not set; Semiconductor device 100 ' will have the parasitic NPN bipolar junction transistor then; This parasitic NPN bipolar junction transistor with first well area 203 as emitter, with the semiconductor-based end 10 ' as base stage, and with first well area 204 as collector electrode.When occur puncturing, by the ESD test machine be injected into semiconductor device 100 ' charge movement to first well area 203, and the voltage of electrode VDD is raise, thereby in semiconductor device 100 ', causes permanent damages or unusual.
Fig. 3 is the curve chart that the voltage change in time of the electrode with the regional semiconductor device of guard ring is shown.Fig. 4 is the curve chart that illustrates according to the change of the voltage of the electrode of the semiconductor device 100 of some embodiments of the present invention.
With reference to Fig. 3, when when moment t1 is injected into the semiconductor device with guard ring zone with electric charge, the voltage V_AVDD of electrode A VDD raises, and the voltage V_VDD of electrode VDD raises above about 8V because of the inflow in hole.At this moment, suppose that the semiconductor device with guard ring zone is changed to the semiconductor device 100 shown in the Fig. 1 that has removed guard ring zone 110.If the electrode VDD of semiconductor device has the allowable voltage (allowable voltage) of 6V, then semiconductor device possibly break down.
With reference to Fig. 4, when when moment t2 is injected into the semiconductor device 100 that comprises guard ring zone 110 with electric charge, the voltage V_AVDD of electrode A VDD raises, but because the hole gets in the guard ring zone 110, so the voltage V_VDD of electrode VDD raises hardly.If the electrode VDD of semiconductor device 100 has the allowable voltage of 6V, then, the voltage V_VDD of electrode VDD reaches about 0.5V, so semiconductor device 100 does not have any fault because only raising.
Fig. 5 is the flow chart according to the method for the manufacturing semiconductor device of some embodiments of the present invention.In operation S100, the surface that at least two first well areas is formed the semiconductor-based end of distance reaches desired depth.At this moment, the semiconductor-based end, can have P-type conduction property, and first well area can have N type conductivity.In addition, can be with the first well area predetermined distance that is separated from each other.
Next, in operation S200, can in each first well area, form at least one second well area with desired depth.After this, in operation S300, between first well area, form guard ring zone, so that the guard ring zone separates predetermined distance with first well area with desired depth.At this moment, can form the guard ring zone darker than first well area.In addition, can the guard ring zone be connected to systematically voltage.
Fig. 6 A is the diagrammatic sketch according to the display device 500 of some embodiments of the present invention.Display device 500 comprises controller 510, gate driver circuit 520, source driver circuit or display driving circuit 530 and panel 540.
Controller 510 is provided to gate driver circuit 520 with grid control signal GCS, and enable signal SEN, clock signal of system CLK and data-signal DATA are provided to source driver circuit 530.Gate driver circuit 520 with signal be provided to gate lines G L1, GL2 ..., GLQ.
Fig. 6 B is the diagrammatic sketch that is included in the system 600 of the display device 500 shown in Fig. 6 A.With reference to Fig. 6 B, system 600 comprises display device 500 and flexible printed circuit board (FPCB) 350.System 600 is connected to systematically voltage through connector 360, therefore, can be connected to systematically voltage in the zone of the guard ring shown in Fig. 1 and Fig. 2 110 and 210.Indicated like label 320, the electric charge of ESD test machine emission can flow in the system 600, and therefore, electric charge can flow in the source electrode driver 530.
Fig. 6 C be ESD test machine emission is shown flow of charge in source electrode driver 530 and therefore be transferred to the semiconductor device 100 or 100 shown in Fig. 1 or Fig. 2 ' the diagrammatic sketch of process.Each node in the node N1_1 to N1_n shown in Fig. 6 C can be with corresponding at node N1 or the N2 shown in Fig. 1 or Fig. 2.
When the ESD test machine is transmitted into panel 540 with electric charge, flow of charge to node N1_1 to N1_n that panel 540 is connected in.Forward diode 311,313,315 and 317 through being connected respectively to node N1_1 to N1_n arrives electrode A VDD with charge transfer.At this moment, electric charge can be positive charge, and is not applied directly to electrode A VSS because of the backward diode 312,314,316 and 318 that is connected respectively to node N1_1 to N1_n.
Therefore, can prevent to cause permanent damages occurring or logic is unusual because of electric charge that the ESD test machine is injected.
Fig. 7 is the diagrammatic sketch according to the semiconductor chip of some embodiments of the present invention.Fig. 8 A and Fig. 8 B are the diagrammatic sketch that is used to realize the semiconductor device of the semiconductor chip shown in Fig. 7.
With reference to Fig. 7, semiconductor chip 700 comprises nucleus 710 and I/O (I/O) zone 720.Nucleus 710 is carried out main processing, and can comprise the integrated circuit that is used to carry out processing.I/O zone 720 is as the interface of input and output signal.I/O zone 720 can be positioned at the edge of nucleus 710, signal is input to nucleus 710 and the output signal from nucleus 710.Between nucleus 710 and I/O zone 720, can there be overdose space.
The structure of Fig. 8 A and the semiconductor device 800 and 800 shown in Fig. 8 B ' have respectively with the semiconductor device 100 and 100 shown in Fig. 1 and Fig. 2 ' structure identical.As shown in Fig. 8 A and Fig. 8 B, can use semiconductor device 800 and 800 ' in any one be implemented in the semiconductor chip 700 shown in Fig. 7.
Specifically, in guard ring zone 810 and 810 ' on every side, semiconductor device 800 and 800 ' can represent nucleus 710 and I/O zone 720 respectively.Guard ring zone 810 and 810 ' can be connected to the systematically voltage of 0V.
In the embodiment shown in Fig. 7 to Fig. 8 B, guard ring zone 810 and 810 ' be arranged between nucleus 710 and the I/O zone 720, but the invention is not restricted to these embodiment.For example, can be applied to prevent all situations according to semiconductor device of the present invention such as the ESD coupling between the piece in nucleus 710 and I/O zone 720.
As stated,,, the structure different semiconductor devices of a kind of structure and traditional semiconductor device is provided, thereby has made the permanent damages of semiconductor device or minimize unusually through introducing guard ring according to some embodiments of the present invention.
As stated,, a kind of guard ring that is used for semiconductor device is provided, thereby has prevented when the ESD test machine is injected into semiconductor device with electric charge, in semiconductor device, permanent damages to occur or logic is unusual according to some embodiments of the present invention.
Though specifically illustrate and described the present invention with reference to exemplary embodiment of the present invention; But what it should be understood by one skilled in the art that is; Under the situation that does not break away from the spirit and scope of the present invention that are defined by the claims, can carry out the various changes on form and the details at this.
Claims (20)
1. semiconductor device comprises:
The semiconductor-based end, has first conduction type;
At least two first well areas have second conduction type and desired depth in the semiconductor-based end;
At least one second well area has first conduction type and desired depth in each first well area;
The guard ring zone has second conduction type and desired depth, and the location separates predetermined distance with first well area between first well area,
Wherein, the guard ring zone is connected to ground voltage.
2. semiconductor device as claimed in claim 1, wherein, the guard ring zone is darker than first well area.
3. semiconductor device as claimed in claim 2; Wherein, Each first well area is included in the lip-deep N+ layer of each first well area, and second well area is included in the lip-deep P+ layer of second well area, and the guard ring zone is included in the lip-deep N+ layer in guard ring zone.
4. semiconductor device as claimed in claim 3, said semiconductor device also are included on the surface at the semiconductor-based end and the P+ layer between first well area and guard ring zone.
5. semiconductor device as claimed in claim 3, wherein, the lip-deep N+ layer in the lip-deep N+ layer of each first well area, the lip-deep P+ layer of second well area and guard ring zone is connected respectively to electrode.
6. semiconductor device as claimed in claim 5, wherein, the electrode that is connected to the lip-deep N+ layer in guard ring zone is connected to ground voltage.
7. semiconductor device as claimed in claim 5, wherein, electric charge is injected into an electrode in the electrode that is connected with the lip-deep N+ layer of each first well area.
8. semiconductor device as claimed in claim 1, wherein, first conduction type is the P type, second conduction type is the N type.
9. a display driving circuit comprises semiconductor device as claimed in claim 1.
10. a display device comprises display driving circuit as claimed in claim 9.
11. a method of making semiconductor device, said method comprises following operation:
First well area of at least two second conduction types formed apart from the surface at the semiconductor-based end of first conduction type reach desired depth;
In each first well area, form second well area of at least one first conduction type with desired depth;
Between first well area, form the guard ring zone that separates predetermined second conduction type distance and that have desired depth with first well area;
The guard ring zone is connected to ground voltage.
12. method as claimed in claim 11, wherein, the operation that forms the guard ring zone of second conduction type comprises and forms the guard ring zone darker than first well area.
13. method as claimed in claim 11, wherein, the operation that forms first well area of at least two second conduction types is included on the surface of each first well area and forms the N+ layer.
14. method as claimed in claim 13, wherein, the operation that forms second well area of at least one first conduction type is included on the surface of second well area and forms the P+ layer.
15. method as claimed in claim 14, wherein, the operation that forms the guard ring zone of second conduction type is included on the regional surface of guard ring and forms the N+ layer.
16. method as claimed in claim 15 wherein, is connected to electrode with the lip-deep N+ layer of each first well area, the lip-deep P+ layer of second well area and the lip-deep N+ layer in guard ring zone respectively.
17. method as claimed in claim 11, wherein, said method also is included on the surface at the semiconductor-based end and between first well area and guard ring zone, forms the P+ layer.
18. method as claimed in claim 16, wherein, the operation that connects the guard ring zone comprises that the electrode with the lip-deep N+ layer that is connected the guard ring zone is connected to ground voltage.
19. a semiconductor device comprises:
First circuit region;
The second circuit zone;
Guard ring zone is arranged between first circuit region and the second circuit zone separating the distance of being scheduled to first circuit region and second circuit zone, and forms and have desired depth,
Wherein, the guard ring zone is connected to ground voltage.
20. semiconductor device as claimed in claim 19, wherein, first circuit region is a nucleus, and the second circuit zone is the I/O zone.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020100138259A KR20110093601A (en) | 2010-02-12 | 2010-12-29 | Semiconductor device having guard-ring, display driver circuit, and display apparatus |
| KR10-2010-0138259 | 2010-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102569356A true CN102569356A (en) | 2012-07-11 |
Family
ID=46457140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104318857A Pending CN102569356A (en) | 2010-12-29 | 2011-12-16 | Semiconductor device having guard ring structure, display driver circuit, and display apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102569356A (en) |
| DE (1) | DE102011089684A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097181A (en) * | 2019-12-23 | 2021-07-09 | 南亚科技股份有限公司 | Semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796147A (en) * | 1993-08-09 | 1998-08-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of circuits driven by different power sources and formed on the same substrate |
| US6479869B1 (en) * | 1999-10-01 | 2002-11-12 | Rohm Co., Ltd. | Semiconductor device with enhanced protection from electrostatic breakdown |
| US20060113571A1 (en) * | 2004-11-29 | 2006-06-01 | Taiwan Semiconductor Manufacturing Co. | Semiconductor structure for isolating integrated circuits of various operation voltages |
| CN101577277A (en) * | 2008-05-09 | 2009-11-11 | 株式会社瑞萨科技 | Semiconductor device |
| US7667288B2 (en) * | 2004-11-16 | 2010-02-23 | Masleid Robert P | Systems and methods for voltage distribution via epitaxial layers |
-
2011
- 2011-12-16 CN CN2011104318857A patent/CN102569356A/en active Pending
- 2011-12-22 DE DE102011089684A patent/DE102011089684A1/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796147A (en) * | 1993-08-09 | 1998-08-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of circuits driven by different power sources and formed on the same substrate |
| US6479869B1 (en) * | 1999-10-01 | 2002-11-12 | Rohm Co., Ltd. | Semiconductor device with enhanced protection from electrostatic breakdown |
| US7667288B2 (en) * | 2004-11-16 | 2010-02-23 | Masleid Robert P | Systems and methods for voltage distribution via epitaxial layers |
| US20060113571A1 (en) * | 2004-11-29 | 2006-06-01 | Taiwan Semiconductor Manufacturing Co. | Semiconductor structure for isolating integrated circuits of various operation voltages |
| CN101577277A (en) * | 2008-05-09 | 2009-11-11 | 株式会社瑞萨科技 | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097181A (en) * | 2019-12-23 | 2021-07-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN113097181B (en) * | 2019-12-23 | 2024-03-22 | 南亚科技股份有限公司 | Semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102011089684A1 (en) | 2012-07-05 |
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Application publication date: 20120711 |