CN102569209A - Anti-cracking structure - Google Patents
Anti-cracking structure Download PDFInfo
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- CN102569209A CN102569209A CN201010610019XA CN201010610019A CN102569209A CN 102569209 A CN102569209 A CN 102569209A CN 201010610019X A CN201010610019X A CN 201010610019XA CN 201010610019 A CN201010610019 A CN 201010610019A CN 102569209 A CN102569209 A CN 102569209A
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Abstract
The invention provides an anti-cracking structure, which is positioned on a semiconductor substrate in a wafer cutting channel. A wafer is spaced into a plurality of chips along the cutting channel; the anti-cracking structure has two parallel arranged lines along a direction of edges of the chips; each line consists of metal lines and connection hole lines, which are staggered with one another in a longitudinal direction; and each pair of metal line and connection hole line, which are arranged on the cutting channel alternatively corresponds to each layer of chips. By adopting the anti-cracking structure, the problems of uneven ground material layers of the chips and easy damage to the chips during cutting are solved.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly a kind of anticracking structure.
Background technology
At present; Be accompanied by the develop rapidly of semiconductor fabrication; Semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, and wafer develops towards higher component density, high integration direction, and the quantity of chip increases gradually on the wafer.
In manufacture of semiconductor, normally wafer is cut into chip one by one, then these chips are made the different semiconductor package of function.Fig. 1 is the vertical view of wafer.Wafer is made up of a plurality of chips 101, and 101 of chips then are separated by with Cutting Road (scribe line) 102.Each chip 101 forms element, lamination, interconnection line and weld pad etc. through technologies such as deposition, little shadow, etching, doping and heat treatments on Semiconductor substrate; Cutting Road 102 is used to prolong and is divided into chip one by one here, so there is not function element.
Through sawing along Cutting Road; Cut into single chip to wafer,, carry out the cleaning of cutting blade after need the entire wafer cutting being accomplished again according to prior art; Increase along with number of chips on the wafer; A wafer has not been cut toward contact, just sticked a lot of metal fragments on the cutting blade, caused cutting blade to use.These metal fragments generally are the conduction redundancy structures that is on the Cutting Road; Constitute by metallic copper; Be used to increase the pattern density of Cutting Road blank region; Make that pattern density and the pattern density on the chip on the Cutting Road are symmetrical, when preventing each material layer on grinding chip, uneven problem occurs grinding.
It should be noted that existing a kind of method that cutting blade just can't use in the cutting of also not accomplishing a wafer that solves, is exactly that the conduction redundancy structure on the Cutting Road is removed; When cutting blade is along the Cutting Road sawing like this; Insulating barrier on the cutting Cutting Road still, even more serious problem will occur at this moment: on the one hand fully; Owing to do not have the conduction redundancy structure on the Cutting Road; The Cutting Road zone is different than the chip area height, so during each material layer on grinding chip, the uneven problem of described grinding before occurring again; On the other hand, only there is insulating barrier on the Cutting Road, so when cutting; The stress that cutting blade produced makes the very fast of insulating barrier splitting; Be easy to extend to chip area, chip area is destroyed, even chip edge is provided with sealing ring (seal ring); Also will be used to probably protect the sealing ring of chip to wash away, and then be corrupted to chip.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: overcome each material layer unevenness and chip easy ruined problem when cutting on the grinding chip simultaneously.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention provides a kind of anticracking structure; Be positioned on the Semiconductor substrate of wafer cutting path; Along said Cutting Road wafer is partitioned into a plurality of chips; This structure is two lines that are arranged in parallel along chip length of side direction, and metal wire and connecting hole line that every line is arranged by alternatively up and down constitute, wherein on the Cutting Road alternately each of arrangement to metal wire and connecting hole line and the corresponding setting of each layer on the chip.
Said connecting hole line is the many rows that are positioned at row of one under the same metal wire or parallel arranged.
Each layer on the said chip to down and on comprise a plurality of metal interconnecting layers and aluminum cushion layer successively, wherein each metal interconnecting layer comprises groove and the connecting hole that is filled with metal, aluminum cushion layer comprises groove and the connecting hole that is filled with metallic aluminium.
Spacing between said two lines that are arranged in parallel is greater than 40 microns.
The width of said every line is 2～10 microns.
Visible by above-mentioned technical scheme; Anticracking structure of the present invention; Be two lines that are arranged in parallel along chip length of side direction; And the certain distance in interval between these two lines, blade can carry out the cutting of chip just under the situation that does not contact the anticracking structure, be not attached on the blade so do not have metal fragment; And two lines that are arranged in parallel have certain pattern density, when having overcome each material layer on grinding chip, uneven problem occurs grinding; The anticracking structure to go up down by metal wire and connecting hole line alternately arrange be arranged at chip around, can protect chip when cutting, not to be damaged well.
Description of drawings
Fig. 1 is the vertical view of wafer.
Fig. 2 is the wafer sketch map that is provided with anticracking structure of the present invention.
Fig. 3 is the profile of embodiment of the invention anticracking structure.
Fig. 4 is the profile of preferred embodiment of the present invention anticracking structure.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The present invention utilizes sketch map to describe in detail; When the embodiment of the invention was detailed, for the ease of explanation, the sketch map of expression structure can be disobeyed general ratio and done local the amplification; Should be with this as to qualification of the present invention; In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
The present invention is provided with anticracking structure (crack stop structure) in Cutting Road, this structure is two lines that are arranged in parallel along chip 101 length of side directions, and is as shown in Figure 2.Fig. 2 is the wafer sketch map that is provided with anticracking structure of the present invention.The width of Cutting Road 102 is generally at 50～80 microns, and the spacing between two lines 200 that the present invention is arranged in parallel is greater than 40 microns, and the width of every line is 2～10 microns.Can know according to common practise; The cutter seam width of cutting blade is approximately 20 microns; Therefore the spacing between two lines of anticracking structure of the present invention is greater than 40 microns; So that the cutting of cutting blade can not be in the conduction redundancy structure on the Cutting Road in prior art, the cutting of process cutting blade is attached on the blade; And two lines that are arranged in parallel have certain pattern density, when having overcome each material layer on grinding chip, uneven problem occurs grinding.
Fig. 3 is the profile of embodiment of the invention anticracking structure.According to prior art, chip comprises sandwich construction, to down and on include source region (AA), a plurality of metal interconnecting layer and aluminium pad (Al pad) layer successively.Wherein for example form by the connecting hole and the groove of metallic copper by being filled with metal for each metal interconnecting layer.The aluminum cushion layer of top layer is made up of connecting hole that is filled with metallic aluminium and groove, just compares the size of groove with metal interconnecting layer and wants big, is used to connect the chip external circuit.Anticracking structure and chip that the present invention is positioned at Cutting Road form simultaneously; Every line of anticracking structure; Be positioned on the Semiconductor substrate of Cutting Road; Metal wire and the connecting hole line arranged by alternatively up and down constitute, wherein alternately arrange on the Cutting Road each to metal wire and connecting hole line and the corresponding setting of each layer on the chip, a plurality of metal interconnecting layers and aluminum cushion layer that each on the chip comprises on layer referring to descending successively.With the metal wire and the connecting hole line that comprise in the corresponding Cutting Road of aluminum cushion layer that aluminium is filled; With comprise metal filled metal wire and connecting hole line in the corresponding Cutting Road of metal interconnecting layer; Particularly; With comprise first metal wire and the first connecting hole line in the corresponding Cutting Road of first metal interconnecting layer; With comprise second metal wire and the second connecting hole line in the corresponding Cutting Road of second metal interconnecting layer, and the like, and comprise top wire and top layer connecting hole line in the corresponding Cutting Road of top-level metallic interconnection layer.Alternatively up and down is arranged the metal wire that connects and is established in the insulating barrier in Cutting Road as a stifled solid wall with the connecting hole line; And can know that according to Fig. 2 the anticracking structure is arranged at around the chip, when diced chip; Even the stress that cutting blade produced makes the very fast of insulating barrier splitting; Splitting also can be prevented from anticracking structure place, is unlikely to extend to chip area, that is to say anticracking structure of the present invention well the protective core panel region time be not damaged in cutting.
Need to prove, for how forming the anticracking structure, be identical with the method that forms a plurality of metal interconnecting layers and aluminum cushion layer.For instance, when forming first metal interconnecting layer, at first etching first groove and first connecting hole in insulating barrier are filled metal then, and are ground in first groove and first connecting hole, flush with insulating barrier through the metal after grinding.In like manner; When first metal wire that forms the anticracking structure and the first connecting hole line; At first etching first metallic channel is connected hole slot with first in the insulating barrier of Cutting Road, is connected with first at first metallic channel then and fills metal in the hole slot, and grind; Metal through after grinding flushes with insulating barrier, thereby forms first metal wire and the first connecting hole line.Wherein, the connecting hole line width can be ignored basically, so the width of the metal wire that the present invention limits is 2～10 microns.
Be not damaged when cutting for protecting chip better; Prevent that promptly splitting from extending to chip area; Preferably pairing connecting hole line is set to many rows of parallel arranged under each metal wire; As shown in Figure 4, Fig. 4 is the profile of preferred embodiment of the present invention anticracking structure, and the connecting hole line that is positioned among the figure under the same metal wire is two rows.Many row's connecting hole lines are compared the extension that can stop splitting better with single connecting hole line.
To sum up; Anticracking structure of the present invention is two lines that are arranged in parallel along chip length of side direction, and the certain distance in interval between these two lines; Blade can carry out the cutting of chip just under the situation that does not contact the anticracking structure, be not attached on the blade so do not have metal fragment; And two lines that are arranged in parallel have certain pattern density, when having overcome each material layer on grinding chip, uneven problem occurs grinding; The anticracking structure to go up down by metal wire and connecting hole line alternately arrange be arranged at chip around, can protect chip when cutting, not to be damaged well.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (5)
1. anticracking structure; Be positioned on the Semiconductor substrate of wafer cutting path; Along said Cutting Road wafer is partitioned into a plurality of chips, it is characterized in that this structure is two lines that are arranged in parallel along chip length of side direction; Metal wire and connecting hole line that every line is arranged by alternatively up and down constitute, wherein on the Cutting Road alternately each of arrangement to metal wire and connecting hole line and the corresponding setting of each layer on the chip.
2. structure as claimed in claim 1 is characterized in that, said connecting hole line is the many rows that are positioned at row of one under the same metal wire or parallel arranged.
3. structure as claimed in claim 2; It is characterized in that; Each layer on the said chip to down and on comprise a plurality of metal interconnecting layers and aluminum cushion layer successively, wherein each metal interconnecting layer comprises groove and the connecting hole that is filled with metal, aluminum cushion layer comprises groove and the connecting hole that is filled with metallic aluminium.
4. structure as claimed in claim 1 is characterized in that, the spacing between said two lines that are arranged in parallel is greater than 40 microns.
5. structure as claimed in claim 2 is characterized in that, the width of said every line is 2～10 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010610019.XA CN102569209B (en) | 2010-12-28 | 2010-12-28 | Anti-cracking structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010610019.XA CN102569209B (en) | 2010-12-28 | 2010-12-28 | Anti-cracking structure |
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| Publication Number | Publication Date |
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| CN102569209A true CN102569209A (en) | 2012-07-11 |
| CN102569209B CN102569209B (en) | 2015-01-28 |
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| CN201010610019.XA Active CN102569209B (en) | 2010-12-28 | 2010-12-28 | Anti-cracking structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752325A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof and method for improving cutting yield of wafer |
| CN105514150A (en) * | 2016-01-22 | 2016-04-20 | 英麦科（厦门）微电子科技有限公司 | Anti-cracking wafer structure and scribing method |
| WO2018213937A1 (en) * | 2017-05-25 | 2018-11-29 | Orpyx Medical Technologies Inc. | Flexible circuit package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060220250A1 (en) * | 2005-03-14 | 2006-10-05 | Kim Sun-Oo | Crack stop and moisture barrier |
| US20070293019A1 (en) * | 2006-06-15 | 2007-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of die sawing and structures formed thereby |
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101685817A (en) * | 2008-09-22 | 2010-03-31 | 恩益禧电子股份有限公司 | Semiconductor chip and semiconductor wafer |
-
2010
- 2010-12-28 CN CN201010610019.XA patent/CN102569209B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060220250A1 (en) * | 2005-03-14 | 2006-10-05 | Kim Sun-Oo | Crack stop and moisture barrier |
| US20070293019A1 (en) * | 2006-06-15 | 2007-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of die sawing and structures formed thereby |
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101685817A (en) * | 2008-09-22 | 2010-03-31 | 恩益禧电子股份有限公司 | Semiconductor chip and semiconductor wafer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752325A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof and method for improving cutting yield of wafer |
| CN104752325B (en) * | 2013-12-30 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof, the method for improving wafer cutting yield rate |
| CN105514150A (en) * | 2016-01-22 | 2016-04-20 | 英麦科（厦门）微电子科技有限公司 | Anti-cracking wafer structure and scribing method |
| WO2018213937A1 (en) * | 2017-05-25 | 2018-11-29 | Orpyx Medical Technologies Inc. | Flexible circuit package |
| US11026325B2 (en) | 2017-05-25 | 2021-06-01 | Orpyx Medical Technologies Inc. | Flexible circuit package |
| US11659657B2 (en) | 2017-05-25 | 2023-05-23 | Orpyx Medical Technologies Inc. | Flexible circuit package |
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| Publication number | Publication date |
|---|---|
| CN102569209B (en) | 2015-01-28 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121116 |
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Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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