CN102569190B - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN102569190B CN102569190B CN201210029658.6A CN201210029658A CN102569190B CN 102569190 B CN102569190 B CN 102569190B CN 201210029658 A CN201210029658 A CN 201210029658A CN 102569190 B CN102569190 B CN 102569190B
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Abstract
The invention provides a method for manufacturing a pixel structure. The method comprises the following steps of: forming a thin film transistor on a substrate, and forming an insulating layer on the substrate so as to cover the substrate and the thin film transistor; patterning the insulating layer by utilizing a semi-dimmable photomask so as to form a raised pattern, a recessed pattern connected with the raised pattern, and an opening positioned in the recessed pattern, wherein the thickness of the raised pattern is greater than that of the recessed pattern, and the opening penetrates through the recessed pattern to expose a drain of the thin film transistor; forming a light-transmitting conductive layer so as to cover the raised pattern and the recessed pattern and fill the patterns in the opening; forming a flat layer to cover the light-transmitting conductive layer; and removing part of flat layer positioned on the raised pattern, part of light-transmitting conductive layer and part of flat layer in the opening so as to form a pixel electrode pattern on the light-transmitting conductive layer. The invention also provides the pixel structure manufactured by the method.
Description
Technical field
The invention relates to a kind of image element structure and preparation method thereof, and particularly about a kind of image element structure that uses half mode optical cover process and preparation method thereof.
Background technology
Social multimedia technology is quite flourishing now, is mostly indebted to the progress of semiconductor element and display unit.With regard to display, have that high image quality, space utilization efficiency are good, the Thin Film Transistor-LCD of low consumpting power, the advantageous characteristic such as radiationless becomes the main flow in market gradually.Generally speaking, Thin Film Transistor-LCD is consisted of thin-film transistor array base-plate, colored filter substrate and the liquid crystal layer that is sandwiched between this two substrates.
Known thin-film transistor array base-plate comprises multi-strip scanning line, many data lines and a plurality of image element structure.In detail, each image element structure comprises thin-film transistor and pixel electrode.Thin-film transistor comprises the gate that is electrically connected with scan line, be positioned at channel layer on gate, be positioned at source electrode and drain on channel layer.Source electrode and data line are electrically connected.Drain and pixel electrode are electrically connected.
In known technology, while making image element structure must by be deposited on rete on substrate respectively patterning to form required element.Furthermore, known image element structure is patterned in order and is formed by the first metal layer, the first insulating barrier, semiconductor layer, the second metal level, the second insulating barrier and transparency conducting layer haply.In detail, after the first metal layer is patterned, form scan line and gate.After semiconductor layer is patterned, form channel layer.After the second metal level is patterned, the source electrode and the drain that form data line and cover the relative both sides of channel layer.After the second metal level is patterned, the second insulating barrier is formed on data line, source electrode and drain top.Afterwards, the second insulating barrier is patterned to form opening.This opening runs through the second insulating barrier and exposes the drain of thin-film transistor.Then, transparency conducting layer is formed on the second insulating barrier.Finally, patterned transparent conductive layer is to form pixel electrode pattern, and wherein pixel electrode pattern sees through the drain electric connection of described opening and thin-film transistor.
Because above-mentioned a plurality of retes (being the first metal layer, semiconductor layer, the second metal level, the second insulating barrier and transparency conducting layer) must be patterned respectively, so the making of known image element structure need be used multiple tracks optical cover process.Yet every one optical cover process all needs to expend time in and money, therefore under the considering of time and cost, how to reduce light shield quantity, for current research staff, desire most ardently one of problem of solution in fact.
Summary of the invention
The invention provides a kind of manufacture method of image element structure, it has advantages of the light shield quantity of minimizing and reduces manufacturing cost.
The invention provides a kind of image element structure, its low cost of manufacture.
The manufacture method that the invention provides a kind of image element structure, comprises the following steps.Substrate is provided, and forms thin-film transistor on substrate.On substrate, form again insulating barrier, with covered substrate and thin-film transistor.Then, utilize half mode mask pattern insulating barrier, with the opening that forms raised design, the recess patterns being connected with raised design and be arranged in recess patterns.The thickness of raised design is greater than the thickness of recess patterns.Opening runs through recess patterns and exposes the drain of thin-film transistor.Then, on substrate, form light transmission conductive layer, to cover raised design, recess patterns and to insert opening.Then, form flatness layer, to cover light transmission conductive layer.Finally, remove the part flatness layer of the part flatness layer, part light transmission conductive layer and the opening that are arranged on raised design, and make light transmission conductive layer form a pixel electrode pattern.
The invention provides a kind of image element structure, comprise substrate, thin-film transistor, insulating barrier and pixel electrode pattern.Thin-film transistor is configured on substrate.Insulating barrier cover film transistor.Insulating barrier comprises raised design and the recess patterns being connected with raised design.The thickness of raised design is greater than the thickness of recess patterns.Recess patterns has opening.This opening exposes the drain of thin-film transistor.Pixel electrode pattern arrangement is on insulating barrier and insert in opening, and is electrically connected with the drain of thin-film transistor.
In one embodiment of this invention, aforesaidly remove the part flatness layer that is positioned on raised design and part light transmission conductive layer, and the method that makes light transmission conductive layer form pixel electrode pattern comprises the following steps.Remove the part flatness layer being positioned on raised design, to expose part light transmission conductive layer.Remove the part light transmission conductive layer being exposed by flatness layer, and form pixel electrode pattern.
In one embodiment of this invention, the aforesaid part flatness layer being positioned on raised design that removes, comprises to expose the step of part light transmission conductive layer: flatness layer is carried out to ashing (Ashing) processing procedure.
In one embodiment of this invention, the aforesaid insulating barrier that forms on substrate be take the step of covered substrate and thin-film transistor as forming insulating barrier with comprehensively covered substrate and thin-film transistor on substrate.
In one embodiment of this invention, aforesaid insulating barrier has relative first surface and second surface, and the first surface of insulating barrier contacts with thin-film transistor, and the second surface of insulating barrier is essentially the plane parallel with substrate.
In one embodiment of this invention, the material of aforesaid insulating barrier comprises organic photoresistance.
In one embodiment of this invention, the aforesaid light transmission conductive layer that forms on substrate comprises with the step that covers raised design, recess patterns and insert opening: on substrate, form light transmission conductive layer with comprehensive covering raised design, recess patterns and opening.
In one embodiment of this invention, aforesaid formation flatness layer comprises that to cover the step of light transmission conductive layer formation flatness layer is with comprehensive covering light transmission conductive layer.
In one embodiment of this invention, aforesaid flatness layer has relative first surface and a second surface, and the first surface of flatness layer contacts with light transmission conductive layer, and the second surface of flatness layer is essentially the plane parallel with substrate.
In one embodiment of this invention, aforesaid pixel electrode pattern covers recess patterns and do not cover raised design.
In one embodiment of this invention, the orthographic projection on substrate overlaps in fact with recess patterns in the orthographic projection of aforesaid pixel electrode pattern on substrate.
In one embodiment of this invention, the transistorized channel layer of aforesaid raised design cover film, and the transistorized drain of recess patterns cover film and the not transistorized channel layer of cover film.
In one embodiment of this invention, aforesaid image element structure more comprises data line interlaced with each other and scan line, and wherein the source electrode of data line and thin-film transistor is electrically connected, and the gate of scan line and thin-film transistor is electrically connected.
In one embodiment of this invention, the transistorized channel layer of aforesaid raised design cover film, data line and scan line.
Based on above-mentioned, in image element structure processing procedure of the present invention, utilize half mode mask pattern insulating barrier, to form raised design and the recess patterns with high low head.Utilize described raised design and recess patterns definable to go out pixel electrode pattern, and then make to make the required light shield quantity of image element structure of the present invention and can reduce.Thus, the cost of manufacture of image element structure of the present invention just can reduce effectively.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Accompanying drawing explanation
Figure 1A to Figure 12 A looks schematic diagram in the making flow process of image element structure of one embodiment of the invention.
Figure 1B to Figure 12 B is respectively the hatching line A-A ' generalized section of corresponding Figure 1A to Figure 12 A.
In figure: 100 image element structures, 110 substrates, 120 thin-film transistors, 121 scan lines, 121a gate, 122 lock insulating barriers, 124 channel layers, 126a drain, 126b source electrode, 126c data line, 130 insulating barriers, 130a, 160a first surface, 130b, 160b second surface, 132 raised designs, 134 recess patterns, 140a, 140b, 140c pattern, 150 light transmission conductive layer, 150 ' pixel electrode pattern, 160 flatness layers, W opening, H1, H1 ', H2 thickness, A-A ' hatching line.
Embodiment
the making flow process of image element structure
Figure 1A to Figure 12 A looks schematic diagram in the making flow process of image element structure of one embodiment of the invention.Figure 1B to Figure 12 B is respectively corresponding Figure 1A to Figure 12 A along the generalized section of hatching line A-A '.Be noted that in Figure 1A to Figure 12 A, if when the border of rete is overlapping with other retes in fact, in top view, only indicate the rete that is positioned at the superiors.Therefore, Figure 1A to Figure 12 A has omitted the sign of partial component, therefore referring to corresponding generalized section (being Figure 1B to Figure 12 B).To coordinate Figure 1A to Figure 12 A and 1B to Figure 12 B to describe the making flow process of the image element structure of one embodiment of the invention in detail below.
Please also refer to Figure 1A and Figure 1B, first, on substrate 110, form the first metal layer (not illustrating).Then, the scan line 121 of this first metal layer of patterning to form gate 121a and to be electrically connected with gate 121a.In the present embodiment, gate 121a can be the some of scan line 121.Yet the present invention is as limit, in other embodiments, gate 121a also can be for by the outward extending branch of scan line 121.In the present embodiment, scan line 121 is generally to use metal material with gate 121a.Yet, the invention is not restricted to this, according to other embodiment, scan line 121 also can be used other electric conducting materials with gate 121a.For example: the nitrogen oxide of the nitride of alloy, metal material, the oxide of metal material, metal material or the stack layer of metal material and other electric conducting material.
Please refer to Fig. 2 A and Fig. 2 B, then, form lock insulating barrier 122 on substrate 110.In the present embodiment, lock insulating barrier 122 is for example comprehensively covered substrate 110, gate 121a and scan line 121.In the present embodiment, the material of lock insulating barrier 122 (for example: the stack layer of silica, silicon nitride, silicon oxynitride or above-mentioned at least two kinds of materials), organic material or above-mentioned combination can be inorganic material.
Please refer to Fig. 3 A and Fig. 3 B, then, on lock insulating barrier 122, form semiconductor layer (not illustrating).Then, this semiconductor layer of patterning is to form channel layer 124.Channel layer 124 is overlapping with gate 121a.The material of channel layer 124 can be the material of crystal silicon, amorphous silicon, polysilicon, oxide etc.
Please refer to Fig. 4 A and Fig. 4 B, then, form the second metal level (not illustrating) to cover channel layer 124 and substrate 110.Then, the data line 126c of this second metal level of patterning to form source electrode 126b, drain 126a and to be electrically connected with source electrode 126b.So far, thin-film transistor 120 just tentatively completes.It should be noted that, the method for above-mentioned formation thin-film transistor 120 be the method that forms end gate (bottom gate) thin-film transistor be example.Yet, the invention is not restricted to this, in other embodiments, thin-film transistor 120 also can be top gate (top gate) thin-film transistor or other forms of thin-film transistor.The method that forms top gate (top gate) thin-film transistor or other forms of thin-film transistor for this reason field has common knowledge and knows, in this just detailed description no longer.
Referring to Fig. 5 A and Fig. 5 B, then, form an insulating barrier 130 with covered substrate 110 and thin-film transistor 120.In the present embodiment, comprehensively covered substrate 110 and thin-film transistor 120 of insulating barrier 130.In detail, insulating barrier 130 has a relative first surface 130a and a second surface 130b, wherein the first surface 130a of insulating barrier 130 contacts with thin-film transistor 120, and the second surface 130b of insulating barrier 130 can be parallel with substrate 110 in fact plane.In the present embodiment, the material of insulating barrier 130 can be organic photoresistance, and this organic photoresistance can be eurymeric photoresistance.Yet, the invention is not restricted to this, in other embodiments, organic photoresistance also can be minus photoresistance.In addition, the thickness H1 of insulating barrier 130 is for example 2 microns to 3 microns.
Please refer to Fig. 6 A and Fig. 6 B, utilize half this insulating barrier 130 of mode light shield 140 patternings.In the present embodiment particularly, this half mode light shield 140 for example has pattern 140a, pattern 140b and the pattern 140c of three kinds of different printing opacity degree, and wherein the light transmittance of pattern 140b is for example between pattern 140a and pattern 140c.Furthermore, pattern 140a is for example complete printing opacity, and pattern 140c is for example light tight, and the printing opacity degree of pattern 140b is for example in the middle of pattern 140a and pattern 140c.
Please refer to Fig. 7 A and Fig. 7 B, be used in after 130 exposures of 140 pairs of insulating barriers of half mode light shield, the engineering of developing is so that the opening W that insulating barrier 130 forms raised designs 132, the recess patterns 134 being connected with raised design 132 and is arranged in recess patterns 134, and its split shed W runs through recess patterns 134 and exposes the drain 126a of thin-film transistor 120.In more detail, in the present embodiment, opening W can utilize the pattern 140a that light transmittance is the highest to form, and recess patterns 134 can utilize light transmittance time high pattern 140b to form, and raised design 132 can utilize the pattern 140c that light transmittance is minimum to form.In the present embodiment, the channel layer 124 of raised design 132 cover film transistors 120, data line 126b and scan line 121.The drain 126a of recess patterns 134 cover film transistors 120 and the not channel layer 124 of cover film transistor 120.In addition, the thickness H1 of raised design 132 is greater than the thickness H1 ' of recess patterns 134.
Please refer to Fig. 8 A and Fig. 8 B, then, on substrate 110, form light transmission conductive layer 150 to cover raised design 132, recess patterns 134 and to insert in opening W.In the present embodiment, light transmission conductive layer 150 is for example comprehensive covering raised design 132, recess patterns 134 and opening W.In the present embodiment, the material of light transmission conductive layer 150 can be metal oxide, for example indium tin oxide, indium-zinc oxide, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide or other suitable oxide or the above-mentioned at least stack layer of the two.
Referring to Fig. 9 A and Fig. 9 B, then, on substrate 110, form a flatness layer 160, to cover light transmission conductive layer 150.In the present embodiment, the comprehensive covering light transmission conductive layer 150 of flatness layer 160.The material of the flatness layer 160 of the present embodiment is for example inorganic photoresistance, that is known technology for patterning the first metal layer and the second metal level to form respectively the photoresistance of gate and source electrode, drain but the present invention not as limit.In addition, flatness layer 160 is for example comprehensive covering light transmission conductive layer 150.Particularly, flatness layer 160 has relative first surface 160a and a second surface 160b.The first surface 160a of flatness layer 160 contacts with light transmission conductive layer 150, and the second surface 160b of flatness layer 160 can be and is essentially a plane parallel with substrate 110.In the present embodiment, the thickness H2 of flatness layer 160 can be between being for example 1 micron to 2.2 microns.
Referring to Figure 10 A and Figure 10 B, then, can carry out the removal step of above-mentioned inorganic photoresistance.In the present embodiment, the method for the inorganic photoresistance of above-mentioned removal is for example that flatness layer 160 is carried out to an ashing (Ashing) processing procedure.In detail, in the present embodiment, can utilize in electric paste etching (Plasma Etching), the method for Ions Bombardment (ion-bombardment) removes to remove the first half of flatness layer 160.Remove after the first half of flatness layer 160, the part flatness layer 160 being positioned on raised design 132 is removed, and exposes part light transmission conductive layer 150.On the other hand, residual fraction flatness layer 160 still in recess patterns 134.
Please refer to Figure 11 A and Figure 11 B, then, remove the part light transmission conductive layer 150 being exposed by flatness layer 160, and make light transmission conductive layer 150 form pixel electrode pattern 150 '.In the present embodiment, can remove part light transmission conductive layer 150 by etching mode.Above-mentioned etching mode is not limited to dry ecthing or wet etching.In addition, because the part light transmission conductive layer 150 on raised design 132 is now removed, therefore expose raised design 132.
Please refer to Figure 12 A and Figure 12 B, then, the removable flatness layer 160 that remains in the part in recess patterns 134 and opening W, and expose pixel electrode pattern 150 '.In detail, in the present embodiment, can utilize photoresistance stripping (photo resist stripping) agent to remove and remain in the part flatness layer 160 in recess patterns 134 and opening W.In this, the image element structure 100 of the present embodiment just completes.
It is worth mentioning that, in image element structure 100 processing procedures of the present embodiment, utilize half mode light shield 140 patterned insulation layers 130, to form the raised design 132 and recess patterns 134 with high low head.And utilize recess patterns 134 to define pixel electrode pattern 150 ', and then the required light shield quantity of image element structure 100 of making the present embodiment is reduced.Thus, the cost of manufacture of the image element structure 100 of the present embodiment just can reduce effectively.In addition, the above-mentioned method that defines pixel electrode pattern 150 ' with the raised design 132 with high low head and recess patterns 134 also can be applicable in any structure that needs insulating barrier and pixel electrode, for example, in the processing procedure of contact panel, semi-penetration semi-reflective panel, IPS panel or FFS panel.
Please refer to Figure 12 A and Figure 12 B, the image element structure 100 of the present embodiment comprises substrate 110, thin-film transistor 120, insulating barrier 130 and pixel electrode pattern 150 '.Thin-film transistor 120 is configured on substrate 110.Thin-film transistor 120 comprises gate 121a, lock insulating barrier 122, channel layer 124, source electrode 126b and drain 126a.
As shown in Figure 12 A, the image element structure 100 of the present embodiment can further comprise data line 126c and scan line 121.The source electrode 126b of data line 126c and thin-film transistor 120 is electrically connected.Scan line 121 is electrically connected with the gate 121a of thin-film transistor 120.
The insulating barrier 130 cover film transistors 120 of the present embodiment.Furthermore, insulating barrier 130 comprises raised design 132 and recess patterns 134.Recess patterns 134 is connected with raised design 132.Raised design 132 has the drain 126a that exposes thin-film transistor 120.In more detail, the channel layer 124 of raised design 132 cover film transistors 120, data line 126c and scan line 121.The drain 126a of recess patterns 134 cover film transistors 120 and the not channel layer 124 of cover film transistor 120.In addition, the thickness H1 of raised design 132 is greater than the thickness H1 ' of recess patterns 134.
The pixel electrode pattern 150 ' of the present embodiment is configured on insulating barrier 130 and inserts in opening W, so that pixel electrode pattern 150 ' is electrically connected with the drain 126a of thin-film transistor 120.It should be noted that pixel electrode pattern 150 ' to cover recess patterns 134 and do not cover raised design 132.In addition, the orthographic projection of pixel electrode pattern 150 ' on substrate 110 overlaps in fact with the orthographic projection of recess patterns 134 on substrate 110.In the processing procedure of the image element structure 100 of the present embodiment, can utilize the raised design 132 with high low head to define pixel electrode pattern 150 ' with recess patterns 134, therefore make the required light shield quantity of image element structure 100 of the present embodiment, can reduce.In other words, the image element structure 100 of the present embodiment has the advantage of low cost of manufacture.
In sum, in the image element structure processing procedure of one embodiment of the invention, utilize half mode mask pattern insulating barrier, to form raised design and the recess patterns with high low head.Utilize described raised design and recess patterns definable to go out pixel electrode pattern, and then the required light shield quantity of image element structure of making one embodiment of the invention can be reduced.Thus, the cost of manufacture of the image element structure of one embodiment of the invention just can reduce effectively.In addition the image element structure made from the method, also has the advantage of low cost of manufacture.
Although the present invention discloses as above with execution mode; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (16)
1. a manufacture method for image element structure, is characterized in that, comprising:
One substrate is provided;
On this substrate, form a thin-film transistor;
On this substrate, form an insulating barrier, to cover this substrate and this thin-film transistor;
Utilize half this insulating barrier of mode mask patternization, with an opening that forms a raised design, the recess patterns being connected with this raised design and be arranged in this recess patterns, wherein the thickness of this raised design is greater than the thickness of this recess patterns, and this opening runs through this recess patterns and exposes a drain of this thin-film transistor;
On this substrate, form a light transmission conductive layer, to cover this raised design, this recess patterns and to insert this opening;
Form a flatness layer, to cover this light transmission conductive layer; And
Remove the part flatness layer of this flatness layer of part, this light transmission conductive layer of part and this opening that are arranged on this raised design, and make this light transmission conductive layer form a pixel electrode pattern.
2. the manufacture method of image element structure according to claim 1, is characterized in that, remove this flatness layer of part and this light transmission conductive layer of part of being positioned on this raised design, and the step that makes this light transmission conductive layer form this pixel electrode pattern comprises:
Remove this flatness layer of part being positioned on this raised design, to expose part light transmission conductive layer; And
Remove this part light transmission conductive layer being exposed by this flatness layer, and form this pixel electrode pattern.
3. the manufacture method of image element structure according to claim 2, is characterized in that, removes this flatness layer of part being positioned on this raised design, comprises: this flatness layer is carried out to an ashing processing procedure to expose the step of part light transmission conductive layer.
4. the manufacture method of image element structure according to claim 1, is characterized in that: on this substrate, form this insulating barrier and comprise to cover the step of this substrate and this thin-film transistor:
On this substrate, form this insulating barrier comprehensively to cover this substrate and this thin-film transistor.
5. the manufacture method of image element structure according to claim 1, it is characterized in that: this insulating barrier has a relative first surface and a second surface, this first surface of this insulating barrier contacts with this thin-film transistor, and this second surface of this insulating barrier is essentially a plane parallel with this substrate.
6. the manufacture method of image element structure according to claim 1, is characterized in that, the material of this insulating barrier comprises: an organic photoresistance.
7. the manufacture method of image element structure according to claim 1, is characterized in that: this raised design covers a channel layer of this thin-film transistor, and this recess patterns covers a drain of this thin-film transistor and do not cover this channel layer of this thin-film transistor.
8. the manufacture method of image element structure according to claim 1, is characterized in that: on this substrate, form this light transmission conductive layer and comprise with the step that covers this raised design, this recess patterns and insert this opening:
On this substrate, form this light transmission conductive layer with this raised design of comprehensive covering, this recess patterns and this opening.
9. the manufacture method of image element structure according to claim 1, is characterized in that: form this flatness layer and comprise to cover the step of this light transmission conductive layer:
Form this flatness layer with this light transmission conductive layer of comprehensive covering.
10. the manufacture method of image element structure according to claim 9, it is characterized in that: this flatness layer has relative first surface and a second surface, this first surface of this flatness layer contacts with this light transmission conductive layer, and this second surface of this flatness layer is essentially a plane parallel with this substrate.
11. 1 kinds of image element structures, is characterized in that, comprising:
One substrate;
One thin-film transistor, is configured on this substrate;
One insulating barrier, covers this thin-film transistor, and this insulating barrier comprises:
One raised design; And
One recess patterns, is connected with this raised design, and wherein the thickness of this raised design is greater than the thickness of this recess patterns, and this recess patterns has an opening, and this opening exposes a drain of this thin-film transistor; And
One pixel electrode pattern, is configured on this insulating barrier and inserts in this opening, and is electrically connected with this drain of this thin-film transistor.
12. image element structures according to claim 11, is characterized in that: this this recess patterns of pixel electrode pattern covers and do not cover this raised design.
13. image element structures according to claim 11, is characterized in that: this pixel electrode pattern orthographic projection on this substrate overlaps in fact with the orthographic projection of this recess patterns on this substrate.
14. image element structures according to claim 11, is characterized in that: this raised design covers a channel layer of this thin-film transistor, and this recess patterns covers a drain of this thin-film transistor and do not cover this channel layer of this thin-film transistor.
15. image element structures according to claim 11, it is characterized in that, more comprise: a data line interlaced with each other and one scan line, wherein the one source pole of this data line and this thin-film transistor is electrically connected, and a gate of this scan line and this thin-film transistor is electrically connected.
16. image element structures according to claim 15, is characterized in that: this raised design covers a channel layer, this data line and this scan line of this thin-film transistor.
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| CN103887245B (en) * | 2014-03-28 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of manufacture method of array base palte |
| CN105679664B (en) * | 2016-03-18 | 2018-07-13 | 武汉华星光电技术有限公司 | Planarization layer goes remaining method |
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| JP3269787B2 (en) * | 1997-05-27 | 2002-04-02 | シャープ株式会社 | Liquid crystal display |
| CN1325984C (en) * | 2001-09-26 | 2007-07-11 | 三星电子株式会社 | Thin film transistor array substrate of liquid crystal display device and producing method thereof |
| CN1187643C (en) * | 2002-05-28 | 2005-02-02 | 友达光电股份有限公司 | Active array base plate of LCD device and its manufacturing method |
| KR100884541B1 (en) * | 2002-12-10 | 2009-02-18 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device and Method for fabricating the same |
| CN2606375Y (en) * | 2003-01-08 | 2004-03-10 | 广辉电子股份有限公司 | Semi-penetrating and semi-reflecting picture element structure |
| CN100485470C (en) * | 2005-09-13 | 2009-05-06 | 爱普生映像元器件有限公司 | Liquid crystal display device and method for manufacturing the same |
| CN101075623B (en) * | 2007-06-11 | 2011-05-11 | 友达光电股份有限公司 | Picture pixel structure and its formation |
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