CN102569186B - Array base plate and forming method thereof - Google Patents
Array base plate and forming method thereof Download PDFInfo
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- CN102569186B CN102569186B CN201010616900.0A CN201010616900A CN102569186B CN 102569186 B CN102569186 B CN 102569186B CN 201010616900 A CN201010616900 A CN 201010616900A CN 102569186 B CN102569186 B CN 102569186B
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Abstract
The invention relates to an array base plate and a forming method of the array base plate, and aims at replacing the existing lift-off process on the premise of that the mask number is not increased. The array base plate and the forming method are characterized in that a multi-section regulation mask is matched with an ordinary mask, and a display region and a peripheral wiring region of the array base plate can be formed only through carrying out a photoetching process for three times. In the peripheral wiring region formed by the process, a top conducting wire is in direct contact with a bottom conducting wire, and no other conducting layers are arranged between the top conducting wire and the bottom conducting wire. In addition, the lift-off process is not needed, and materials which cannot be dissolved in delustering resistance liquid are prevented from suspending on the delustering resistance liquid or from remaining on the surface of the array base plate.
Description
Technical field
The invention relates to the technique of liquid crystal display, especially about the formation method of its array base palte.
Background technology
The array base palte of making at present liquid crystal display generally need to reach the photoetching process in Si Zhi five roads, needs Si Zhi five road masks.If adopt three road mask process, need to utilize to lift off (Lift-off) technique.Lifting off in technique, first form photoresistance pattern as plated film sacrifice layer.Then form plated film on photoresistance and not by the region of photoresistance pattern covers, then substrate is soaked and is placed in the blocking solution of delustering.Along with photoresistance pattern is removed, can in the lump the plated film being positioned on photoresistance pattern be peeled off, reach the technique object of saving mask.But general TFT volume production equipment be not suitable for allowing the substrate that contains photoresistance enter deposition chamber carrying out technique, and plated film after peeling off also easily after-tacks to base plate array and forms defect.On the other hand, the plated film on photoresistance may be suspended in and deluster in blocking solution, causes the plug pipe phenomenon of the blocking solution feed-line that delusters.
In sum, array base palte San road mask process is needed new process at present badly, replaces the existing technique that lifts off under the prerequisite that does not increase mask count.
Summary of the invention
One embodiment of the invention provides a kind of formation method of array base palte, comprises and forms the first conductive layer on substrate; Form the first photoresist layer on the first conductive layer; Adjust mask with the first multisection type and carry out photoetching process, patterning the first photoresist layer is to form first without photoresistance region, the first thin layer photoresistance pattern and the first thick-layer photoresistance pattern; Etching correspondence first is without first conductive layer in photoresistance region, form grid, the gate line being connected with grid, common electrode wire and end wire, wherein the first thin layer photoresistance pattern is positioned on the cabling region of grid, gate line, common electrode wire and end wire, and the first thick-layer photoresistance pattern is positioned on the contact area of end wire; Ashing the first thin layer photoresistance pattern, the cabling region of exposing grid, gate line, common electrode wire and end wire; Selectivity depositing insulating layer is on the cabling region of substrate, grid, gate line, common electrode wire and end wire; Selectivity depositing semiconductor layers is on insulating barrier; Remove the first thick-layer photoresistance pattern; And form the second conductive layer on the contact area of semiconductor layer and end wire.
Another embodiment of the present invention provides a kind of formation method of array base palte, comprises and forms grid, the gate line being connected with grid and common electrode wire on substrate; Depositing insulating layer is in substrate, grid, gate line and common electrode wire; Depositing semiconductor layers is on insulating barrier; Depositing conducting layer is on semiconductor layer; Form photoresist layer on conductive layer; Adjust mask with multisection type and carry out photoetching process, patterning photoresist layer is to form without photoresistance region, thin layer photoresistance pattern, inferior thick-layer photoresistance pattern and thick-layer photoresistance pattern; Remove corresponding conductive layer and semiconductor layer without photoresistance region, form data wire, the conductive pattern that is connected to data wire, channel layer and top electrode, wherein data wire and gate line intersect vertically to define pixel region, channel layer is located between conductive pattern and grid, and top electrode cover part common electrode wire is to define storage capacitors; The wherein core of the corresponding conductive pattern of thin layer photoresistance pattern, and both sides, data wire and the top electrode of the corresponding conductive pattern of thick-layer photoresistance pattern for the second time; Ashing thin layer photoresistance pattern, exposes the core of conductive pattern; Remove the core of the conductive pattern exposing to form source/drain, and expose the channel layer on grid core, its drain electrode of medium bed photoresistance pattern corresponding part and part top electrode; Ashing time thick-layer photoresistance pattern, exposes source/drain, data wire and top electrode; On the All Ranges of selectivity deposition protective layer beyond thick-layer photoresistance pattern; Ashing thick-layer photoresistance pattern, exposed portions serve drain electrode and part top electrode; And form pixel electrode pattern on the protective layer of this pixel region, and pixel electrode pattern is connected to the part drain electrode and part top electrode of exposing.
Further embodiment of this invention provides a kind of formation method of array base palte, comprises and forms conductive layer on substrate; Form photoresist layer on conductive layer; Adjust mask with multisection type and carry out photoetching process, patterning photoresist layer is to form without photoresistance region, thin layer photoresistance pattern and thick-layer photoresistance pattern; Etching correspondence, without the conductive layer in photoresistance region, forms end wire, and wherein thin layer photoresistance pattern is positioned on the cabling region of end wire, and thick-layer photoresistance pattern is positioned on the contact area of end wire; Ashing thin layer photoresistance pattern, the cabling region of exposing end wire; Selectivity depositing insulating layer is on the cabling region of substrate and end wire; Selectivity depositing semiconductor layers is on insulating barrier; Remove thick-layer photoresistance pattern, expose the contact area of end wire; Form top wire on semiconductor layer, and top wire is connected on the contact area of end wire; Remove the semiconductor layer not covered by top wire; And form protective layer on insulating barrier and top wire.
Yet another embodiment of the invention provides a kind of array base palte, comprises end wire, is positioned on substrate; Insulating barrier, is positioned on end wire and substrate, and this insulating barrier has wire at the bottom of opening exposed portions serve; Top wire, is positioned on insulating barrier and via opening and directly contacts end wire; And protective layer, be positioned on top wire and substrate; Wherein sandwiched semiconductor layer between top wire and insulating barrier.
Accompanying drawing explanation
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:
In Figure 1A-1C, 3A-3H, 5A and 5C-5G one embodiment of the invention, form the technique cutaway view of the viewing area of array base palte;
In Fig. 1 D, 3I and 5B one embodiment of the invention, form the technique top view of the viewing area of array base palte;
In Fig. 2 A-2E and 4A-4E one embodiment of the invention, form the technique cutaway view in the peripheral wiring district of array base palte; And
In Fig. 1 E, Fig. 2 F and 4F one embodiment of the invention, form the technique cutaway view in the peripheral wiring district of array base palte.
Main element symbol description:
A-A ', B-B '～sound upper thread;
10～substrate;
11A, 33A～without photoresistance region;
11B, 33B～thin layer photoresistance pattern;
33C～inferior thick-layer photoresistance pattern;
11C, 33D～thick-layer photoresistance pattern;
12A～grid;
12B～gate line;
12C～bottom electrode;
12D～common electrode wire;
12E～end wire;
14～insulating barrier;
16～semiconductor layer;
16A～channel layer;
18～contact hole;
32～conductive layer;
32A～data wire;
32B～conductive pattern;
32C～top electrode;
32D～top wire;
32E～source electrode;
32F～drain electrode;
36A～drain contact hole;
36B～top electrode contact hole;
51～pixel electrode layer;
52～pixel electrode pattern;
53A, 53B～photoresistance pattern;
100～viewing area;
150～peripheral wiring district;
121A～cabling region;
121B～contact area;
300～pixel region;
330～storage capacitors.
Embodiment
How embodiment in following explanation forms and uses array base palte by description.Essential understanding, these embodiment provide multiple feasible inventive concept, and can be applicable in multiple certain content.Specific embodiment only forms and uses the ad hoc fashion of embodiment in order to explanation, not in order to limit to scope of the present invention.
First, sequentially form conductive layer and photoresist layer on substrate 10, then adjust mask with multisection type and carry out photoetching process, patterning photoresist layer is to form without photoresistance region 11A, thin layer photoresistance pattern 11B and thick-layer photoresistance pattern 11C.Then remove the corresponding conductive layer without photoresistance region 11A, until expose substrate 10.As shown in Figure 1A and Fig. 2 A, be positioned at the bottom electrode 12C that the patterned conductive layer of viewing area 100 comprises grid 12A and storage capacitors, and the patterned conductive layer that is positioned at peripheral wiring district 150 comprises end wire 12E.Thin layer photoresistance pattern 11b corresponding pattern conductive layer, such as the cabling region 121A of grid 12A, bottom electrode 12C and end wire 12E.The contact area 121B of the corresponding end wire 12E of thick-layer photoresistance pattern 11C.Cabling region 121A and contact area 121B about end wire 12E can be with reference to figure 2F.
The material of above-mentioned conductive layer can be metal, alloy or above-mentioned sandwich construction.In certain embodiments, conductive layer is combination or its alloy of the single or multiple lift materials such as molybdenum, aluminium, copper, titanium, gold, silver.The formation method of conductive layer can be physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), sputtering method or similar approach.Photoetching process can be following step: coating photoresistance, soft baking, alignment mask, exposure, postexposure bake, development, rinsing, drying are as hard baking, other appropriate process or above-mentioned combination.The rubbing methods such as that the formation method of photoresistance can be is rotary, slit, drum-type, ink jet type or atomizing.The etch process that removes conductive layer can be dry ecthing, wet etching or above-mentioned combination.
Photoetching process multisection type used is adjusted mask (Multi-tone mask) and be can be lamination mask (Stacklayer mask) or gray scale mask (Grey level mask).Be understandable that, in the time that photoresist layer consists of positive photoresistance, mask correspondence is transparent area without the part of photoresistance district 11A, and the part of the corresponding thin layer photoresistance of mask pattern 11B is part transparent area, and the part of the corresponding thick-layer photoresistance of mask pattern 11C is shading region.In the time that photoresist layer consists of negative photoresistance, mask correspondence is shading region without the part of photoresistance district 11A, and the part of the corresponding thin layer photoresistance of mask pattern 11B is part transparent area, and the part of the corresponding thick-layer photoresistance of mask pattern 11C is transparent area.In brief, negative photoresistance is contrary with the mask pattern that positive photoresistance adopts.
Then ashing thin layer photoresistance pattern 11B, exposes grid 12A and bottom electrode 12C as shown in Figure 1B, and the cabling region 121A that exposes end wire 12E as shown in Figure 2 B.This cineration step can adopt oxygen plasma, and its temperature is between between room temperature to 200 ℃.If the excess Temperature of cineration step, easily makes photoresistance coking cause subsequent technique cannot remove coking photoresistance.If the temperature of cineration step is too low, may cause reaction rate excessively slow, affect the process time.Above-mentioned cineration step can complete ashing thin layer photoresistance pattern 11B, and part ashing thick-layer photoresistance pattern 11C.Because cineration step belongs to etc. to removing mode, therefore the profile of thick-layer photoresistance pattern 11C need be greater than the contact area 121B of its corresponding end wire 12E.For instance, if when the thickness of thin layer photoresistance pattern 11b is 10 μ m, the outer rim of the outer rim of thick-layer photoresistance pattern 11C and the contact area 121B of the end wire 12E 10 μ m of being also separated by.Thus, can avoid cineration step to dwindle the contact area 121B of end wire 12E.
Then selectivity depositing insulating layer 14 is upper in the cabling region 121A of substrate 10, grid 12A, gate line 12B and common electrode wire 12D (please refer to Fig. 1 E), bottom electrode 12C and end wire 12E (please refer to Fig. 2 F), as shown in Fig. 1 C and Fig. 2 C.In other words, insulating barrier 14 is to be deposited on thick-layer photoresistance pattern 11C All Ranges in addition.Selectivity deposition can be ald (ALD, Atomic LayerDeposition), and its technological temperature is between between about room temperature to 200 ℃.If depositing temperature is too high, the easy coking of photoresistance, causes subsequent technique cannot remove coking photoresistance.If depositing temperature is too low, be easy to course of reaction and form graininess defect, or unsound plated film.Its characteristic one of atomic layer deposition method, for forming the fine and close plated film of complete stepcoverage, completes the gate insulator of high-quality; Its characteristic two is for having deposition region selectivity, suitably select the process conditions can deposition plating in organic substance surface, after removing photoresistance technique, directly form contact hole, and do not have plated film and peel off, can avoid polluting array base palte or the obstruction blocking solution feed-line that delusters.Insulating barrier 14 can be aluminium oxide, lanthana, hafnium oxide, nitrogen hafnium oxide, zirconia, other are applicable to the material of selectivity deposition or the stacking sandwich construction of above-mentioned monolayer material.
Then selectivity depositing semiconductor layers 16 is on insulating barrier 14, as shown in Fig. 1 D and Fig. 2 D.In other words, semiconductor layer 16 is not deposited on thick-layer photoresistance pattern 11C.Semiconductor layer 16 can be zinc oxide, indium oxide, indium gallium zinc oxide, tin oxide or other and is applicable to the material of selectivity deposition.The temperature control of selectivity deposition as previously mentioned, is not repeated herein.
Then remove residual thick-layer photoresistance pattern 11C, form the contact area 121B that contact hole 18 exposes end wire 12E, as shown in Figure 2 E.Because viewing area 100 does not have thick-layer photoresistance pattern 11C, therefore this removes step does not affect the structure shown in Fig. 1 D.This removes step and can be aforesaid cineration step or known wet type process for stripping.Be understandable that, the cutaway view of Fig. 1 E section line A-A ' is the structure shown in Fig. 1 D, and the cutaway view of Fig. 2 F section line B-B ' is the structure shown in Fig. 2 E.
Although in Fig. 1 E and 2F, the conductive layer of patterning is only as the grid 12A of thin-film transistor in viewing area 100, gate line 12B, the common electrode wire 12D (part common electrode wire 12D is using the bottom electrode 12C as storage capacitors described later) that are connected with grid and the end wire 12E in peripheral wiring district 150, but patterned conductive layer also can be used as contact pad or other elements, and end depends on the needs.As shown in Fig. 1 E, the parallel to each other and alternative arrangement of gate line 12B and common electrode wire 12D.
Then as shown in Figure 3A, form conductive layer 32 on the bottom and sidewall of semiconductor layer 16 and contact hole 18.Conductive layer 32 can be metal, alloy or above-mentioned sandwich construction, is preferably the stacked structure of molybdenum/aluminium/molybdenum, molybdenum/copper, molybdenum/copper/molybdenum or titanium/copper.The formation method of conductive layer 32 can be evaporation, sputter, physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Then form photoresist layer on conductive layer 32, adjust mask with another multisection type again and carry out photoetching process, patterning photoresist layer is to form without photoresistance region 33A, thin layer photoresistance pattern 33B, inferior thick-layer photoresistance pattern 33C and thick-layer photoresistance pattern 33D, as shown in Fig. 3 B and Fig. 4 B.The constitution and formation method of photoresist layer and aforesaid patterning photoresist layer are similar, are not repeated herein.Be understandable that, in the time that photoresist layer consists of positive photoresistance, mask correspondence is transparent area without the part of photoresistance district 33A.The corresponding thin layer photoresistance of mask pattern 33B is part transparent area with the part of time thick-layer photoresistance pattern 33C, and the light transmittance of the part transparent area of corresponding thin layer photoresistance pattern 33B is higher than the light transmittance of the part transparent area of corresponding time thick-layer photoresistance pattern 33B.The part of the corresponding thick-layer photoresistance of mask pattern 33D is shading region.In the time that photoresist layer consists of negative photoresistance, mask correspondence is shading region without the part of photoresistance district 33A, the part of the corresponding thin layer photoresistance pattern 33B of mask and inferior thick-layer photoresistance pattern 33C is part transparent area, and the light transmittance of the part transparent area of corresponding time thick-layer photoresistance pattern 33C is higher than the light transmittance of the part transparent area of corresponding thin layer photoresistance pattern 33B.The part of the corresponding thick-layer photoresistance of mask pattern 33D is transparent area.In brief, negative photoresistance is contrary with the mask pattern that positive photoresistance adopts.
Then remove corresponding conductive layer 32 and semiconductor layer 16 without photoresistance pattern 33A, as shown in Fig. 3 C and Fig. 4 C.The method that removes conductive layer 32 and semiconductor layer 16 can be wet etching, dry ecthing or above-mentioned combination.Form data wire 32A (please refer to Fig. 3 I), the conductive pattern 32B that is connected to data wire 32A, channel layer 16A and top electrode 32C in viewing area 100, form top wire 32D (please refer to Fig. 4 F) simultaneously in peripheral wiring district 150.In viewing area 100, data wire 32A and this gate line 12B intersect vertically to define pixel region 300 (please refer to Fig. 3 I).Channel layer 16A is located between conductive pattern 32B and grid 12A.Top electrode 32C cover part this common electrode wire 12D (being bottom electrode 12C) is to define storage capacitors 330.In peripheral wiring district 150, top wire 32D is connected to end wire 12E.In the contact area of the peripheral wiring of general technology, top wire is connected to end wire by electric conducting materials such as ITO.But in Fig. 4 C, top wire 32D is directly connected to end wire 12E via the contact hole 18 of insulating barrier 14, does not have the transparent conductive materials such as ITO between the two.
Equally at Fig. 3 C and Fig. 4 C, the core of the corresponding grid 12A of the thin layer photoresistance pattern 33B of known previous formation.The both sides of conductive pattern 32B in the corresponding viewing area 100 of inferior thick-layer photoresistance pattern 33C, data wire 32A, with top electrode 32C, and the top wire 32D in corresponding peripheral wiring district 150.The corresponding drain contact hole of follow-up formation of thick-layer photoresistance pattern 33D and the contact hole of top electrode 32C.
Then ashing thin layer photoresistance pattern 33B, exposes the conductive pattern 32B on the core of grid 12A, as shown in Figure 3 D.The technological parameter of this cineration step, with aforementioned cineration step, is not repeated herein.Above-mentioned cineration step can remove thin layer photoresistance pattern 33B completely, and part ashing time thick-layer photoresistance pattern 33C and thick-layer photoresistance pattern 33D.Because cineration step belongs to etc. to removing mode, because of the profile of this thick-layer photoresistance pattern 33C should be greater than the both sides, data wire 32A, top electrode 32C of its corresponding conductive pattern 32B, with top wire 32D.With above-mentioned reason, the profile of thick-layer photoresistance pattern 33D should be greater than the drain contact hole of follow-up formation and the contact hole of top electrode 32C.
Then remove the conductive pattern 32B on the core of grid 12A, form source electrode 32E and 32F and also expose the channel layer 16A under it, as shown in Fig. 3 E.The method that removes partially conductive pattern 32B can be dry ecthing, wet etching or above-mentioned combination.
Then ashing time thick-layer photoresistance pattern 33C, expose end wire 12E, data wire 32A, top electrode 32C, top wire 32D, source electrode 32E, with drain electrode 32F, as shown in Fig. 3 F and Fig. 4 D.The technological parameter of this cineration step, with aforementioned cineration step, is not repeated herein.Above-mentioned cineration step can remove time thick-layer photoresistance pattern 33C completely, and part ashing thick-layer photoresistance pattern 33D.Because cineration step belongs to etc. to removing mode, therefore the profile of thick-layer photoresistance pattern 33D should be greater than the drain contact hole of follow-up formation and the contact hole of top electrode 32C.
Then on the All Ranges of selectivity deposition protective layer 34 beyond thick-layer photoresistance pattern 33D, as shown in Fig. 3 G and Fig. 4 E.The material of protective layer 34 is selected with insulating barrier 14 similar, is not repeated herein.In an embodiment of the present invention, selectivity is deposited as ald.The temperature control of selectivity deposition as previously mentioned, is not repeated herein.
Then remove residual thick-layer photoresistance pattern 33D, form drain contact hole 36A and top electrode contact hole 36B, exposed portions serve drain electrode 32F and part top electrode 32C respectively, as shown in Fig. 3 H.This removes step and can be aforesaid cineration step or known wet type process for stripping.Because peripheral wiring district 150 does not have thick-layer photoresistance pattern 33D, this technique does not affect the structure shown in Fig. 4 E.Be understandable that, the cutaway view of Fig. 3 I section line A-A ' is the structure shown in Fig. 3 H, and the cutaway view of Fig. 4 F section line B-B ' is the structure shown in Fig. 4 E.
As shown in Figure 5A, form pixel electrode pattern 52 in pixel region 300 finally.Pixel electrode pattern 52, via drain contact hole 36A and top electrode contact hole 36B, is connected to respectively the drain electrode 32F of thin-film transistor and the top electrode 32C of storage capacitors 330.In an embodiment of the present invention, array base palte is to be applied to penetrating LCD, and the material of pixel electrode pattern 52 can be transparent material as indium tin oxide (ITO), indium-zinc oxide (IZO), aluminium zinc oxide (AZO), cadmium tin-oxide (CTO), tin oxide (SnO
2), zinc oxide (ZnO), development (Ag) or CNT (carbon nano-tube) (CNT).In another embodiment of the present invention, array base palte is to be applied to reflective liquid-crystal display, and the material of pixel electrode pattern 52 can be reflective material as aluminium, gold, tin, silver, copper, iron, lead, chromium, tungsten, molybdenum, neodymium, above-mentioned nitride, above-mentioned oxide, above-mentioned nitrogen oxide, above-mentioned alloy or above-mentioned combination.In addition, the surface of reflective pixel electrode pattern 52 presents concavo-convex, to increase the effect of reflection and scattering of light.Be understandable that, the cutaway view of Fig. 5 B section line A-A ' is the structure shown in Fig. 5 A.
The generation type of pixel electrode pattern 52 mainly contains two.The first is with photoetching process collocation mask, forms photoresistance pattern 53A in the region that does not need to form pixel electrode pattern 52, as shown in Figure 5 C.Then selectivity pixel deposition electrode pattern 52 is in pixel region 300, as shown in Figure 5 D.Finally remove photoresistance pattern 53A, form the structure shown in Fig. 5 A.The second is that first compliance terrain imaging element electrode layer 51 is in All Ranges, as shown in Fig. 5 E.Then form photoresistance pattern 53B on the pixel electrode layer 51 of pixel region 300, as shown in Fig. 5 F with photoetching process collocation mask.Then etching is not by the pixel electrode layer 51 of photoresistance pattern covers, as shown in Fig. 5 G.Finally remove photoresistance pattern 53B, can form the structure shown in Fig. 5 A.Because peripheral wiring district 150 does not need to form pixel electrode layer 51, if adopt first method, need to form the 3rd photoresistance pattern 53A in peripheral wiring district 150 to avoid pixel deposition electrode pattern 52, remove again afterwards photoresistance pattern 53A.If employing second method, does not form photoresistance pattern 53B in peripheral wiring district 150, in order to the pixel electrode layer 51 removing in peripheral wiring district 150.
In sum, one embodiment of the invention provide twice multisection type adjust mask with together with general mask, form numerous elements in viewing area 100 and peripheral wiring district 150.In another embodiment of the present invention, can adopt the photoetching process of normal masks to form the structure of Fig. 1 E, then form the structure shown in Fig. 3 I with the photoetching process of multisection type adjustment mask, finally form the structure shown in Fig. 5 B with the photoetching process of normal masks.In brief, in the situation that not considering peripheral wiring district 150, only need adjust mask and twice normal masks can form viewing area 100 with one multisection type.In further embodiment of this invention, the photoetching process that can adopt multisection type to adjust mask forms the structure of Fig. 2 F, then forms the structure shown in Fig. 4 F with the photoetching process of normal masks.In brief, in the situation that not considering viewing area 100, only need one multisection type adjust mask with together with normal masks can form peripheral wiring district 150.The array base palte that contains above-mentioned peripheral wiring district 150 can be applicable to photoelectric cell as the solar cell of irradiation generation electric energy, or electrified light emitting element is as display.In an embodiment of the present invention, display can be large scale flat-panel screens as TV, or middle display of size is if e-book or small-size display are as mobile phone screen.
Compare with known skill, adopt multisection type to adjust mask and can reduce photoetching process and alignment issues.Because the present invention does not need to lift off step, therefore do not form any material on photoresist layer.Thus, the step that removes photoresist layer can retained material on array base palte (yield is low) or the feed-line etc. that blocks the blocking solution of delustering be common in the problem that lifts off technique.The practice that Yi San road mask collocation selectivity depositing operation forms insulating barrier 14, semiconductor layer 16 and the protective layer 34 in viewing area 100 and/or peripheral wiring district 150 can increase volume production possibility.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little modification and perfect, therefore protection scope of the present invention is worked as with being as the criterion that claims were defined.
Claims (8)
1. a formation method for array base palte, comprising:
Form one first conductive layer on a substrate;
Form one first photoresist layer on this first conductive layer;
Adjust mask with one first multisection type and carry out a photoetching process, this first photoresist layer of patterning is to form one first without photoresistance region, one first thin layer photoresistance pattern and one first thick-layer photoresistance pattern;
Etching is to should first this first conductive layer without photoresistance region, the gate line, a common electrode wire and the end wire that form a grid, be connected with this grid, wherein this first thin layer photoresistance pattern is positioned on the cabling region of this grid, this gate line, this common electrode wire and this end wire, and this first thick-layer photoresistance pattern is positioned on the contact area of this end wire;
This first thin layer photoresistance pattern of ashing, the cabling region of exposing this grid, this gate line, this common electrode wire and this end wire;
Selectivity deposits on the cabling region of this substrate, this grid, this gate line, this common electrode wire and this end wire of an insulating barrier beyond this first thick-layer photoresistance pattern;
On selectivity deposition semi-conductor layer this insulating barrier beyond this first thick-layer photoresistance pattern;
Remove this first thick-layer photoresistance pattern; And
Form one second conductive layer on the contact area of this semiconductor layer and this end wire,
Wherein this selectivity is deposited as ald, and suitably selects process conditions with can deposition plating in organic substance surface.
2. the formation method of array base palte as claimed in claim 1, is characterized in that, more comprises:
Form one second photoresist layer on this second conductive layer;
Adjust mask with one second multisection type and carry out a photoetching process, this second photoresist layer of patterning is to form one second without photoresistance region, one second thin layer photoresistance pattern, thick-layer photoresistance pattern and one second thick-layer photoresistance pattern for the second time;
Remove should the second this second conductive layer and this semiconductor layer without photoresistance region, form a data wire, be connected to a conductive pattern, a channel layer, a top wire and a top electrode of this data wire, wherein this data wire and this gate line intersect vertically to define a pixel region, this top wire is connected to this end wire, this channel layer is located between this conductive pattern and this grid, and this this common electrode wire of top electrode cover part is to define a storage capacitors;
Wherein this second thin layer photoresistance pattern is to core that should grid, and this both sides, this data wire, this top electrode and this top wire of corresponding conductive pattern of thick-layer photoresistance pattern for the second time;
This second thin layer photoresistance pattern of ashing, exposes this conductive pattern on this grid core;
Remove this conductive pattern exposing, expose this channel layer on grid core and form source/drain electrode, wherein this this drain electrode of the second thick-layer photoresistance pattern corresponding part and this top electrode of part;
This thick-layer photoresistance pattern for the second time of ashing, exposes this source/drain, this data wire, this top electrode and this top wire;
Selectivity deposits on the All Ranges of a protective layer beyond this second thick-layer photoresistance pattern; And
This second thick-layer photoresistance pattern of ashing, this drain electrode of exposed portions serve and this top electrode of part.
3. the formation method of array base palte as claimed in claim 2; it is characterized in that; more comprise and form a pixel electrode pattern on the protective layer of this pixel region; and this pixel electrode pattern is connected to this drain electrode of part and this top electrode of part of exposing, and the step that wherein forms this pixel electrode pattern comprises:
Form on region in addition, this pixel region of photoresistance pattern covers;
Selectivity deposits this pixel electrode pattern on this pixel region; And
Remove this photoresistance pattern.
4. the formation method of array base palte as claimed in claim 2; it is characterized in that; more comprise and form a pixel electrode pattern on the protective layer of this pixel region; and this pixel electrode pattern is connected to this drain electrode of part and this top electrode of part of exposing, and the step that wherein forms this pixel electrode pattern comprises:
Form on the region of a conductive layer beyond this pixel region and pixel region;
Form this conductive layer of this pixel region of photoresistance pattern covers;
This conductive layer that removes region in addition, pixel region, forms this pixel electrode pattern; And
Remove this photoresistance pattern.
5. a formation method for array base palte, comprising:
A gate line that forms a grid, be connected with this grid and a common electrode wire are on a substrate;
Deposit an insulating barrier in this substrate, this grid, this gate line and this common electrode wire;
Deposition semi-conductor layer is on this insulating barrier;
Deposit a conductive layer on this semiconductor layer;
Form a photoresist layer on this conductive layer;
Adjust mask with a multisection type and carry out a photoetching process, this photoresist layer of patterning is to form one without photoresistance region, skim photoresistance pattern, thick-layer photoresistance pattern and a thick-layer photoresistance pattern;
Remove this conductive layer and this semiconductor layer that should unglazed resistance region, form a data wire, be connected to a conductive pattern, a channel layer and a top electrode of this data wire, wherein this data wire and this gate line intersect vertically to define a pixel region, this channel layer is located between this conductive pattern and this grid, and this this common electrode wire of top electrode cover part is to define a storage capacitors;
Wherein this thin layer photoresistance pattern is to core that should conductive pattern, and both sides, this data wire and this top electrode of this corresponding conductive pattern of thick-layer photoresistance pattern;
Ashing thin layer photoresistance pattern, exposes the conductive pattern on the core of this conductive pattern;
Remove this conductive pattern exposing to form source/drain electrode, and expose this channel layer on grid core, wherein this thick-layer photoresistance pattern this drain electrode of corresponding part and this top electrode of part;
This thick-layer photoresistance pattern of ashing, exposes this source/drain, this data wire and this top electrode;
Selectivity deposits on the All Ranges of a protective layer beyond this thick-layer photoresistance pattern;
This thick-layer photoresistance pattern of ashing, this drain electrode of exposed portions serve and this top electrode of part; And
Form a pixel electrode pattern on the protective layer of this pixel region, and this pixel electrode pattern is connected to this drain electrode of part of exposing and this top electrode of part,
Wherein this selectivity is deposited as ald, and suitably selects process conditions with can deposition plating in organic substance surface.
6. the formation method of array base palte as claimed in claim 5, is characterized in that, the step that forms this pixel electrode pattern comprises:
Form on region in addition, this pixel region of photoresistance pattern covers;
Selectivity deposits this pixel electrode pattern on this pixel region; And
Remove this photoresistance pattern.
7. the formation method of array base palte as claimed in claim 5, is characterized in that, the step that forms this pixel electrode pattern comprises:
Form on the region of a conductive layer beyond this pixel region and pixel region;
Form this conductive layer of this pixel region of photoresistance pattern covers;
This conductive layer that removes region in addition, pixel region, forms this pixel electrode pattern; And
Remove this photoresistance pattern.
8. a formation method for array base palte, comprising:
Form a conductive layer on a substrate;
Form a photoresist layer on this conductive layer;
Adjust mask with a multisection type and carry out a photoetching process, this photoresist layer of patterning is to form one without photoresistance region, skim photoresistance pattern and a thick-layer photoresistance pattern;
Etching, to this conductive layer that should unglazed resistance region, forms an end wire, and wherein this thin layer photoresistance pattern is positioned on the cabling region of this end wire, and this thick-layer photoresistance pattern is positioned on the contact area of this end wire;
This thin layer photoresistance pattern of ashing, the cabling region of exposing this end wire;
Selectivity deposits on the cabling region of this substrate beyond this thick-layer photoresistance pattern of an insulating barrier and this end wire;
On selectivity deposition semi-conductor layer this insulating barrier beyond this thick-layer photoresistance pattern;
Remove this thick-layer photoresistance pattern, expose the contact area of this end wire;
Form a top wire on this semiconductor layer, and this top wire is connected on the contact area of this end wire;
Remove the semiconductor layer not covered by this top wire; And
Form a protective layer on this insulating barrier and this top wire,
Wherein this selectivity is deposited as ald, and suitably selects process conditions with can deposition plating in organic substance surface.
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