CN102568602A - Flash memory development system - Google Patents
Flash memory development system Download PDFInfo
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- CN102568602A CN102568602A CN2011100942235A CN201110094223A CN102568602A CN 102568602 A CN102568602 A CN 102568602A CN 2011100942235 A CN2011100942235 A CN 2011100942235A CN 201110094223 A CN201110094223 A CN 201110094223A CN 102568602 A CN102568602 A CN 102568602A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 29
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- 230000008054 signal transmission Effects 0.000 claims abstract description 24
- 238000012360 testing method Methods 0.000 claims description 11
- 238000011084 recovery Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000004088 simulation Methods 0.000 abstract 2
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- 238000012544 monitoring process Methods 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 125000002015 acyclic group Chemical group 0.000 description 1
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Abstract
A flash memory development system comprises a transmission path switcher and a flash memory simulator. The transmission path switcher is connected in series between the memory controller and the signal transmission path of the flash memory and receives the debug start signal. The flash memory simulator receives at least one control command from the memory controller through the signal transmission path. The flash memory simulator interprets the control command and responds to the control command to generate at least one simulation response data. The flash memory simulator also transmits simulation response data to the memory controller through the signal transmission path. The invention does not need expensive instruments or complex methods, and improves the cost competitiveness of products.
Description
Technical field
The present invention relates to a kind of flash memory development system.
Background technology
Flash memory (flash memory) is that (read only memory, ROM), it allows by erasing and upgrade stored data repeatedly for the ROM (read-only memory) of a kind of (programmable) able to programme.
To flash memory with and Memory Controller when carrying out debug, often utilize so-called development system (development system) to accomplish.In known technical field; This development system that relates to flash memory module can be used logic analyser (Logical Analyzer; LA) or universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter UART) comes construction.The above-mentioned known practice of utilizing logic analyser is though can provide comparatively detailed debug data, suitable costliness on price.In addition, logic analyser also can't provide long debug record, is not a kind of good selection.And in the technology of using universal asynchronous receiving-transmitting transmitter, the debug record that it produced also can't produce related with the time of origin of mistake.In addition, universal asynchronous receiving-transmitting transmitter also can't provide the writing function of the debug record of big quantity.
Certainly, except the above-mentioned dual mode of carrying, known technology also proposes multiple different replacement scheme, carries out the debug and the policer operation of flash memory module.Yet, taking into account on cost and the effect, do not have gratifying answer.Therefore, the effectively foundation of the development system of flash memory module also is the problem that the deviser paid attention to of this area.
Summary of the invention
The present invention provides a kind of flash memory development system, effectively carries out the debug and the monitoring function of flash memory and affiliated Memory Controller thereof.
The present invention proposes a kind of flash memory development system, comprises transmission path switch and flash memory simulator.The transmission path switch is serially connected between the signal transmission path of Memory Controller and flash memory and receives the debug enabling signal.The flash memory simulator couples the transmission path switch, receives at least one control command from Memory Controller by signal transmission path.Flash memory simulator and decipher control command and responsing control command are to produce at least one analog response data.The flash memory simulator also transmits the analog response data to Memory Controller through signal transmission path.
In one embodiment of this invention; Above-mentioned transmission path switch is sent to flash memory simulator and flash memory by signal transmission path with the control command that Memory Controller transmits, and the real response data that analog response data and flash memory produced according to the debug enabling signal wherein one be sent to Memory Controller by signal transmission path.
In one embodiment of this invention, above-mentioned flash memory simulator also is coupled to host side, in order at least one status information of transmitting Memory Controller to host side.
In one embodiment of this invention, above-mentioned status information comprises that Memory Controller is directed against the magnitude of traffic flow that flash memory carries out access.
In one embodiment of this invention, above-mentioned host side also to transmit at least one data-signal each other with Memory Controller according to the non-flash memory control command through flash memory simulator and signal transmission path.
In one embodiment of this invention, above-mentioned host side is also set the debug test pattern, and makes the flash memory simulator produce the debug test data with as the analog response data and be sent to Memory Controller according to status information and debug test pattern.
In one embodiment of this invention, above-mentioned Memory Controller checks according to the fixed cycle whether the flash memory simulator transmits the flash memory access requirement, and Memory Controller also comes access flash memory according to the flash memory access requirement.
In one embodiment of this invention, above-mentioned flash memory access requirement is sent to the flash memory simulator by host side.
In one embodiment of this invention, above-mentioned host side also in order to the storing state data to obtain the Status of Backups data.
In one embodiment of this invention, above-mentioned host side also transmits Status of Backups data to Memory Controller with the recovery foundation as the duty of Memory Controller.
Based on above-mentioned, the present invention accomplishes the transmission operation of the multiple signal between Memory Controller, flash memory and flash memory simulator by the signal transmission path that is provided in the transmission path switch.And use to reach and come flash memory and affiliated Memory Controller is monitored and the operation of debug through the flash memory simulator.Need not promote the cost competitiveness of product through expensive instrument or complicated method.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 shows the synoptic diagram of development system 100 of the flash memory module of the embodiment of the invention.
Fig. 2 shows an embodiment synoptic diagram of the transmission path switch 110 of the embodiment of the invention.
The main element symbol description:
100: development system
110: the transmission path switch
120: the flash memory simulator
10: Memory Controller
30: host side
50: flash memory
111: the path handover module
CTRLS: control command
DEBEN: debug enabling signal
SW1, SW2: switch
A1, A2: end points
Embodiment
At first please with reference to Fig. 1, Fig. 1 shows the synoptic diagram of development system 100 of the flash memory module of the embodiment of the invention.Wherein, development system 100 comprises transmission path switch 110 and flash memory simulator 120.Transmission path switch 110 is serially connected between the signal transmission path of Memory Controller 10 and flash memory 50 of flash memory module.Flash memory simulator 120 couples transmission path switch 110; Receive at least one control command CTRLS by signal transmission path from Memory Controller, and the control command CTRLS that decipher received with responsing control command CTRLS to produce at least one analog response data.Flash memory simulator 120 also transmits the analog response data to Memory Controller through signal transmission path.
Above-mentioned signal transmission path comprises that the control command CTRLS that Memory Controller 110 is transmitted is sent to flash memory simulator 120 and flash memory 50 simultaneously.In addition, signal transmission path also comprise real response data that analog response data that flash memory simulator 120 corresponding control command CTRLS are produced and flash memory 50 produce one of them be sent to Memory Controller 110.At this, transmission path switch 110 receives debug enabling signal DEBEN and selects to transmit the real response data that analog response data that flash memory simulator 120 produced or flash memory 50 produce according to debug enabling signal DEBEN and reaches Memory Controller 110 back and forth.Explain that more specifically when debug enabling signal DEBEN indication debug action was activated, transmission path switch 110 selected to transmit analog response returning data to the Memory Controller 110 that flash memory simulator 120 is produced.Opposite, as if when debug enabling signal DEBEN indication debug action is closed, the real response data that transmission path switch 110 is selected to transmit flash memory 50 generations reach Memory Controller 110 back and forth.
120 in flash memory simulator is all functions that are designed to comprise flash memory 50.In simple terms, when 10 pairs of flash memories 50 of Memory Controller write data, these data can be written into flash memory simulator 120 simultaneously exactly.Identical, when Memory Controller 10 sent reading order to flash memory and is transferred into flash memory simulator 120, its stored data to Memory Controller 10 was seen in 120 passbacks of flash memory simulator off.
Note that debug enabling signal DEBEN can be by 120 generations of flash memory simulator.In addition, flash memory simulator 120 also provides a transmission interface, comes to be connected with the host side 30 in the external world and the operation of data transmission.That is to say that flash memory simulator 120 can be sent to host side 30 with the one or more status information in the flash memory module through the connecting interface of itself and host side 30.In addition, flash memory simulator 120 also can receive the order that host side 30 is provided through this connecting interface, carries out flash memory module is carried out the associative operation of debug.In the present embodiment, debug enabling signal DEBEN assigns the order that debug starts through host side 30, and makes flash memory simulator 120 produce the debug enabling signal DEBEN that indication debug operation is activated.
Subsidiary one carries, and host side 30 can be the electronic installation that PC or other same types have data-handling capacity.
In the present embodiment; Flash memory simulator 120; Can be by its one or more control command CTRLS that provides signal transmission path to receive through 110 of transmission path switchs; Parse the magnitude of traffic flow that 10 pairs of flash memories of flash memory controller 50 carry out access, and with this magnitude of traffic flow periodicity or the acyclic host side 30 that is sent to.30 of host side can be monitored the access status of flash memory controller 10 and flash memory 50 according to the one or more magnitude of traffic flow that is received.
In addition, host side 30 can also transmit one or more data-signals each other with Memory Controller 10 according to the non-flash memory control command through flash memory simulator 120 and signal transmission path 110.Wherein, above-mentioned non-flash memory control command can't be stored that device controller 10 is mistranslated and flash memory 50 is carried out wrong access.Therefore, utilize the non-flash memory control command can effectively make host side 30 and Memory Controller 10 carry out two-way communication, existing flash memory module is not produced interference and can not produce.In addition, the non-flash memory control command can be defined by the deviser voluntarily, and host side 30 and Memory Controller 10 both sides all can be discerned get final product.
On the other hand, host side 30 can also be set a debug test pattern by the user.When the status information that is transmitted when flash memory simulator 120 is consistent with the debug test pattern that sets, then make flash memory simulator 120 produce the debug test datas with as the analog response data and be sent to Memory Controller 10.Explain that more specifically for example host side 30 settings are the debug test pattern when Memory Controller 10 sends to address 0x0020 sense data.The control command CTRLS that Memory Controller 10 transmitted that receives when flash memory simulator 120 just is when being directed against address 0x0020 sense data, and the data that are stored in address 0x0020 (for example being 0xAA) that 120 changes of flash memory simulator should be sent out originally are used as the analog response data and are sent to Memory Controller 10 for debug test data 0x55.And observe Memory Controller 10 by this and receive this and the reaction carried out of the different analog response data of expection, with observation Memory Controller 10.
Below please with reference to Fig. 2, Fig. 2 shows an embodiment synoptic diagram of the transmission path switch 110 of the embodiment of the invention.Transmission path switch 110 comprises path handover module 111.Path handover module 111 comes construction by switch SW 1 and SW2.Wherein, switch SW 1 and SW2 all are controlled by debug enabling signal DEBEN, and the state of the conducting of switch SW 1 and SW2 or disconnection is opposite.In simple terms, transmission path switch 110 can be sent to flash memory simulator 120 and flash memory 50 respectively through terminal A 1 and A2 simultaneously with the receive control command CTRS that comes from Memory Controller 10.On the other hand; The data (analog response data and real response data) that reach transmission path switch 110 by flash memory simulator 120 and flash memory 50 then can be according to conducting or the off-state of switch SW in the path handover module 111 1 and SW2, and one of them that transmits analog response data and real response data is to Memory Controller 10.
In sum, the control command that the present invention utilizes the flash memory simulator to come the decipher Memory Controller to be produced, and according to control command to produce the analog response data to monitor and the function of debug.In addition; The present invention also selects the debug action launching by the transmission path switch or the signal transmission path when closing; And use and make the flash memory simulator when the debug action launching; Can be effectively and flash memory and Memory Controller carry out interaction, and when the debug action is closed, the normal running that can recover flash memory and Memory Controller.Thus, do not need the down auxiliary of expensive electronic installation, can reach the debug and the monitoring function of flash memory.
Though the present invention discloses as above with embodiment, so it is not in order to limiting the present invention, any under those skilled in the art, when can doing a little change and retouching, and do not break away from the spirit and scope of the present invention.
Claims (10)
1. flash memory development system comprises:
One transmission path switch is serially connected between a signal transmission path of a Memory Controller and a flash memory, receives a debug enabling signal; And
One flash memory simulator; Couple this transmission path switch; Receive at least one control command by this signal transmission path from this Memory Controller; This control command of decipher also responds this control command to produce at least one analog response data, and this flash memory simulator also transmits these analog response data to this Memory Controller through this signal transmission path.
2. flash memory development system according to claim 1; Wherein this transmission path switch is sent to this flash memory simulator and this flash memory by this signal transmission path with this control command that this Memory Controller transmits, and one of them of real response data that these analog response data and this flash memory produced according to this debug enabling signal is sent to this Memory Controller by this signal transmission path.
3. flash memory development system according to claim 1, wherein this flash memory simulator also is coupled to a host side, in order at least one status information of transmitting this Memory Controller to this host side.
4. flash memory development system according to claim 3, wherein this status information comprises the magnitude of traffic flow that this Memory Controller carries out access to this flash memory.
5. flash memory development system according to claim 3, wherein this host side also to transmit at least one data-signal each other with this Memory Controller according to a non-flash memory control command through this flash memory simulator and this signal transmission path.
6. flash memory development system according to claim 3; Wherein this host side is also set a debug test pattern, and makes this flash memory simulator produce a debug test data with as these analog response data and be sent to this Memory Controller according to this status information and this debug test pattern.
7. flash memory development system according to claim 3; Wherein this Memory Controller checks according to a fixed cycle whether this flash memory simulator transmits a flash memory access requirement, and this Memory Controller also comes this flash memory of access according to this flash memory access requirement.
8. flash memory development system according to claim 7, wherein this flash memory access requirement is sent to this flash memory simulator by this host side.
9. flash memory development system according to claim 3, wherein this host side is also in order to store this status data to obtain Status of Backups data.
10. flash memory development system according to claim 9, wherein this host side also transmits these Status of Backups data to this Memory Controller with the recovery foundation as the duty of this Memory Controller.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099144318 | 2010-12-16 | ||
| TW099144318A TWI463501B (en) | 2010-12-16 | 2010-12-16 | Development system for a flash memory module |
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| Publication Number | Publication Date |
|---|---|
| CN102568602A true CN102568602A (en) | 2012-07-11 |
| CN102568602B CN102568602B (en) | 2015-01-21 |
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| CN201110094223.5A Active CN102568602B (en) | 2010-12-16 | 2011-04-13 | Flash memory development system |
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| CN (1) | CN102568602B (en) |
| TW (1) | TWI463501B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108804272A (en) * | 2018-05-25 | 2018-11-13 | 深圳市德名利电子有限公司 | A kind of the flash memory simulator and its analogy method of high speed |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI492054B (en) * | 2012-11-05 | 2015-07-11 | Phison Electronics Corp | Simulator and simulating method for flash memory |
| US9582608B2 (en) | 2013-06-07 | 2017-02-28 | Apple Inc. | Unified ranking with entropy-weighted information for phrase-based semantic auto-completion |
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| US6904400B1 (en) * | 1998-09-30 | 2005-06-07 | Stmicroelectronics S.R.L. | Flash EEPROM memory emulator of non-flash EEPROM device and corresponding method |
| CN1896975A (en) * | 2005-07-11 | 2007-01-17 | 佛山市顺德区顺达电脑厂有限公司 | Controllable module and method for detecting disk driver state |
| US20090144487A1 (en) * | 2007-11-30 | 2009-06-04 | Aten International Co., Ltd. | Storage emulator and method thereof |
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| US7028212B1 (en) * | 2002-08-08 | 2006-04-11 | Cisco Technology, Inc. | Network device and method of operation |
| TW200625066A (en) * | 2005-01-14 | 2006-07-16 | Farstone Tech Inc | Backup/recovery system and method thereof |
| CN101329647A (en) * | 2007-06-20 | 2008-12-24 | 上海华虹集成电路有限责任公司 | Emulator of emulation in-chip FLASH |
| CN101329646B (en) * | 2007-06-20 | 2011-11-30 | 上海华虹集成电路有限责任公司 | Emulator for implementing FLASH page erase emulation |
-
2010
- 2010-12-16 TW TW099144318A patent/TWI463501B/en active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6904400B1 (en) * | 1998-09-30 | 2005-06-07 | Stmicroelectronics S.R.L. | Flash EEPROM memory emulator of non-flash EEPROM device and corresponding method |
| CN1896975A (en) * | 2005-07-11 | 2007-01-17 | 佛山市顺德区顺达电脑厂有限公司 | Controllable module and method for detecting disk driver state |
| US20090144487A1 (en) * | 2007-11-30 | 2009-06-04 | Aten International Co., Ltd. | Storage emulator and method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108804272A (en) * | 2018-05-25 | 2018-11-13 | 深圳市德名利电子有限公司 | A kind of the flash memory simulator and its analogy method of high speed |
| CN108804272B (en) * | 2018-05-25 | 2021-08-27 | 深圳市德明利技术股份有限公司 | High-speed flash memory simulator and simulation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI463501B (en) | 2014-12-01 |
| TW201227745A (en) | 2012-07-01 |
| CN102568602B (en) | 2015-01-21 |
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