CN102567163B - Method for identifying cooperative behaviors of components of real-time embedded system based on UPPAAL tool - Google Patents
Method for identifying cooperative behaviors of components of real-time embedded system based on UPPAAL tool Download PDFInfo
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- CN102567163B CN102567163B CN2011104230954A CN201110423095A CN102567163B CN 102567163 B CN102567163 B CN 102567163B CN 2011104230954 A CN2011104230954 A CN 2011104230954A CN 201110423095 A CN201110423095 A CN 201110423095A CN 102567163 B CN102567163 B CN 102567163B
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Abstract
The invention discloses a method for identifying cooperative behaviors of components of a real-time embedded system based on a UPPAAL tool. The method comprises the following steps of: converting a modeling and analysis of real-time embedded systems (MARTE) model which is formed by modeling the real-time embedded system into timed automata which can be identified by the UPPAAL tool; identifying the timed automata by using the UPPAAL tool to obtain an identification result; according to the obtained identification result, determining the consistency of interactive behaviors of the component of the real-time embedded system and time accuracy; and performing corresponding operation on the model. Therefore, the probability of errors in the running and operating processes of the real-time embedded system which is generated by the model is reduced.
Description
Technical field
The present invention relates to model component and verification technique field, particularly the verification method of agreement between a kind of member of real time embedded system based on UPPAAL.
Background technology
Therefore in real time embedded system, any point mistake all may cause the generation of disaster, guarantees safety, reliability is to set up the matter of utmost importance of real time embedded system.For traditional real time embedded system, when designing, be in different modelling phases and period due to member overall design, component interactive behavior and member status information three, therefore, in the model of finally paying, tend to exist inconsistent phenomenon, thereby the specific implementation of system has from now on been increased to defect and hidden danger.
In modelling verification and time verifying field, UPPAAL is comparatively ripe at present verification tool.UPPAAL is the Verification of Real-Time Systems simulation tool of the time-based automat (Timed Automata) of Sweden Uppsala university and the joint production of Denmark Aalborg university.In UPPAAL, process is described to the Timed Automata be comprised of limited control structure, real number value clock and variable, by pipeline channel, shared variable communication, pipeline, carries out simultaneously for guaranteeing two conversions of different automats between process.UPPAAL is since nineteen ninety-five proposes, with its powerful efficient simplation verification ability, in industry member and the extensively recognition and acceptance of research circle's quilt.
Simultaneously, for for the modeling personnel provide modeling technique support widely, the OMG tissue has been released up-to-date real time embedded system modeling standard, MARTE.Particularly in the Real-time modeling set field, MARTE provides abundant time modeling and solution for system designer.The bag figure of MARTE time model structure as shown in Figure 1.MARTE supports multi-clock (multi time), multiple types clock and polymorphic clock (multiform time), and combine VSL(value specification language) language and CCSL, express system restriction with grammatical form semantic, more standard more clearly.
Yet, for the real-time system model that adopts the MARTE modeling, lack at present perfect modelling verification theory and practice method comprehensively.And between member, the factor such as mutual consistance and time correctness is the important consideration factor to security of system.
Summary of the invention
What the objective of the invention is to provide for the deficiencies in the prior art a kind ofly take verification tool UPPAAL and is basic modelling verification method, the method can verify the mutual consistance of real time embedded system and the correctness of time, take model as basic member, produce wrong probability in practical operation thereby reduced; The present invention is the Timed Automata model that instrument UPPAAL can verify by the model conversation of real time embedded system commonly used, by the result of UPPAAL, model is taked to innovative approach.
The object of the present invention is achieved like this:
The verification method of agreement between a kind of member of real time embedded system based on UPPAAL, the method is: the MARTE model conversation that will form the real time embedded system modeling is the Timed Automata that instrument UPPAAL can verify, then use the UPPAAL instrument to verify Timed Automata, and draw the result; Specifically comprise the following steps:
A, real time embedded system MARTE model conversation are Timed Automata
I), for the MARTE component diagram that CCSL constraint is arranged in the MARTE model, according to the CCSL semanteme, component model is converted into to the emulation automat; Specifically comprise:
Each port of member is modeled as to a Timed Automata; Then, according to the CCSL semanteme, to constraint mutual between port, the interbehavior information between port is extracted, and these behavioural information modelings are become to the main Timed Automata in model, for simulation and the checking of the component of a system;
II), for the MARTE component diagram that there is no CCSL constraint in the MARTE model, at first, the MARTE precedence diagram in model is converted into to the monitoring automat; Then, the MARTE constitutional diagram in model is converted into to the object Timed Automata; Specifically comprise:
The process that MARTE precedence diagram in model is converted into to the monitoring automat is: modelling verification is that transmission by message is as the modeling foundation; At first, using message as a monitored object, take over party and transmit leg according to each message, the time-constrain comprised in the context of message and message generates state transition and the signal variable of UPPAAL monitoring automat accordingly, and then be converted into the monitoring automat, be used for the interbehavior of whole system is monitored;
The process that MARTE constitutional diagram in model is converted into to Timed Automata is: the MARTE constitutional diagram is a component of a system modeling accordingly; The event information of component inside means by the MARTE constitutional diagram; Event information comprises outside interactive information and inner lastest imformation; Each state in the MARTE constitutional diagram is converted into to the location in Timed Automata correspondingly, according to the migration between state, correspondingly be converted into the edge in Timed Automata, for in constitutional diagram, calling of other objects being converted into to synchronization, the constitutional diagram built-in variable is upgraded and is converted into effect, and in constitutional diagram, control variable is converted into guard; Last extra synchronization and the effect of adding in relating to mutual edge again, so that the monitoring automat is collected signal;
B, tool using UPPAAL verify (as the concern checking etc. of variable of Deadlock, safety) to the Timed Automata model transformed, and the output the result.
Compared with prior art, the present invention adopts the mode of reusable component, develops real time embedded system by Components Composition, has effectively improved development efficiency and the quality of system.And the present invention can carry out the conversion of model to the good real time embedded system of modeling, according to mutual between building and obtain a result by the checking of model, the model of system is improved; Thereby reduced the real time embedded system wrong probability occurred in operation and operating process by model generation.Make the security guarantee of real time embedded system in design process can be more fully and concrete.
The accompanying drawing explanation
Fig. 1 is the bag figure of MARTE time model;
Fig. 2 is the schematic diagram that the MARTE constitutional diagram is converted into the monitoring automat;
Fig. 3 is the schematic diagram of embodiment 1 train control system;
Fig. 4 is the component diagram of embodiment 1 train control system;
Fig. 5 is the MARTE precedence diagram of embodiment 1 train control system;
Fig. 6 is the monitoring automat that the MARTE precedence diagram transforms into;
Fig. 7 is the MARTE constitutional diagram of member Gate;
Fig. 8 is the MARTE constitutional diagram of member Control;
Fig. 9 is the MARTE constitutional diagram of member Train;
Figure 10 is the Timed Automata that member Gate is corresponding;
Figure 11 is the Timed Automata that member Control is corresponding;
Figure 12 is the Timed Automata model that member Train is corresponding;
Figure 13 is the result of embodiment 1 train control system;
Figure 14 is the DMA video card component of a system figure of embodiment 2;
Figure 15 is the relation of describing by CCSL between the DMA display system member port of embodiment 2;
Figure 16 is the main Timed Automata of Filter;
Figure 17 is the Timed Automata of Ready port;
Figure 18 is the Timed Automata of Inword port;
Figure 19 is the Timed Automata of Outpixel port;
Figure 20 is the Timed Automata of EOL port;
Figure 21 is the result of the DMA display card system of embodiment 2.
Embodiment
The present invention is based on UPPAAL is verification tool, input using the MARTE model as method, interactive information in the MARTE model is extracted, then by transforming, the expression way of information interaction in MAETE is converted into to the modeling language of UPPAAL, by the expression of UPPAAL modeling language, information interaction is converted into to the Timed Automata model that can use the UPPAAL checking; Difference according to interactive information is extracted has proposed two kinds of settling modes:
1. from the MARTE precedence diagram, extracting interactive information
At first, use the agreement between MARTE precedence diagram modeling Real-time Component, using each message in precedence diagram as a monitored object, according to take over party and transmit leg, and the context of different message, be converted into the modeling language of UPPAAL, regeneration monitoring automat (observer automata).
The monitoring automat can be verified by the UPPAAL instrument, be that the interbehavior of whole system is analyzed, verified and monitors.
Precedence diagram is converted into to the monitoring automat, and the mutual constraint information for occurring in precedence diagram mainly is divided three classes:
A. the time context constraint of Message generation;
B. Message receives and sends object;
C. MARTE " TimeConstraints " time-constrain.
Extraction transfer process for above three kinds of constraint informations is respectively:
I) because the monitoring period automat is single-threaded, so the sequencing of its each state transition is to construct in strict accordance with the front and back order of message in precedence diagram.In case during system simulation, run counter to alternately the front and back sequence requirement of monitoring automat between member, monitor automat and directly fall into the fail state, abnormal to show mutual appearance.
II) in the MARTE precedence diagram, each message has a fixing and unique sending and receiving object (member), therefore, when the monitoring period automat is constructed, can determine by synchronizing information and guard condition the correctness of monitored interactive information in each state transition.In case certain constantly mutual both sides is abnormal, monitors automat and falls into immediately the fail state.
III) extraction for time constraints in MARTE has related to concrete VSL grammer, but the principal mode of time constraints can be described as duration<t or duration in essence > form of t.In order to verify the time-constrain of this form, on the monitoring period automat, constructed time error state.When the duration of monitored component behavior surpasses or is less than constraint condition, can jump into time error state, thereby reach the purpose of monitoring precedence diagram time-constrain.Fig. 2 is the schematic diagram that the MARTE precedence diagram is converted into the monitoring automat.
Then, will use the MARTE constitutional diagram to construct the model of each member according to component diagram.In the MARTE model, the status information of component inside is used MARTE constitutional diagram (state machine diagram) to describe usually.And the event information related in constitutional diagram, these event informations can be divided into outside interactive information and inner lastest imformation.Each member of system is constructed to a Timed Automata accordingly.Due to the similarity of MARTE constitutional diagram and Timed Automata, when design transforms, constructed a mapping function one to one, as following table:
Finally, by UPPAAL, verify the Timed Automata that monitoring automat that the MARTE precedence diagram is converted into and MARTE constitutional diagram corresponding to the component of a system are converted into.The Uppaal instrument provides the simulation of the system be comprised of Timed Automata and authentication function.The modeling graphics set that component of a system figure by before, MARTE precedence diagram and constitutional diagram form, provide instrument to be automatically converted to the XML document that uppaal accepts, and load uppaal and carry out automatic Verification.In view of the monitoring automat (observer) of constructing before, four general uppaal proof rules have been proposed, to reach the consistance of the modeling information of verifying component interactive, and the checking of system deadlock problem etc.Article four, proof rule is as follows:
A [] not FAIL (1)
E <> END (2)
A [] not TimeError (3)
A [] not deadlock (4)
Wherein whether (1) formula checking monitoring automat enters the FAIL state, (2) whether whether formula checking whole system can finally be moved time-constrain that complete (3) formula is used for verifying that precedence diagram contains and be satisfied in can be mutual on member opportunity, and whether (4) formula verification system has deadlock.
2, from the MARTE component diagram of system, obtain interactive information
For the extraction of MARTE member designs figure interactive information, adopt different means.The MARTE member in design, is different clocks by each port definition usually, and the interactive information between member is by completing alternately between these clocks.Therefore, the mutual constraint stipulations of member are just often write out with the form of CCSL.
At first, when modelling verification, the simulation automat of each port member by component inside, by the synchronization mechanism of automat, be stitched together each port and member, as the unit of simplation verification.
Then, according to the restriction relation of input and output between each port of corresponding CCSL constraint specification, the behavior of member and port is retrained, thereby from component diagram, extracting complete interactive information, for simulation and the checking of the component of a system.
Finally, by UPPAAL, verify the Timed Automata model of the system that information extraction is converted in the MARTE component diagram.The UPPAAL instrument provides simulation and the authentication function of the system that free automat is formed.Provide instrument that the CCSL semanteme is converted into to the Timed Automata model.Again according to the UPPAAL proof rule that passes through, to reach consistance mutual between member, and the checking of Deadlock etc.Article four, proof rule is as follows:
A [] not FAIL (1)
E <> END (2)
A [] not TimeError (3)
A [] not deadlock (4)
Wherein whether (1) formula checking monitoring automat enters the FAIL state, (2) whether whether formula checking whole system can finally be moved time-constrain that complete (3) formula is used for verifying that precedence diagram contains and be satisfied in can be mutual on member opportunity, and whether (4) formula verification system has deadlock.
The checking input message is the system of the precedence diagram of MARTE constitutional diagram and MARTE
What the present embodiment adopted is an easy train control system.Fig. 3 is the schematic diagram of this train control system.In the train merger, only allow a train by critical zone (critical section), to prevent collision.Near arriving the place ahead, critical zone, train when (near), can, to control system (control) inquiry, whether allow it to pass through.If can not, stop immediately; If of course, control can order Gate to become rail, makes train pass through critical zone.Notice control when train rolls critical zone away from, control can notify the train of wait to restart and enter critical section by door gate.In if train arrives, another track has had train in the periphery, critical zone, to wait while being true (be waiting global variable), and new train can stop immediately, allows the vehicle of having waited for pass through in advance.The component diagram that the present embodiment modeling forms comprises three members: the Gate(door), the Control(control desk) and the Train(train).Fig. 4 is the component diagram of this train control system.
According to the method that the present invention proposes, class figure, constitutional diagram and the precedence diagram of inputting carried out to the Timed Automata conversion, concrete implementing procedure is as follows:
1), modeling goes out the MARTE precedence diagram of the present embodiment, and the MARTE precedence diagram that modeling is good is converted into the monitoring automat.
Fig. 5 is the MARTE precedence diagram of train control system.
According to the above-mentioned method that precedence diagram is converted into to the monitoring automat, be applied to the timed automata formed in the present embodiment.Fig. 6 is the monitoring automat that the MARTE precedence diagram transforms into.
2), the modeling MARTE constitutional diagram that goes out each member in the present embodiment, and the MARTE constitutional diagram that modeling is good is converted into Timed Automata.
The present embodiment comprises three member: Gate, Control and Train.The MARTE constitutional diagram that the Gate modeling becomes, Fig. 7 is the MARTE constitutional diagram of member Gate.The MARTE constitutional diagram that Control is modeled as, Fig. 8 is the MARTE constitutional diagram of member Control.The MARTE constitutional diagram that the Train modeling becomes, Fig. 9 is the MARTE constitutional diagram of member Train.By the method in this patent, can easily the MARTE constitutional diagram be converted into to Timed Automata.According to the method in this patent, the MARTE constitutional diagram of Gate is converted into Timed Automata, and Figure 10 is the Timed Automata that member Gate is corresponding; The MARTE constitutional diagram of Control is converted into Timed Automata, and Figure 11 is the Timed Automata that member Control is corresponding; The MARTE constitutional diagram of Train is converted into Timed Automata, and Figure 12 is the Timed Automata model that member Train is corresponding.
The Timed Automata that 3), will be converted into is verified in instrument UPPAAL.
The Timed Automata of system in embodiment is verified by UPPAAL, drawn result, Figure 13 is the result of train control system.Result shows that there is deadlock in this system.
The checking input message is the MARTE component diagram of describing with detailed CCSL
What the present embodiment adopted is DMA display card (filter) construction system.The DMA display card can directly read byte stream (bit stream) information from corresponding interior nonresident portion, through inter-process and transcoding, by byte stream bit stream with the form of a pixel of every 4 bit coding to display output pixel (pixel) information; In addition, because the width of display is limited, the display width of regulation display is 8 pixels in this embodiment, when namely display card often outputs to the 8th pixel, can send control signal next line to display, to point out its line feed.
Figure 14 is the component of a system figure of DMA video card.Being undertaken by port alternately between member.The time relationship that between port, information transmits is described by CCSL.Figure 15 is the relation of describing by CCSL between DMA display system member port.
According to the method for the present invention's proposition, to the port modeling of video card member.Figure 16 is the main Timed Automata of Filter.Figure 17 is the Timed Automata of Ready port.Figure 18 is the Timed Automata of Inword port.Figure 19 is the Timed Automata of Outpixel port.Figure 20 is the Timed Automata of EOL port.
According to the concrete characteristics of DMA display card, design two basic verification rules.Article one, for verifying that buffer memory (buffer) perseverance of display card can not surpass allowed band, whether the second verification system deadlock.Figure 21 is the result of DMA display card system.
The result shows, the present embodiment system meets top two principle.
Claims (4)
1. the verification method of agreement between the member of the real time embedded system based on UPPAAL, it is characterized in that the method is: the MARTE model conversation that the real time embedded system modeling is formed is the Timed Automata that instrument UPPAAL can verify, then use the UPPAAL instrument to verify Timed Automata, and draw the result; Specifically comprise the following steps:
A, real time embedded system MARTE model conversation are Timed Automata
I), for the MARTE component diagram that CCSL constraint is arranged in the MARTE model, according to the CCSL semanteme, component model is converted into to the emulation automat;
II), for the MARTE component diagram that there is no CCSL constraint in the MARTE model, at first, the MARTE precedence diagram in model is converted into to the monitoring automat; Then, the MARTE constitutional diagram in model is converted into to the object Timed Automata;
B, tool using UPPAAL verify and export the result to the Timed Automata model transformed.
2. verification method according to claim 1, it is characterized in that describedly according to the CCSL semanteme, component model being converted into to the emulation automat and being: according to each port CCSL semanteme, each port of member is modeled as to one from Timed Automata, respectively from Timed Automata, is responsible for simulating the agreement of corresponding ports; By whole Component Modeling, be main Timed Automata simultaneously, main Timed Automata is controlled respectively the behavior from Timed Automata by synchronization mechanism.
3. verification method according to claim 1 is characterized in that the described process that MARTE precedence diagram in model is converted into to the monitoring automat is: modelling verification is that transmission by message is as the modeling foundation; At first, using message as a monitored object, take over party and transmit leg according to each message, the time-constrain comprised in the context of message and message generates state transition and the signal variable of UPPAAL monitoring automat accordingly, and then be converted into the monitoring automat, be used for the interbehavior of whole system is monitored.
4. verification method according to claim 1, it is characterized in that the described process that MARTE constitutional diagram in model is converted into to Timed Automata is: the MARTE constitutional diagram is a component of a system modeling accordingly; The event information of component inside means by the MARTE constitutional diagram; Event information comprises outside interactive information and inner lastest imformation; Each state in the MARTE constitutional diagram is converted into to the location in Timed Automata correspondingly, according to the migration between state, correspondingly be converted into the edge in Timed Automata, for in constitutional diagram, calling of other objects being converted into to synchronization, the constitutional diagram built-in variable is upgraded and is converted into effect, and in constitutional diagram, control variable is converted into guard; Last extra synchronization and the effect of adding in relating to mutual edge again, so that the monitoring automat is collected signal.
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| CN103761084B (en) * | 2013-12-31 | 2017-01-18 | 宁波城市职业技术学院 | Internet-of-things credibility evaluation method based on extended activity sequence diagram model tests |
| CN103699394B (en) * | 2014-01-08 | 2017-04-12 | 夏夀民 | Method for automatically generating software system interaction framework based on multi-party communication protocol |
| CN105975695B (en) * | 2016-05-09 | 2018-12-14 | 华东师范大学 | The quantitative analysis method of ThingML model under Uncertain environments |
| CN108199940B (en) * | 2017-12-26 | 2021-07-20 | 首都师范大学 | Verification method and system for robot joint communication system model |
| CN109976712A (en) * | 2019-03-12 | 2019-07-05 | 中山大学 | One kind doing formalization verification method to network physical system requirements based on UPPAAL-SMC |
| CN110502815A (en) * | 2019-08-13 | 2019-11-26 | 华东师范大学 | A kind of time constraints specification normative language method based on SKETCH |
| CN111722539B (en) * | 2020-06-03 | 2021-05-28 | 西安交通大学 | Digital twin manufacturing unit behavior modeling method based on time automaton |
| CN112416337B (en) * | 2020-11-11 | 2023-05-02 | 北京京航计算通讯研究所 | Software architecture development system for aerospace embedded system |
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