CN102566959B - Image segmentation processing method and device thereof based on SGDMA (scatter gather direct memory access) - Google Patents
Image segmentation processing method and device thereof based on SGDMA (scatter gather direct memory access) Download PDFInfo
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- CN102566959B CN102566959B CN201110440503.7A CN201110440503A CN102566959B CN 102566959 B CN102566959 B CN 102566959B CN 201110440503 A CN201110440503 A CN 201110440503A CN 102566959 B CN102566959 B CN 102566959B
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Abstract
The invention discloses an image segmentation processing method and a device thereof based on SGDMA (scatter gather direct memory access). The method comprises the following steps: reading a DMA chain table of an entire image, wherein each node of the DMA chain table comprises an image segmentation starting x coordinate, an image segmentation starting y coordinate, image segmentation length, target address of the DMA and a pointer of the next node; getting image data of a corresponding target area according to contents of the current node of the DMA chain table; and transmitting the image data of the target area so as to facilitate the follow-up processing according to a preset strategy. The entire image is stored in an external memory of the device, and the DMA chain table of the entire image is stored in the external memory or a video memory/a memory; and a DMA controller is used for reading the DMA chain table of the entire image and further getting and transmitting the image data of the corresponding target area according to the contents of the current node of the DMA chain table; and GPUs (graphic processing units) are used for receiving the image data of the target area and then performing the follow-up processing. According to the image segmentation processing method and the device thereof disclosed by the invention, the special data is transmitted to each GPU, so that the bandwidth utilization rates of a bus and the external memory can be improved.
Description
Technical field
The present invention relates to digital image processing techniques, particularly relate to a kind of image segmentation processing method based on SGDMA and device, it is specially adapted to large-scale digital jointing display wall field.
Background technology
DMA (Direct Memory Access, direct memory access) be a kind of ideal style of high speed data transfer, data are directly transmitted by dma mode between internal memory and I/O equipment, its data manipulation is completed by dma controller and does not need the participation of CPU, thus greatly increases the utilization factor of CPU.
DMA has two kinds of implementations: one is Bulk transport formula DMA (block DMA) mode; Another kind is SGDMA (Scatter Gather DMA, dispersin polymerization formula DMA) mode, can by the data-moving of discontinuous storage to continuation address space, otherwise good.
DMA transmits in the process of data and usually requires that source physical address and target physical address are continuous print, but there will be source physical address and the discontinuous situation of target physical address in some applications, then DMA transmits to be divided into and repeatedly completes.For this kind of application, SGDMA mode describes the discontinuous storer of physics by a DMA chained list.After dma controller transfers one piece of physics continuous print data, transmit next block physics continuous print data according to DMA chained list, finally initiate once to interrupt.
At present, DMA is used widely.Such as, in image processing field, existing image processing process is roughly as follows: acquisition of image data, with dma mode by PCIE (Peripheral Component InterconnectionExpress, peripheral component interconnection is expanded) view data collected is sent to video memory or internal memory by bus, then GPU (Graphic Processing Unit, graphic process unit) or CPU is utilized to process view data.
For large-scale digital jointing display wall field, then need multiple GPU to process a secondary complete image, each GPU only needs the small block data processed wherein simultaneously.Therefore, image Segmentation Technology seems particularly important in this case, is summarized as follows.
Referring to Fig. 1, is the schematic diagram of conventional images dividing processing device.This Iamge Segmentation treating apparatus comprises: data acquisition unit 101, for gathering the decoded view data of video decoding chip 100, and is stored in external memory storage 104 by the view data of collection; Dma controller 102, for the image data transmission that will be stored in external memory storage 104 in video memory/internal memory 105; CPU 107, can be stored in external memory storage 104 or video memory/internal memory 105 by DMA chained list (specific constructive form refers to Fig. 2); GPU 108, is used as image procossing, wherein comprises image segmentating device 106, for realizing the segmentation to image.
As shown in Figure 1, owing to there being multiple unit can carry out read-write operation to external memory storage 104, therefore, in order to avoid producing conflict, the operation of these different units to external memory storage 104 can be controlled by carrying device 103 second month in a season.Specifically, when data acquisition unit 101 and dma controller 102 pairs of external memory storages 104 carry out read-write operation, by moderator 103 for distributing the control of read-write operation.Such as, if data acquisition unit 101 externally storer 104 initiate read-write requests, and dma controller 102 does not initiate read-write requests, and now the Read-write Catrol of external memory storage 104 power is distributed to data acquisition unit 101 by moderator 103; If data acquisition unit 101 and dma controller 102 initiate read-write requests simultaneously, now read-write controller power preferentially can be distributed to dma controller 102 by moderator 103.
It should be noted that, the dma controller 102 in above-mentioned Iamge Segmentation treating apparatus, data acquisition unit 101, moderator 103 can be realized by FPGA (Field Programmable Gate Array, field programmable gate array).
As shown in Figure 2, the exterior storage address of the data that can be transmitted as required by CPU 107 of above-mentioned DMA chained list, size of data and video memory or internal memory the information such as address and generate in advance.As shown in Figure 2, this DMA chained list can be check configuration or loop configuration, comprising data source address and data destination address.Also can comprise the information such as control word and next node pointer further, wherein in control word, comprise data bit width, whether data block size, current block end of transmission (EOT) cause the control informations such as interruption.DMA Bulk transport can be regarded as only containing a node, and next node pointer always points to the hash transmission of present node.
From above, prior art, when dividing processing one secondary complete image, is that an auxiliary image data is intactly sent to each GPU 108 by it simultaneously, is then completed the dividing function of image by GPU 108.The shortcoming of this Iamge Segmentation mode is:
(1) auxiliary image data is intactly sent to each GPU by this dividing method, and in fact just a part of data wherein of needing of each GPU, this causes data in transmitting procedure, need to take the bandwidth of bus, and therefore, this method causes the utilization factor of bandwidth in bus lower;
(2) view data is taken out from external memory storage, and too much invalid data also can reduce the bandwidth availability ratio of external memory storage;
(3) realize function of image segmentation by GPU, add the complexity of GPU programming.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of image segmentation processing method based on SGDMA and device, can bandwidth availability ratio be improved.
For solving above technical matters, technical scheme of the present invention is, a kind of image segmentation processing method based on SGDMA, comprising:
Read the DMA chained list of entire image, wherein each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, DMA destination address and next node pointer;
According to the content of current DMA chained list node, obtain corresponding target area image data;
Transmit this target area image data, to carry out subsequent treatment by predetermined policy.
More preferably, each DMA chained list node only operates the data line of entire image.
More preferably, Iamge Segmentation initial x coordinate, Iamge Segmentation length, the initial x coordinate of Iamge Segmentation and Iamge Segmentation length and be all less than or equal to image line resolution, the initial y coordinate of Iamge Segmentation is less than or equal to a resolution.
More preferably, each DMA chained list node comprises CRC check code.
More preferably, this DMA chained list is check configuration or loop configuration.
On this basis, the invention provides a kind of Iamge Segmentation treating apparatus based on SGDMA, comprise dma controller, be connected to the external storage of dma controller, be connected to the video memory/internal memory of dma controller by bus, be connected to the GPU of video memory/internal memory, wherein: in external storage, store entire image; Store the DMA chained list of entire image in external storage or video memory/internal memory, wherein each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, DMA destination address and next node pointer; Dma controller reads the DMA chained list of entire image, then according to the corresponding target area image data of the content obtaining of current DMA chained list node, transmits this target area image data afterwards; GPU receives this target area image data, and carries out subsequent treatment by predetermined policy.
More preferably, comprising the CPU being connected to dma controller by bus, for transmitting the address information of the exterior storage address of data, size of data and video memory or internal memory as required, generating and storing this DMA chained list in advance.
More preferably, comprise data acquisition unit, this data acquisition unit input end connects video decoding chip, and output terminal is connected to external storage, for gathering the decoded entire image data of video decoding chip, and is stored in external memory storage.
More preferably, comprise moderator, this moderator is connected between data acquisition unit and dma controller, for distributing data acquisition unit and dma controller to the read-write operation control of external memory storage.
More preferably, the DMA chained list in external storage or video memory/internal memory, each DMA chained list node comprises CRC check code.
Compared with prior art, the present invention is by amendment DMA chained list to realize Iamge Segmentation processing capacity, and it can obtain and include but are not limited to following beneficial effect:
(1) utilization ratio of bus bandwidth is improved.Dma controller only transmits the view data after segmentation to GPU according to the information of DMA chained list, instead of transmits complete view data to each GPU, therefore can reduce transmitted data amount, bus bandwidth utilization factor is improved;
(2) bandwidth availability ratio of external memory storage is improved.After amendment DMA chained list chained list, the invalid data read from external storage reduces, and this can improve the bandwidth availability ratio of external memory storage undoubtedly.
(3) the programming difficulty of GPU is reduced.In GPU, operational order can adopt universal program, and difference is only that the image block initial parameters obtained is different, and difficulty of thus programming reduces greatly.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of conventional images dividing processing device;
Fig. 2 is the data structure diagram of DMA chained list in conventional images division processing method;
Fig. 3 is the image segmentation processing method process flow diagram that the present invention is based on SGDMA;
Fig. 4 is the data structure diagram of DMA chained list in image segmentation processing method of the present invention;
Fig. 5 is the schematic diagram of the Iamge Segmentation treating apparatus that the present invention is based on SGDMA.
Embodiment
Core concept of the present invention is, by revising the DMA list structure of entire image, realizes the part image data only transmitting corresponding region to GPU.
In order to make those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Simultaneously see Fig. 3, Fig. 4, represent the process flow diagram that the present invention is based on the image segmentation processing method of SGDMA.This figure is that main body is described with DMA, and its basic step comprises:
The DMA chained list of S301, reading entire image, wherein each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, DMA destination address and next node pointer (as Fig. 4), and each DMA chained list node comprises CRC check code further.
Above-mentioned DMA chained list can be check configuration or loop configuration, and the information such as address of the exterior storage address of the data that it can be transmitted as required by CPU, size of data and video memory or internal memory generates in advance.More preferably.Each DMA chained list node application drawing is as the data of a line, wherein: numerical value and the segmentation length of the initial x coordinate of Iamge Segmentation all can not be greater than image line resolution, the initial y coordinate of Iamge Segmentation can not be greater than a resolution, and the initial x coordinate of Iamge Segmentation adds that segmentation length can not be greater than image line resolution; And CRC check code is for ensureing the reliability of each node.
S302, content according to current DMA chained list node, obtain corresponding target area image data.
According to DMA chained list node pointer, dma controller only reads the view data of corresponding cut zone at every turn, subtracts small data transmission quantity thus, is conducive to utilizing bandwidth.
S303, transmit this target area image data, to carry out subsequent treatment by predetermined policy.
After transmitting these target area image data, follow-up GPU can process accordingly to the data of this segmentation image-region, specifically according to prior art, repeats no more.
In above embodiment, the advantage of image partition method is: (1) dma controller only transmits the view data after segmentation to GPU according to the information of DMA chained list, instead of transmit complete view data to each GPU, therefore can reduce transmitted data amount, bus bandwidth utilization factor is improved; (2) by amendment DMA chained list chained list, the invalid data read from external storage reduces, and this can improve the bandwidth availability ratio of external memory storage undoubtedly; (3) in GPU, operational order can adopt universal program, and difference is only that the image block initial parameters obtained is different, and difficulty of thus programming reduces greatly.
Above image segmentation processing method of the present invention is illustrated, correspondingly Iamge Segmentation treating apparatus of the present invention is described below.
See Fig. 5, represent the preferred embodiment that the present invention is based on the Iamge Segmentation treating apparatus of SGDMA.This Iamge Segmentation treating apparatus comprises the elements such as video decoding chip 100, data acquisition unit 101, dma controller 102, moderator 103, external memory storage 104, video memory/internal memory 105, GPU 108, CPU 107, wherein: video memory/internal memory 105 and CPU 107 are connected to dma controller 102 by bus, this video memory/internal memory 105 is also connected with GPU; External storage 104 accesses dma controller 102 and data acquisition unit 101 by moderator 103, and this data acquisition unit 101 is also connected to video decoding chip 100.More preferably, dma controller 102, data acquisition unit 101, moderator 103 are realized by FPGA.Below respectively each main element is described.
Data acquisition unit 101, for gathering the decoded view data of video decoding chip 100, and is stored into the view data of collection in external memory storage 104.
Not only store view picture data image in external memory storage 104, also can store the DMA chained list (this DMA chained list page can be stored in video memory/internal memory 105) of entire image.Each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, CRC check code, DMA destination address and next node pointer.More preferably.Each DMA chained list node application drawing as the data of a line, wherein: the numerical value of Iamge Segmentation initial x coordinate, Iamge Segmentation length, the initial x coordinate of Iamge Segmentation and Iamge Segmentation length sum all can not be greater than image line resolution; The initial y coordinate of Iamge Segmentation can not be greater than a resolution; And CRC check code can in order to ensure the reliability of each node.
Moderator 103, for distributing data acquisition unit and dma controller to the read-write operation control of external memory storage.Such as, when data acquisition unit 101 externally storer 104 initiate read-write requests and dma controller 102 do not initiate read-write requests time, the Read-write Catrol of external memory storage 104 power is distributed to data acquisition unit 101; When data acquisition unit 101 and dma controller 102 initiate read-write requests simultaneously, preferentially read-write controller power is distributed to dma controller 102.
Dma controller 102, obtaining to the Read-write Catrol of external storage 104 temporary, read the DMA chained list of entire image, then according to the corresponding target area image data of the content obtaining of current DMA chained list node, transmit these target area image data afterwards in video memory/internal memory 105.
GPU 108, then receive these target area image data in video memory/internal memory 105, and carry out subsequent treatment by predetermined policy, and concrete process then can by prior art process.
CPU 107, can be used for transmitting as required the address information of the exterior storage address of data, size of data and video memory or internal memory, generate and store this DMA chained list in advance in external storage 104 or video memory/internal memory 105, so that dma controller 102 carries out corresponding operating.
In this embodiment, Iamge Segmentation device is by amendment DMA chained list, can transmit the data in respective objects region, thus have the following advantages: (1) improves the utilization ratio of bus bandwidth for each GPU 108; (2) bandwidth utilization efficiency of external memory storage is improved; (3) the programming difficulty of GPU is reduced.
Below be only the preferred embodiment of the present invention, it should be pointed out that above-mentioned preferred implementation should not be considered as limitation of the present invention, protection scope of the present invention should be as the criterion with claim limited range.For those skilled in the art, without departing from the spirit and scope of the present invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. based on an image segmentation processing method of SGDMA, it is characterized in that, comprising:
Read the DMA chained list of entire image, wherein each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, DMA destination address and next node pointer; Wherein, described DMA chained list generates in advance;
According to the content of current DMA chained list node, obtain corresponding target area image data;
Transmit this target area image data, to carry out subsequent treatment by predetermined policy.
2., as claimed in claim 1 based on the image segmentation processing method of SGDMA, it is characterized in that, each DMA chained list node only operates the data line of entire image.
3. as claimed in claim 2 based on the image segmentation processing method of SGDMA, it is characterized in that, Iamge Segmentation initial x coordinate, Iamge Segmentation length, the initial x coordinate of Iamge Segmentation and Iamge Segmentation length and be all less than or equal to image line resolution, the initial y coordinate of Iamge Segmentation is less than or equal to a resolution.
4., as claimed in claim 1 based on the image segmentation processing method of SGDMA, it is characterized in that, each DMA chained list node comprises CRC check code.
5. the image segmentation processing method based on SGDMA as described in any one of Claims 1 to 4, is characterized in that, this DMA chained list is check configuration or loop configuration.
6. the Iamge Segmentation treating apparatus based on SGDMA, it is characterized in that, comprise dma controller, be connected to the external storage of dma controller, be connected to the video memory/internal memory of dma controller by bus, be connected to the GPU of video memory/internal memory, wherein: in external storage, store entire image; Store the DMA chained list of entire image in external storage or video memory/internal memory, wherein each DMA chained list node comprises Iamge Segmentation initial x coordinate, the initial y coordinate of Iamge Segmentation, Iamge Segmentation length, DMA destination address and next node pointer; Dma controller reads the DMA chained list of entire image, then according to the corresponding target area image data of the content obtaining of current DMA chained list node, transmits this target area image data afterwards; GPU receives this target area image data, and carries out subsequent treatment by predetermined policy.
7. as claimed in claim 6 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise the CPU being connected to dma controller by bus, for transmitting the address information of the exterior storage address of data, size of data and video memory or internal memory as required, generate and store this DMA chained list in advance.
8. as claimed in claim 6 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise data acquisition unit, this data acquisition unit input end connects video decoding chip, output terminal is connected to external storage, for gathering the decoded entire image data of video decoding chip, and be stored in external storage.
9. as claimed in claim 8 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise moderator, this moderator is connected between data acquisition unit and dma controller, for distributing data acquisition unit and dma controller to the read-write operation control of external storage.
10. the Iamge Segmentation treating apparatus based on SGDMA as described in any one of claim 6 ~ 9, is characterized in that, the DMA chained list in external storage or video memory/internal memory, each DMA chained list node comprises CRC check code.
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| CN104363402B (en) * | 2014-10-27 | 2017-11-24 | 同辉佳视（北京）信息技术股份有限公司 | A kind of method and apparatus of quick display video |
| CN105491281B (en) * | 2015-11-24 | 2019-01-25 | 深圳眼神智能科技有限公司 | The method and apparatus for improving image acquisition speed |
| CN111061443B (en) * | 2018-10-17 | 2023-10-10 | 杭州海康威视数字技术股份有限公司 | Menu image display method, menu image display device, electronic equipment and machine-readable storage medium |
| CN109669654A (en) * | 2018-12-22 | 2019-04-23 | 威创集团股份有限公司 | A kind of combination display methods and device |
| CN110427265A (en) * | 2019-07-03 | 2019-11-08 | 平安科技（深圳）有限公司 | Method, apparatus, computer equipment and the storage medium of recognition of face |
| CN114785748B (en) * | 2022-06-21 | 2022-09-16 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954818A (en) * | 1985-10-18 | 1990-09-04 | Hitachi, Ltd. | Multi-window display control system |
| CN102005028A (en) * | 2010-11-18 | 2011-04-06 | 福州瑞芯微电子有限公司 | Image processing system using special DMA for images |
-
2011
- 2011-12-23 CN CN201110440503.7A patent/CN102566959B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954818A (en) * | 1985-10-18 | 1990-09-04 | Hitachi, Ltd. | Multi-window display control system |
| CN102005028A (en) * | 2010-11-18 | 2011-04-06 | 福州瑞芯微电子有限公司 | Image processing system using special DMA for images |
Non-Patent Citations (2)
| Title |
|---|
| 基于PLB总线的多通道SGDMA设计;陈卓等;《航空电子技术》;20090522;第40卷(第1期);第12页右栏第4段,第14页第3段,第15页左栏第2段 * |
| 求解二值图像连通域的改进算法;李欢等;《计算机与现代化》;20050512(第4期);第12页左栏第1-15段 * |
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