CN102565660A - Superspeed drain current gate voltage (Id-Vg) test method applied to metal oxide semiconductor field effect transistors (MOSFETs) elements - Google Patents
Superspeed drain current gate voltage (Id-Vg) test method applied to metal oxide semiconductor field effect transistors (MOSFETs) elements Download PDFInfo
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- CN102565660A CN102565660A CN201210000912XA CN201210000912A CN102565660A CN 102565660 A CN102565660 A CN 102565660A CN 201210000912X A CN201210000912X A CN 201210000912XA CN 201210000912 A CN201210000912 A CN 201210000912A CN 102565660 A CN102565660 A CN 102565660A
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Abstract
The invention belongs to the technical field of metal oxide semiconductor transistor tests, and particularly relates to a superspeed drain current gate voltage (Id-Vg) test method applied to high performance metal oxide semiconductor field effect transistors (MOSFETs) elements. The method includes replacing a transistor to be tested with a chip-shaped resistor which is access to a transistor on resistance value in a testing loop, and obtaining two pulse signals: a grid voltage pulse signal and a voltage signal which is amplified by the drain current penetrating through an Op current voltage amplifier, and then performing a synchronous correction of the signals; testing and obtaining a displacement current signal of the transistor when the power supply voltage of a same testing platform is set as zero, and then performing correction of errors caused by the displacement current. According to the superspeed Id-Vg test method applied to the MOSFETs elements, the method has a simple structure, almost no cost, remarkable effects and accurate testing, and is applicable for the study of the reliability of gate dielectric of high-dielectric permittivity on high current performance MOSFETs which uses structures of III-V compound semiconductor, germanium, graphene, various nanotube and wires and the like as current carrier channels.
Description
Technical field
The invention belongs to metal oxide semiconductor transistor (MOSFET) technical field of measurement and test, be specifically related to a kind of I that is used for the high performance MOSFET transistor device
d-V
gMethod of testing.
Background technology
Along with the transistor size in the integrated circuit narrows down to below the 32 nm nodes, the exploration of relevant small size device technology is more urgent.Realize the further scaled down of device, must solve the factor of existing restriction development, could improve transistorized performance through adopting new material, technology or new device architecture.Find out the developing direction of the following integrated circuit technique of listing from Intel Company; Adopt new channel material,, can promote the carrier mobility of raceway groove effectively like the III-V compound semiconductor; Thereby improve the operating rate of integrated circuit, be expected in the technology below the 16nm technology node.Yet; Reliability testing for various high workload current capability MOSFET devices; For example based on III-V family semiconductor, Ge, Graphene, various nanotube, the isostructural MOSFETs of line, the instability that the bias voltage temperature causes, high-k (high-k) gate dielectric material characteristic none not with semiconductor channel in the charge carrier activity of being caught fast by media defect relevant.In fact, charge carrier is caught by gate medium oxide layer or boundary defect fast and the compound problem of charge carrier that causes is an important factors that influences the MOSFET performance, for example the instability of threshold voltage, channel carrier mobility variation.
According to the gap of interface trap and surperficial carrier energy position, it is generally acknowledged that interface trap is caught and discharge the charge carrier time (be inversely proportional to and catch boundary coefficient) greatly about nanosecond to microsecond level.Spread to high dielectric oxide layer trap by interface trap, its time of catching the release charge carrier is greatly more than the microsecond level.Thereby traditional DC current voltage test method records the current corresponding signal through linear ramp and obtains complete current-voltage (I-V) information.Although the clock setting of instrument itself has very big difference, this test process needs about several seconds usually.Therefore, the DC current voltage test method is difficult to the transmission activity between the charge carrier and various trap in the complete MOSFET device that reflects the high workload current capability.Thereby, in a hurry need through reliably fast test macro obtain charge carrier action message accurately.
Utilize quick I
d-V
gThe trap that the method for (transfer characteristic curve of device) is tested the high-k dielectric layer is suggested very early, has a large amount of documents to adopt the fast state and the slow state reaction of the method research trap.Quick I
d-V
gGenerally the grid at the MOSFET device loads a pulse signal of conversion fast.When grid voltage from low level to the process of high level conversion because the time is enough short, the electronics on device channel surface also has little time to be caught by the trap of gate medium, thereby obtains the intrinsic current characteristic of channel material.Along with grid voltage transfers high level to, when the trap of gate medium had been caught channel electrons gradually and tended towards stability state, therefore the channel surface electromotive force was affected, and makes channel current reduce gradually until tending towards stability.
Yet,, when especially being applied to large-area very-high performance device (as based on MOSFETs devices such as III-V family semiconductor, Ge, Graphene, various nanotube, line structures) measurement, the work discussion is arranged seldom but about the deficiency of the method.If these situation are not analyzed, and directly adopting said method tends to cause more serious error, is difficult to distinguish the influence of various defectives to device performance, sometimes even can get the wrong sow by the ear.For this reason, the inventive method has proposed a kind of improved quick I
d-V
gMethod of testing is so that be applied in the research of high-k gate medium reliability aspect on the high current capability MOSFETs transistor.
Summary of the invention
The object of the present invention is to provide a kind of accurately measurement high speed MOSFET device I
d-V
gThe method of characteristic.
Hypervelocity I of the present invention
d-V
gMethod of testing to when practical devices is carried out high-frequency test, no longer can be ignored the displacement current signal of device, must revise this signal, so that accurately measure high-k medium or defective at the interface on it to the influence of device electric property.It is characterized in that the signal when transistor performance tested carries out synchronous processing, and the error that the displacement current signal causes is revised.
Described hypervelocity I
d-V
gMethod of testing; Be in test loop, to replace test transistor with a pellet resistance near transistor ON resistance resistance; Record two pulse signals: the voltage signal after grid voltage pulse signal and drain current amplify through Op current/voltage amplifier, thus carry out the correction of signal Synchronization.
Described hypervelocity I
d-V
gMethod of testing is when supply voltage being set on same experiment porch being zero, records transistorized displacement current signal, thereby carries out the error correction that displacement current causes.
Described hypervelocity I
d-V
gMethod of testing, concrete steps comprise:
(1) a design computing (Op) current/voltage amplifier.Its enlargement factor and bandwidth are set as required, are 500 like enlargement factor, and bandwidth is 30 MHz etc.;
(2) replace transistor with a pellet resistance, measure the relative time delay time between grid pulse signal and the output pulse signal near transistor ON resistance resistance;
(3) supply voltage is set to zero, and transistor gate is kept same pulse signal, records transistorized displacement current error signal;
(4) in the correction and the correction of relative time delay time of the enterprising line displacement current error signal of current signal of prediction;
(5) corresponding grid voltage and drain current pulse signal convert I to
d-V
gRelation curve.
The present invention has the following advantages:
(1) homemade pellet resistance is simple and reliable, is easy on the semiconductor probe platform, realize, effect highly significant, cost are almost nil.
(2) step of signal correction and signal Synchronization is very effectively simple, is prone to realize.
(3) be 100 μ m at area
2Rank is above, the raceway groove ON resistance is merely on the nMOSFETs of III-V family of 37 Ω, finally can measure the oxygen trap and catch charge carrier soon to the response more than 5 ns.
The present invention is applicable to that with structures such as III-V family semiconductor, germanium, Graphene, various nanotube, lines be the research of the high current capability MOSFETs transistor k gate dielectric on high reliability aspect of carrier channels.
Description of drawings
Fig. 1 hypervelocity I of the present invention
d-V
gThe circuit design of method of testing.
Fig. 2 hypervelocity I of the present invention
d-V
gThe displacement current correction effect synoptic diagram of method of testing.
Fig. 3 hypervelocity I of the present invention
d-V
gThe test limits synoptic diagram of method of testing.
Embodiment
Embodiment of the present invention is described with reference to the drawings below.In the description of back, identical Reference numeral is represented identical assembly, and it is repeated in this description omission.
At first, circuit design of the present invention is described.Fig. 1 representes circuit structure of the present invention.The signal that pulse producer (101) produces is through behind the probe, provides on the mosfet transistor (103) of suitable gate voltage pulse signal (106) to high-performance.The bandwidth of digital oscilloscope (105) is 1 GHz.In order to collect abundant data point in nanosecond fast rise or negative edge, oscillograph (105) sampling rate is set to 4 GS/s.The rising edge of gate voltage pulse signal (106), negative edge time and dutycycle all are adjustable.Supply voltage (102) is gone up at mosfet transistor (103) and is loaded the required voltage signal.Leakage current signal (108) process that MOS transistor (103) is corresponding changes into voltage signal (109) after the undistorted amplification filtering of Op amplifier (104) of design, input to digital oscilloscope (105).The gate voltage pulse signal (106) that while pulse producer (101) sends also inputs to and shows digital wave device (105) signal as a setting.In the entire circuit system, set up public ground (110).When circuit connects, guarantee that Op amplifier (104) drain potentials and public ground (110) are consistent.
As shown in Figure 1, arrive the two paths of signals that has of oscillograph (105): grid voltage pulse signal (106) and drain current (108) voltage signal (109) after through Op current/voltage amplifier (104) amplification.In order accurately to extract I
d-V
gData relationship, must must guarantee the synchronism of two paths of signals.And behind latter process MOSFET (103) and the Op amplifier (104), comparing the former has had the regular hour time-delay.Time-delay between two signals of accurate estimation replaces device MOSFET (103) with a chip resistor in the loop.Two paths of signals is the full sized pules signal like this, gets the delay time that the half the time point of corresponding rising edge calculates the loop.Each when changing the grid voltage pulse signal, all record the delay time of two paths of signals earlier with this resistance, so that revise the mistiming of two paths of signals, guarantee the synchronous of voltage and current signal, obtain I accurately
d-V
gCurve.
Fig. 2 has provided the contrast effect before and after the displacement current correction.The MOS transistor (103) of test is Al
2O
3/ In
0.53Ga
0.47As NMOSFETs, grid length is 1 μ m, grid width is 100 μ m.Grid impulse voltage signal V
g(106) shown in Fig. 2 mazarine curve, low level is-1 V, and high level is 4 V, and the rising edge negative edge is 100 ns, and the cycle is 1 μ s, and dutycycle is 50%.Channel current signal (108) when light blue curve is a supply voltage (102) for-5 mV, displacement current signal definition are the signal that supply voltage (102) records when being 0 V, shown in red curve among the figure.Clearly, compare the channel current signal (108) that records, the displacement current signal almost with the current signal that records on the same order of magnitude, and cause current signal (108) distortion that records very serious.After displacement current revised, shown in Fig. 2 pink colour curve, current signal (108) curve was as MOSFET transfer characteristic curve shape.In order further to have confirmed the effect of displacement current error correction, when being set to-50 mV, adopt supply voltage (102) same step to record channel current signal (108).Because when supply voltage (102) was-5 mV and-50 mV, transistor all was in the range of linearity, so its corresponding channel current signal (109) should differ 10 times.As hypothesis, shown in the green curve 0.099 times of the channel current signal (108) that records during for-50 mV of supply voltage (102) like figure, the channel current signal (108) that records during for-5 mV with supply voltage (102) coincide good.This and the identical favorable linearity characteristic of theory hypothesis have further confirmed the accurate effect of displacement current error correction.Owing to use same set of equipment, same grid voltage waveform testing, this displacement current method of testing is fairly simple, accurate and effective.
Fig. 3 is the current pulse signal of MOS transistor (103) when the rising edge negative edge time being reduced to 50 ns.Obviously, can change rapidly between current pulse signal low level that obtains after the correction and the high level, have no distortion to exist.Proved also that thus above-mentioned high-frequency circuit correction is very effective.
The foregoing description is of the present invention giving an example; Although disclose most preferred embodiment of the present invention and accompanying drawing for the purpose of illustration; But it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the present invention and appended claim, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.
Claims (2)
1. hypervelocity I who is applied to mosfet transistor
d-V
gMethod of testing comprises that the signal when transistor performance tested carries out synchronous processing, and the error that the displacement current signal causes is revised; It is characterized in that: be in test loop, to replace test transistor with a pellet resistance near transistor ON resistance resistance; Record two pulse signals: the voltage signal after grid voltage pulse signal and drain current amplify through Op current/voltage amplifier, thus carry out the correction of signal Synchronization; And when supply voltage being set being zero on same experiment porch, record transistorized displacement current signal, thereby carry out the error correction that displacement current causes.
2. hypervelocity I according to claim 1
d-V
gMethod of testing is characterized in that concrete steps comprise:
(1) a design computing (Op) current/voltage amplifier;
(2) replace transistor with a pellet resistance, measure the relative time delay time between grid pulse signal and the output pulse signal near transistor ON resistance resistance;
(3) supply voltage is set to zero, and transistor gate is kept same pulse signal, records transistorized displacement current error signal;
(4) in the correction and the correction of relative time delay time of the enterprising line displacement current error signal of current signal of prediction;
(5) corresponding grid voltage and drain current pulse signal convert I to
d-V
gRelation curve.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210000912XA CN102565660A (en) | 2012-01-04 | 2012-01-04 | Superspeed drain current gate voltage (Id-Vg) test method applied to metal oxide semiconductor field effect transistors (MOSFETs) elements |
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| CN201210000912XA CN102565660A (en) | 2012-01-04 | 2012-01-04 | Superspeed drain current gate voltage (Id-Vg) test method applied to metal oxide semiconductor field effect transistors (MOSFETs) elements |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104820178A (en) * | 2015-04-09 | 2015-08-05 | 深圳深爱半导体股份有限公司 | Method for screening field effect transistor with double-line defect in transfer characteristic curve |
| CN106680686A (en) * | 2016-12-29 | 2017-05-17 | 浙江大学 | Method of improving picosecond-level superfast electrical property testing accuracy of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS517034B1 (en) * | 1970-01-20 | 1976-03-04 | ||
| CN1797019A (en) * | 2004-12-27 | 2006-07-05 | 安捷伦科技公司 | Method for measuring characteristics of fets |
-
2012
- 2012-01-04 CN CN201210000912XA patent/CN102565660A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS517034B1 (en) * | 1970-01-20 | 1976-03-04 | ||
| CN1797019A (en) * | 2004-12-27 | 2006-07-05 | 安捷伦科技公司 | Method for measuring characteristics of fets |
Non-Patent Citations (3)
| Title |
|---|
| 《IEEE ELECTRON DEVICE LETTERS》 20060131 C. Shen等 A Fast Measurement Technique of MOSFET Id-Vg Characteristics 55-57 1,2 第27卷, 第1期 * |
| C. SHEN等: "A Fast Measurement Technique of MOSFET Id–Vg Characteristics", 《IEEE ELECTRON DEVICE LETTERS》, vol. 27, no. 1, 31 January 2006 (2006-01-31), pages 55 - 57 * |
| C. WANG等: "An improved fast Id-Vg measurement technology with expanded application range", 《2009 IIRW FINAL REPORT》, 22 October 2009 (2009-10-22), pages 163 - 165 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104820178A (en) * | 2015-04-09 | 2015-08-05 | 深圳深爱半导体股份有限公司 | Method for screening field effect transistor with double-line defect in transfer characteristic curve |
| CN104820178B (en) * | 2015-04-09 | 2017-12-29 | 深圳深爱半导体股份有限公司 | The method that screening transfer characteristic curve has the FET of two-wire defect |
| CN106680686A (en) * | 2016-12-29 | 2017-05-17 | 浙江大学 | Method of improving picosecond-level superfast electrical property testing accuracy of semiconductor device |
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Application publication date: 20120711 |