CN102547196B - Digital video interface data recovery circuit - Google Patents
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- CN102547196B CN102547196B CN201110447192.7A CN201110447192A CN102547196B CN 102547196 B CN102547196 B CN 102547196B CN 201110447192 A CN201110447192 A CN 201110447192A CN 102547196 B CN102547196 B CN 102547196B
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Abstract
The invention provides a digital video interface data recovery circuit, which comprises a charge pump phase-locked loop, an oversampler and a data recovery unit; the charge pump phase-locked loop receives TMDS (Transition Minimized Differential Signaling) clock input and generates 20-phase clock output two times higher than TMDS clock frequency; the oversampler samples the inputted high-speed serial TMDS data signals; and the data recovery unit recovers raw digital video data according to the 40-bit parallel data outputted by the oversampler. The digital video interface data recovery circuit provided by the invention can solve the problem that the digital phase-locked loop in the prior art is not stable enough, and the error rate of data transmission is decreased.
Description
Technical field
The present invention relates to a kind of data recovery circuit of digital visual interface, particularly relate to the data recovery circuit of over-sampling structure.
Background technology
Digital visual interface or HDMI (High Definition Multimedia Interface) adopt transition minimized differential signaling (Transition Minimized Differential Signaling, hereinafter to be referred as TMDS) encode, TMDS coding is converted into 10 by 8 original digital video signals and has the serial signal sequence that minimizes transmission difference, row field signal direct coding becomes 10 Bits Serial bursts, row field signal and original digital video signal are by data enable (Data Enable, hereinafter to be referred as DE) signal distinguishing.A complete TMDS transmission link comprises a clock TMDS passage and three data TMDS passages, clock TMDS channel frequence is 25 ~ 165MHz, three data TMDS passages are respectively used to the serial TMDS signal of transmission red (R), green (G), blue (B), the data transmission rate of data TMDS passage is ten times of clock TMDS passage, that is to say in the clock TMDS cycle and has ten Bits Serial TMDS data in transmission.
The main task of digital video interface data recovery circuit is according to clock TMDS channel signal and three data TMDS channel signals of input, recovers DE signal, row field signal and the raw digital video signal of digital visual interface.The high speed data transmission system sending separately for clock signal generally all adopts over-sampling (over-sampling) technology to carry out data recovery.U.S. Patent number is US5,905,769, title is data reconstruction method and the system that discloses a kind of three times of over-samplings (3X over-sampling) in the patent document of " the insensitive multi-channel Transmission System of high speed deflection and method " (System and method for high-speed skew-insensitive multi-channel data transmission).China Patent No. is data reconstruction method and the system that discloses a kind of four times of over-samplings in CN101321052A, the title patent document that is " data reconstruction method of four times of over-samplings and system ".
Above two kinds of digital visual interface data reconstruction methods all directly carry out data recovery to the TMDS signal of input, and method adopts DPLL digital phase-locked loop (Digital Phase Locked Loop, hereinafter to be referred as DPLL) to carry out data recovery.Too poor when the serial data signal of input, digital phase-locked loop may be stable not, causes data error code.
Summary of the invention
The present invention proposes a kind of digital video interface data recovery circuit, adopt the method can solve the problem that the digital phase-locked loop that exists in prior art may be stable not, reduce the error rate of transfer of data.The present invention adopts four times of over-sampling devices to sample to the TMDS data-signal of input, and within a clock TMDS cycle, sampler is exported 40 parallel-by-bit data.The present invention is based on TMDS and be coded in the difference of the TMDS data-signal conversion times of exporting when DE is different value, at digital visual interface receiving terminal, detect in advance DE signal.The 40 parallel-by-bit data that the DE that utilization of the present invention detects samples during for low level are entered horizontal phasing control.The present invention, according to 40 parallel-by-bit data of sampler output, selects misdata minimum number and the maximum phase place output of correct data number in four possible phase places, and the phase place of selection is recovered for the data of digital visual interface.
For solving above-mentioned technical problem, the present invention by the following technical solutions:
Digital video interface data recovery circuit, this circuit comprises:
Charge pump phase lock loop, for receiving the input of TMDS clock, produce the 20 phase clock outputs that double TMDS clock frequency;
Over-sampling device, samples to the high speed serialization TMDS data-signal of input, and a TMDS data-signal is sampled four times, and within a clock TMDS cycle, sampler is exported 40 parallel-by-bit data;
Data recovery unit, according to 40 parallel-by-bit data of over-sampling device output, recovers original digital of digital video data.
Further:
Recovery unit comprises:
DE detector, detects DE signal according to the conversion times of 40 bit data of over-sampling device output;
Phase-detection logical block, when DE is low level, to 40 bit data of the sampler output phase-detection of dividing into groups, every four data form a phase-detection elementary cell, phase-detection elementary cell detects two kinds of data modes, is respectively correct data state or misdata state;
Phase-detection pretreatment unit, processes correct data state and the misdata state of the output of phase-detection logical block, exports four corresponding cumulative correct data numbers of possible Selecting phasing and misdata number;
Phase control state machine, processes the signal of phase-detection pretreatment unit output, selects misdata minimum number and the maximum phase place output of correct data number in four possible phase places;
Output data selection unit, according to the Selecting phasing of phase control state machine output, the digital of digital video data that output recovers.
Described DE detector comprises:
The four roads DE detecting unit that walks abreast, carries out DE detection to 40 parallel-by-bit data of input;
The output state that the parallel DE in four tunnels detects carries out logic OR operation, deburring operation, and rising edge detects operation.
Described DE detector 301 also comprises two signal map module 310-0, 310-1 and serial shift register, wherein signal map module 310-0 is mapped to 40 parallel-by-bit data D the data output signal A0 of four phase places, A1, A2, A3, signal map module 310-1 is mapped to 40 parallel-by-bit data D131 the data output signal B0 of four phase places, B1, B2, B3, A0 and B0 are 0 phase mapping signals, B0 is the one-period time delay output of A0, A1 and B1 are 1 phase mapping signals, B1 is the one-period time delay output of A1, A2 and B2 are 2 phase mapping signals, B2 is the one-period time delay output of A2, A3 and B3 are 3 phase mapping signals, B3 is the one-period time delay output of A3, two same phases and have the mapping signal A0B0 of one-period time delay, A1B1, A2B2, A3B3 is input to respectively four DE detecting unit 320-0, 320-1, 320-2, 320-3, four DE detecting units are exported four road DE detection signal match0, match1, match2, match3, signal match is that four described DE detecting units are exported four road DE detection signal match0, match1, match2, match3) or logic, signal match sends into serial shift register, shift register output carries out logic OR operation, this logic OR operates the matched signal match_filt after the little burr output filtering that filters out signal match, filtered matched signal match_filt sends into rising edge testing circuit output DE detection signal de_detected, DE detection signal de_detected is that high level represents to detect effective DE signal.
The inside of described each DE detecting unit comprises ten parallel DE detection sub-unit, and the signal of ten detection sub-unit outputs carries out logic OR operation output detection signal match0; Described DE detection sub-unit inside comprises mapping block and detection sub-unit logical circuit.
Described phase-detection logic comprises:
The parallel phase-detection subelement in four tunnels carries out phase-detection to 40 parallel-by-bit data of input;
Phase-detection subelement carries out phase-detection to 40 parallel-by-bit data of input, and each phase-detection subelement inside comprises ten parallel detecting units, and each detecting unit is input as four figures certificate, is output as error flag and accurate indication.
Described each parallel detecting unit comprises:
The first XOR gate, produces signal a after the zero-bit data in parallel input four figures certificate and the 3rd bit data;
The second XOR gate, produces signal b after the first bit data in parallel input four figures certificate and second data, and this signal is misdata signal E;
The first not gate, signal a produces signal c;
The second not gate, signal b produces signal d;
With door, signal c and signal d produce data correct signal O.
Described phase-detection preliminary treatment comprises:
Error in data number and the data correct number of the parallel phase error accumulator in four tunnels to four outs of phase adds up;
The error in data number of four outs of phase is sent into minimum detector, produces minimum value marking signal;
The data correct number of four outs of phase is sent into maximum value detector, produces maximum marking signal;
Minimum value marking signal and maximum marking signal carry out logical AND operation, produce maximum and minimum value marking signal.
The judgment criterion of described phase control FSM is:
According to maximum and minimum value marking signal, carry out Selecting phasing, make the phase place of selecting have error in data number minimum and data correct number maximum, the minimum priority of error in data number is higher than data correct number maximum.
The invention allows for a kind of new data reconstruction method that utilizes above-mentioned digital video interface data recovery circuit to carry out, comprise the following steps: that DE detects, according to the conversion times of 40 bit data of sampler output, detect DE signal; Phase-detection logic, when DE is low level, to 40 bit data of the sampler output phase-detection of dividing into groups, every four data form a phase-detection elementary cell, phase-detection elementary cell detects two kinds of data modes, is respectively correct data state or misdata state; Phase-detection preliminary treatment, processes correct data state or the misdata state of the output of phase-detection logic, exports four corresponding cumulative correct data numbers of possible Selecting phasing and misdata number; Phase control FSM(is phase control state machine Finite State Machine), the signal of phase-detection preliminary treatment output is processed, select misdata minimum number and the maximum phase place output of correct data number in four possible phase places; Output data selection, according to the Selecting phasing of phase control state machine output, the digital of digital video data that output recovers.
Compared with prior art, the invention has the beneficial effects as follows:
The digital video interface data recovery circuit that the present invention proposes can solve the problem that the digital phase-locked loop that exists in prior art may be stable not, reduces the error rate of transfer of data.
Accompanying drawing explanation
Fig. 1 is digital video interface data recovery circuit structural representation of the present invention;
Fig. 2 is digital video interface data recovery circuit TMDS data sampling sequential chart of the present invention;
Fig. 3 is DE detector schematic diagram of the present invention;
Fig. 4 is DE detector data mapping relations schematic diagram of the present invention;
Fig. 5 is DE detecting unit structural representation of the present invention;
Fig. 6 is DE detection sub-unit structural representation of the present invention;
Fig. 7 is that DE detection sub-unit data-mapping of the present invention is related to schematic diagram;
Fig. 8 is phase-detection logical construction schematic diagram of the present invention;
Fig. 9 is phase-detection logical data mapping relations schematic diagram of the present invention;
Figure 10 is phase-detection sub-unit structure schematic diagram of the present invention;
Figure 11 is phase-detection basic cell structure schematic diagram of the present invention;
Figure 12 is phase-detection pre-processing structure schematic diagram of the present invention;
Figure 13 is phase error accumulator structural representation of the present invention;
Figure 14 is phase control FSM schematic diagram of the present invention;
Figure 15 is that the present invention exports data selection structural representation.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further elaborated.
As shown in Figure 1, a kind of digital video interface data recovery circuit, this circuit comprises charge pump phase lock loop 101, over-sampling device 201, data recovery unit 300.Wherein, data recovery unit 300 comprises DE detector 301, phase-detection logical block 302, phase-detection pretreatment unit 303, output data selection unit 304, phase control FSM305.
Charge pump phase lock loop 101 receives TMDS clock signal 10, and output doubles 20 phase clock signal CLK[0:19 of TMDS clock frequency] 102.Over-sampling device 201 receives TMDS data-signal 20, sampling clock is the 20 phase clock CLK[0:19 that double TMDS clock frequency] 102, within a TMDS clock cycle, over-sampling device is exported 40 parallel-by-bit data D[0:39] 30, namely TMDS data are sampled four times.
DE detector 301 receives 40 parallel-by-bit data D[0:39 of sampler output] 30, DE detector output de_detected signal 50, de_detected signal is that high level represents to detect effective DE signal.Phase-detection logic 302 receives 40 parallel-by-bit data D[0:39 of sampler output] 30 and the de_detected signal 50 of DE detector output, at de_detected signal 50 40 parallel-by-bit data D[0:39 to current input during for high level] 30 carry out phase-detection, phase-detection logic output error data number E0 ~ E3 60 and correct data number O0 ~ O3 70, E0 represents the corresponding misdata number of 0 phase place, E1 represents the corresponding misdata number of 1 phase place, E2 represents the corresponding misdata number of 2 phase place, E3 represents the corresponding misdata number of 3 phase place, O0 represents the corresponding correct data number of 0 phase place, O1 represents the corresponding correct data number of 1 phase place, O2 represents the corresponding correct data number of 2 phase place, O3 represents the corresponding correct data number of 3 phase place.Phase-detection preliminary treatment 303 receiving phases detect misdata number E0 ~ E3 60 and the correct data number O0 ~ O3 70 that logic 302 is exported, output minimal error data number and the corresponding phase signal f_big_small 80 of maximum correct data number.Phase control FSM 305 receiving phases detect the phase signal f_big_small 80 that preliminary treatment 303 is exported, and output phase is selected control signal sel_phase 90.Output data selection 304 receives the 40 parallel-by-bit data D[0:39 that over-sampling device 201 is exported] 30 and Selecting phasing control signal sel_phase 90, the data-signal dataout 40 that output recovers.
As shown in Figure 2, Fig. 2 is digital video interface data recovery circuit TMDS data sampling sequential chart of the present invention.Charge pump phase lock loop 101 outputs double 20 phase clock signal CLK[0:19 of TMDS clock frequency] 102, phase place is as Figure 102-0,102-1,102-2 ... shown in 102-19.Over-sampling device 201 is sampled to the TMDS data of input, and within a TMDS clock cycle, over-sampling device is exported 40 parallel-by-bit data D[0:39] 30, namely TMDS data are sampled four times.As Figure 20-0,20-1,20-2 ... shown in 20-39.
As shown in Figure 3, Fig. 3 is the schematic diagram of DE detector of the present invention.The parallel data D[0:39 that over-sampling device 201 is exported] 30 be input to 40 bit registers and be output as D1[0:39] 31, signal map module 310-0 is by 40 parallel-by-bit data D[0:39] 30 be mapped to the data output A0 of four phase places, A1, A2, A3, signal map module 310-1 is by 40 parallel-by-bit data D1[0:39] 31 be mapped to the data output B0 of four phase places, B1, B2, B3, A0 and B0 are 0 phase mapping signals, B0 is the one-period time delay output of A0, A1 and B1 are 1 phase mapping signals, B1 is the one-period time delay output of A1, A2 and B2 are 2 phase mapping signals, B2 is the one-period time delay output of A2, A3 and B3 are 3 phase mapping signals, B3 is the one-period time delay output of A3.Mapping relations as shown in Figure 4,40 parallel-by-bit data D[0:39] be mapped to the output of four phase data A0, A1, A2, A3.Two same phases and have mapping signal A0B0, A1B1, A2B2, the A3B3 of one-period time delay to be input to four DE detecting unit 320-0,320-1,320-2,320-3, DE detecting unit output DE detection signal match0, match1, match2, match3, match be four phase places DE detecting unit output signal or logic, namely match=match0 or match1 or match2 or match3.Match signal is sent into serial shift register, shift register output carries out logic OR operation, this logic OR operation filters out the little burr output match_filt signal of match signal, match_filt signal is sent into rising edge testing circuit output de_detected signal, and de_detected signal is that high level represents to detect effective DE signal.
As shown in Figure 5, inside comprises ten parallel DE detection sub-unit 321-0,321-1,321-2 to DE detecting unit 320 ... 321-9, the signal that ten detection sub-unit 321 are exported carries out logic OR operation output detection signal match0.As shown in Figure 6, inside comprises mapping block 325 and detection sub-unit logical circuit to DE detection sub-unit 321.Detection sub-unit logical circuit is to detect whether nine input data are 110101010 or 001010101, and namely front two data are identical, and rear eight bit data successively logic is contrary, and the data transaction number of times of rear eight bit data is seven.A feature of TMDS coding is within a clock TMDS cycle, when DE signal is low level, ten Bits Serial TMDS data-signal conversion times of TMDS coding output are more than or equal to seven, and when DE signal is high level, ten Bits Serial TMDS data-signal conversion times of TMDS coding output are less than or equal to five.When detecting that nine input data of input are 110101010 or 001010101, effective DE signal detected.Fig. 7 is the signal map relation of mapping block 325, the phase difference of the input signal of DE detection sub-unit 0 ~ 9 was 1/10 TMDS clock cycle, QB signal is the time delayed signal in a TMDS cycle of QA signal, and namely B signal is the time delayed signal in a TMDS cycle of a-signal.
As shown in Figure 8, Fig. 8 is phase-detection logical construction schematic diagram of the present invention.The parallel data D[0:39 that over-sampling device 201 is exported] 30 be input to 40 bit registers and be output as D1[0:39] 32, signal map module 331 input is D[0:39] 30 and D1[0:39] 32 signals, output is 40 parallel-by-bit data B0[0:39 of four phase places], B1[0:39], B2[0:39], B3[0:39].Fig. 9 is the signal map graph of a relation of signal map module 331, and B0 is 0 phase data, and B1 is 1 phase data, and B2 is 2 phase data, and B3 is 3 phase data.Phase-detection subelement 330-0,330-1,330-2,330-3 carry out phase-detection to 40 parallel-by-bit data B0, B1, B2, the B3 of four phase places respectively, error in data number E0 and the data correct number O0 of phase-detection subelement 330-0 output B0 data, error in data number E1 and the data correct number O1 of phase-detection subelement 330-1 output B1 data, error in data number E2 and the data correct number O2 of phase-detection subelement 330-2 output B2 data, error in data number E3 and the data correct number O3 of phase-detection subelement 330-3 output B3 data.
Phase-detection subelement 330 as shown in figure 10, comprises ten parallel detecting unit 340-0,340-1 ... 340-9.The input data of detecting unit 0 are B[0:3], the input data of detecting unit 1 are B[4:7], the input data of detecting unit 2 are B[8:11], the input data of detecting unit 3 are B[12:15], the input data of detecting unit 4 are B[16:19], the input data of detecting unit 5 are B[20:23], the input data of detecting unit 6 are B[24:27], the input data of detecting unit 7 are B[28:31], the input data of detecting unit 8 are B[32:35], the input data of detecting unit 9 are B[36:39].Ten detecting units are exported corresponding four figures according to phase-detection state, namely error in data state E[0] ~ E[9] and data correct status O[0] ~ O[9].
Detecting unit as shown in figure 11, four parallel datas of input are B[0:3], middle two signal B[1] and B[2] signal carries out XOR output error signal E, namely E=B[1] xor B[2], correct signal O is B[0] B[3] with or and B[1] B[2] and with or logical AND output, namely O=(not (B[1] xor B[2])) and (not (B[0] xor B[3])).Work as B[0:3] two of centres signal B[1] B[2] not phase time rub-out signal E output 1, the input data that comprise have [0,0,1,0], [0,0,1,1], [1,0,1,0], [1,0,1,1], [0,1,0,0], [0,1,0,1], [1,1,0,0], [1,1,0,1], as B[0] B[3] identical and B[1] B[2] correct signal O output 1 when identical, the input data that comprise have [0,0,0,0], [1,0,0,1], [0,1,1,0], [1,1,1,1].
As shown in figure 12, Figure 12 is invention phase-detection pre-processing structure schematic diagram.The pretreated input of phase-detection is data correct signal O0, O1, O2, O3 and data error signal E0, E1, E2, the E3 of four phase places.Data correct signal O0 and the data error signal E0 of phase place 0 input to phase error accumulator 350-0, the phase error accumulator 350-0 output correct accumulated value sum_O0 of data and error in data accumulated value sum_E0; Data correct signal O1 and the data error signal E1 of phase place 1 input to phase error accumulator 350-1, the phase error accumulator 350-1 output correct accumulated value sum_O1 of data and error in data accumulated value sum_E1; Data correct signal O2 and the data error signal E2 of phase place 2 input to phase error accumulator 350-2, the phase error accumulator 350-2 output correct accumulated value sum_O2 of data and error in data accumulated value sum_E2; Data correct signal O3 and the data error signal E3 of phase place 3 input to phase error accumulator 350-3, the phase error accumulator 350-3 output correct accumulated value sum_O3 of data and error in data accumulated value sum_E3.Error in data accumulated value sum_E0, sum_E1, sum_E2, sum_E3 send into phase error number minimum detector, and minimum detector is exported the marking signal f_small of four error in data accumulated values of current input.The correct accumulated value sum_O0 of data, sum_O1, sum_O2, sum_O3 send into phase place correct number maximum value detector, and maximum value detector is exported the marking signal f_big of four correct accumulated values of data of current input.Mistake accumulated value marking signal f_small and correct accumulated value marking signal f_big carry out logical AND, output minimal error and maximum accurate indication signal f_big_small.
As shown in figure 14, Figure 14 is digital video interface data recovery circuit phase control FSM of the present invention 305 schematic diagrames.Phase control FSM output phase selects signal sel_phase to have four phase states, respectively P_SEL0, P_SEL1, P_SEL2, P_SEL3, P_SEL0 selects 0 phase data output, P_SEL1 selects 1 phase data output, P_SEL2 selects 2 phase data outputs, and P_SEL3 selects 3 phase data outputs.SET0=1 when the minimal error of inputting and maximum accurate indication signal f_big_small=0001, represents 0 phase data error number minimum and data correct number maximum, Selecting phasing signal sel_phase=P_SEL0; SET1=1 when the minimal error of inputting and maximum accurate indication signal f_big_small=0010, represents 1 phase data error number minimum and data correct number maximum, Selecting phasing signal sel_phase=P_SEL1; SET2=1 when the minimal error of inputting and maximum accurate indication signal f_big_small=0100, represents 2 phase data error number minimums and data correct number maximum, Selecting phasing signal sel_phase=P_SEL2; SET3=1 when the minimal error of inputting and maximum accurate indication signal f_big_small=1000, represents 3 phase data error number minimums and data correct number maximum, Selecting phasing signal sel_phase=P_SEL3.When minimal error and the maximum accurate indication signal f_big_small of input comprise two 1 continuous signals as [0011], [0110], [1100], [1001], the error in data number that represents two continuous phase states is equal and minimum, data correct number equates and is maximum, now, can be according to the state of current Selecting phasing signal sel_phase, set UP signal or DOWN signal.When UP signal is 1, phase place redirect is P_SEL0-> P_SEL1-> P_SEL2-> P_SEL3.When DOWN signal is 1, phase place redirect is P_SEL3-> P_SEL2-> P_SEL1-> P_SEL0.The maximum correct number phase place of phase place when phase control FSM state transition is selected phase minimal error number.
As shown in figure 15, Figure 15 is that the present invention exports data selection structural representation.Data are input as the output signal D[0:39 of over-sampling device 201], selecting control signal is the output signal sel_phase 90 of phase control FSM 305, output data selection output signal is dataout 40.
Although the present invention in conjunction with the preferred embodiments mode is described, it will be appreciated by those skilled in the art that under the prerequisite of spirit and scope that does not deviate from this law, can be by using known equivalent way to change the present invention.Description related to the preferred embodiment is considered to be exemplary description rather than limits the scope of the invention above, and scope of the present invention is limited by the accompanying claims.
Claims (9)
1. digital video interface data recovery circuit, is characterized in that, this circuit comprises:
Charge pump phase lock loop (101), for receiving the input of TMDS clock, produce the 20 phase clock outputs that double TMDS clock frequency;
Over-sampling device (201), samples to the high speed serialization TMDS data-signal of input, and a TMDS data-signal is sampled four times, and within a clock TMDS cycle, sampler is exported 40 parallel-by-bit data;
Data recovery unit (300), according to 40 parallel-by-bit data of over-sampling device output, recovers original digital of digital video data;
Described data recovery unit (300) comprising:
DE detector (301), detects DE signal according to the conversion times of 40 bit data of over-sampling device (201) output;
Phase-detection logical block (302), when DE is low level, to 40 bit data of the sampler output phase-detection of dividing into groups, every four data form a phase-detection elementary cell, phase-detection elementary cell detects two kinds of data modes, is respectively correct data state or misdata state;
Phase-detection pretreatment unit (303), processes correct data state and the misdata state of the output of phase-detection logical block, exports four corresponding cumulative correct data numbers of possible Selecting phasing and misdata number;
Phase control state machine (305), processes the signal of phase-detection pretreatment unit output, selects misdata minimum number and the maximum phase place output of correct data number in four possible phase places;
Output data selection unit (304), according to the Selecting phasing of phase control state machine (305) output, the digital of digital video data that output recovers.
2. digital video interface data recovery circuit according to claim 1, is characterized in that, described DE detector (301) comprising:
The four roads DE detecting unit (320-0,320-1,320-1,320-3) that walks abreast, carries out DE detection to 40 parallel-by-bit data of input;
The output state that the parallel DE in four tunnels detects carries out logic OR operation, deburring operation, and rising edge detects operation.
3. digital video interface data recovery circuit according to claim 2, it is characterized in that: described DE detector (301) also comprises two signal map module (310-0, 310-1) and serial shift register, wherein signal map module (310-0) is mapped to 40 parallel-by-bit data D the data output signal A0 of four phase places, A1, A2, A3, signal map module (310-1) is by 40 parallel-by-bit data D1(31) be mapped to the data output signal B0 of four phase places, B1, B2, B3, A0 and B0 are 0 phase mapping signals, B0 is the one-period time delay output of A0, A1 and B1 are 1 phase mapping signals, B1 is the one-period time delay output of A1, A2 and B2 are 2 phase mapping signals, B2 is the one-period time delay output of A2, A3 and B3 are 3 phase mapping signals, B3 is the one-period time delay output of A3, two same phases and have the mapping signal A0B0 of one-period time delay, A1B1, A2B2, A3B3 is input to respectively four DE detecting unit (320-0, 320-1, 320-2, 320-3), four DE detecting units are exported four road DE detection signal match0, match1, match2, match3, signal match is that four described DE detecting units are exported four road DE detection signal match0, match1, match2, match3's or logic, signal match sends into serial shift register, shift register output carries out logic OR operation, this logic OR operates the matched signal match_filt after the little burr output filtering that filters out signal match, filtered matched signal match_filt sends into rising edge testing circuit output DE detection signal de_detected, DE detection signal de_detected is that high level represents to detect effective DE signal.
4. digital video interface data recovery circuit according to claim 2, it is characterized in that: the inside of each DE detecting unit (320-0,320-1,320-1,320-3) comprises ten parallel DE detection sub-unit (321-0,321-1,321-2,321-3,321-4,321-5,321-6,321-7,321-8,321-9), the signal of ten detection sub-unit (321) output carries out logic OR operation output detection signal match0; Described DE detection sub-unit (321) inside comprises mapping block (325) and detection sub-unit logical circuit.
5. digital video interface data recovery circuit according to claim 1, is characterized in that: described phase-detection logical block (302) comprising:
The parallel phase-detection subelement (330-0,330-1,330-2,330-3,330-4) in four tunnels carries out phase-detection to 40 parallel-by-bit data of input;
Phase-detection subelement carries out phase-detection to 40 parallel-by-bit data of input, each phase-detection subelement inside comprises ten parallel detecting units (340-0,340-1,340-2,340-3,340-4,340-5,340-6,340-7,340-8,340-9), each detecting unit is input as four figures certificate, is output as error flag and accurate indication.
6. digital video interface data recovery circuit according to claim 5, is characterized in that, each parallel detecting unit comprises:
The first XOR gate, produces signal a after the zero-bit data in parallel input four figures certificate and the 3rd bit data;
The second XOR gate, produces signal b after the first bit data in parallel input four figures certificate and second data, and this signal is misdata signal E;
The first not gate, signal a produces signal c;
The second not gate, signal b produces signal d;
With door, signal c and signal d produce data correct signal O.
7. digital video interface data recovery circuit according to claim 1, is characterized in that, described phase-detection pretreatment unit (303) comprising:
Misdata number and the correct data number of the parallel phase error accumulator (350-0,350-1,350-2,350-3) in four tunnels to four outs of phase adds up;
The misdata number of four outs of phase is sent into minimum detector, produces minimum value marking signal;
The correct data number of four outs of phase is sent into maximum value detector, produces maximum marking signal;
Minimum value marking signal and maximum marking signal carry out logical AND operation, produce maximum and minimum value marking signal.
8. digital video interface data recovery circuit according to claim 7, is characterized in that, the judgment criterion of described phase control state machine (305) is:
According to maximum and minimum value marking signal, carry out Selecting phasing, the phase place that makes to select has the minimum and correct data number maximum of misdata number, and the priority of misdata number minimum is higher than correct data number maximum.
9. the data reconstruction method that utilizes any digital video interface data recovery circuit as described in claim 1-8, comprises the following steps:
Step 1, DE detects, and according to the conversion times of 40 bit data of sampler output, detects DE signal;
Step 2, phase-detection logic, when DE is low level, to 40 bit data of the sampler output phase-detection of dividing into groups, every four data form a phase-detection elementary cell, and phase-detection elementary cell detects two kinds of data modes, is respectively correct data state or misdata state;
Step 3, phase-detection preliminary treatment, processes correct data state or the misdata state of the output of phase-detection logic, exports four corresponding cumulative correct data numbers of possible Selecting phasing and misdata number;
Step 4, phase control state machine FSM processes the signal of phase-detection preliminary treatment output, selects misdata minimum number and the maximum phase place output of correct data number in four possible phase places;
Step 5, output data selection, according to the Selecting phasing of phase control state machine output, the digital of digital video data that output recovers.
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| KR102577232B1 (en) * | 2016-11-28 | 2023-09-11 | 삼성전자주식회사 | Hybrid clock data recovery circuit and receiver |
| CN112511165B (en) * | 2020-11-25 | 2023-11-28 | 中国科学技术大学 | Multi-target weak signal detection method and device based on single-bit sampling |
| CN114339107B (en) * | 2022-03-14 | 2022-06-24 | 武汉精立电子技术有限公司 | Method and device for reducing VBO signal rate and test equipment |
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