CN102547177A - Picture amplifying control device applied to display - Google Patents
Picture amplifying control device applied to display Download PDFInfo
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- CN102547177A CN102547177A CN2011103292987A CN201110329298A CN102547177A CN 102547177 A CN102547177 A CN 102547177A CN 2011103292987 A CN2011103292987 A CN 2011103292987A CN 201110329298 A CN201110329298 A CN 201110329298A CN 102547177 A CN102547177 A CN 102547177A
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Abstract
The invention discloses a picture amplifying control device applied to a display, comprising a scale controller, wherein the scale controller can lead an original image signal to generate an output image signal by utilizing a linear interpolation method. When the linear interpolation method is carried out, a forced locking mechanism and a local locking mechanism are used for deciding an actual position of an interpolation pixel so as to lead the position error of the pixel position to be smaller. Therefore, the difference between the calculated pixel value and an ideal value is smaller and the image quality in the output image signal is better.
Description
Present patent application be that on 08 31st, 2010, application number are 201010269839.7 the applying date, exercise question divides an application for the patent application of " applying to the picture amplification control method and the device of display ".
Technical field
The invention relates to a kind of control device that applies to display, and particularly relevant for a kind of picture amplification control device that applies to display.
Background technology
In general, comprise a scale controller (scaler) in the display, it can change exploration on display resolution ratio in response to the requirement in the user.For instance, suppose that it is 640 * 480 VGA picture signal that display receives resolution, the VGA picture signal after scale controller can change resolution (for example 1024 * 768) and output according to user's demand and changes.That is to say that when if user's desire is heightened the resolution of picture, at this moment, scale controller just must carry out picture and amplify (Scaling up) control action.Certainly the picture signal after changing also can be the picture signal of other specification, for example HDTV picture signal.
Please with reference to Fig. 1, its illustrate is carried out the sketch map that picture amplifies for known scale controller.Scale controller 100 comprise a line buffer control unit (line buffer controller) 110, line buffer (line buffer) 120, vertical linearity arithmetic element (Vertical linear operating unit) 130, horizontal linearity arithmetic element (Horizontal linear operating unit) 140, with time generator (timing generator) 150.
For instance; Line buffer control unit 110 in the scale controller 100, line buffer 120, vertical linearity arithmetic element 130, with horizontal linearity arithmetic element 140, convert original image signal (original image signal) into output image signal (output image signal).Wherein, original image signal is different with the resolution of output image signal, is the output image signal that 640 * 480 original image signal is converted into resolution 1024 * 768 with resolution for example.
Moreover; The time signal that time generator 150 receives in the original image signal; For example original vertical synchronizing signal (original V-sync signal), original level synchronizing signal (original H-sync signal), original pixels clock (original pixel clock); And be converted into the time signal in the output image signal according to this, for example export vertical synchronizing signal (output V-sync signal), output horizontal-drive signal (output H-sync signal), output pixel clock (output pixel clock).Below introduce scale controller 100 in detail and carry out the flow process that picture amplifies.
When original image signal was sent to scale controller 100,480 original line data (original line data) that line buffer control unit 110 can receive in the original image signal to be comprised in regular turn also were temporary in the line buffer 120.Wherein, each original line data comprises 640 three color pixel values (3-color value).And three color pixel values be red pixel value (R pixel value), green pixel values (G pixel value), with blue pixel value (B pixel value).If each color pixel value representes that with 1 ancestral (1 byte) then the data volume of the original line data of each is 1920 (640 * 3) bytes (bytes).
In general, the size in the line buffer 120 (size) is the capacity of three original line data, that is, 5760 (1920 * 3) bytes (bytes).That is to say that comprise three line buffer cells 122,124,126 in the line buffer 120, each line buffer cell can store original line data.
Therefore; In order to use line buffer 120 effectively; When the first line buffer cell 122 and the second line buffer cell 124 have finished receiving the process that the first stroke original line data and second original line data and three-way buffer cell 126 are receiving the 3rd original line data, vertical linearity arithmetic element 130 just must be utilized linear interpolation (linear interpolation) and go out at least one interpolated line data (interpolated line data) and be passed to horizontal linearity arithmetic element 140 according to the first stroke original line data and second original line data computation of line buffer control unit 110 outputs.
After three-way buffer cell 126 finishes receiving the 3rd original line data; The first line buffer cell 122 is receiving the process of the 4th original line data, and vertical linearity arithmetic element 130 is utilized linear interpolation and gone out at least one interpolated line data and be passed to horizontal linearity arithmetic element 140 according to second original line data and the 3rd original line data computation of line buffer control unit 110 output.
In like manner; After the first line buffer cell 122 finishes receiving the 4th original line data; The single 124 yuan of processes that receiving the 5th original line data of second line buffering, vertical linearity arithmetic element 130 are utilized linear interpolation and are gone out at least one interpolated line data and be passed to horizontal linearity arithmetic element 140 according to the 3rd original line data and the 4th original line data computation of line buffer control unit 110 outputs.
Can know by above description; When a line buffer cell in the line buffer 120 was receiving original line data, two original line data in other two line buffer cells promptly were sent to vertical linearity arithmetic element 130 and calculate the interpolated line data by line buffer control unit 110.Above-mentioned step must continue to proceed to 480 original line data and all convert into till 768 interpolated line data, and interpolated image signal (interpolated image signal) promptly comprises 768 interpolated line data.
Moreover; After horizontal linearity arithmetic element 140 receives the interpolated line data that vertical linearity arithmetic element 130 exports in regular turn; Promptly utilize linear interpolation that 768 interpolated line data transaction are become 768 output line numbers according to (output line data) once more, and output image signal promptly comprise 768 output line number certificates.
That is to say that 480 original line data transaction that vertical linearity arithmetic element 130 can will receive become 768 interpolated line data, make that the resolution of interpolated image signal is 640 * 768.Wherein, the data volume of each interpolated line data is 1920 (640 * 3) bytes (bytes).Moreover horizontal linearity arithmetic element 140 can be converted into the data volume of each interpolated line data the output line number certificate of 3072 (1024 * 3) bytes (bytes) by 1920 (640 * 3) bytes (bytes).Therefore, 768 output line number is 1024 * 768 according to its resolution of output image signal of being formed.
Please with reference to Fig. 2 A and Fig. 2 B, its illustrate produces the sketch map of interpolated line data into vertical linearity arithmetic element under the ideal state.Because vertical linearity arithmetic element 130 can be 768 interpolated line data with 480 original line data transaction.Therefore, the scale factor of vertical direction (ratio factor) is 5/8 (480/768).That is to say that suppose that two distances between the continuous original line data are 1 unit length, and the distance of changing between back two interpolated line data is (5/8) unit length, then the ratio between second length and first length is the vertical scale factor (5/8).And vertical linearity arithmetic element 130 is promptly carried out linear interpolation according to the scale factor of this vertical direction.Distance between above-mentioned two continuous original line data is 1 unit length, and the distance that also can be interpreted as between the same pixel in continuous two original line data (first pixels in for example continuous two original line data) is 1 unit length.
Please refer to Fig. 2 A, the position concerned sketch map when its illustrate was carried out the linear interpolation of vertical direction for the vertical linearity arithmetic element.Can know that by Fig. 2 A 5 unit lengths equal 8 (5/8) unit lengths.That is to say that per 5 original line data need be converted into 8 interpolated line data.In like manner, other follow-up original line data are all identical with the position of interpolated line data relation, repeat no more.
Moreover; Please refer to the 2nd figure B; Suppose that first color pixel values in the first stroke original line data (L1) (for example red pixel value) is A1, A2, A3～A640 in regular turn, first color pixel values is B1, B2, B3～B640 in regular turn in second original line data (L2), because the first stroke interpolated line data are positioned at the position of (5/8) unit length; It is positioned between the first stroke original line data (L1) and second the original line data (L2); So utilize linear interpolation can obtain that all first color pixel values do in the first stroke interpolated line data (11), an=(3/8) An+ (5/8) Bn, wherein n is 1～640 Any Digit.That is to say that the first color pixel value is to obtain according to first color pixel values of the first stroke original line data (L1) with the middle opposite position of second original line data (L2) in the first stroke interpolated line data (11).And the second original line data (L2) are nearer apart from the first stroke interpolated line data (11), have higher weight (weighting) (5/8); The first original line data (L1) are far away apart from the first stroke interpolated line data (11), have lower weight (3/8).Certainly, other color pixel values in the first stroke interpolated line data (11) (for example green pixel values and blue pixel value) also is to calculate with identical method, repeats no more.
In like manner; Suppose that first color pixel values is C1, C2, C3～C640 in regular turn in the 3rd the original line data (L3); Because second interpolated line data are positioned at the position of (10/8) unit length, it is positioned between second original line data (L2) and the 3rd the original line data (L3), so utilize linear interpolation can obtain that first color pixel values does in second interpolated line data (l2); Bn=(6/8) Bn+ (2/8) Cn, wherein n is 1～640 Any Digit; And be positioned at the position of (15/8) unit length owing to the 3rd interpolated line data; It is positioned between second original line data (L2) and the 3rd the original line data (L3); So utilize linear interpolation can obtain that first color pixel values does in the 3rd the interpolated line data (l3); Cn=(1/8) Bn+ (7/8) Cn, wherein n is 1～640 Any Digit.That is to say that the first color pixel value is to obtain according to first color pixel values of second original line data (L2) with the middle opposite position of the 3rd original line data (L3) in second interpolated line data (l2) and the 3rd the interpolated line data (l3).
In like manner, suppose that first color pixel values is D1, D2, D3～D640 in regular turn in the 4th the original line data (L4); First color pixel values is E1, E2, E 3～E640 in regular turn in the 5th the original line data (L5); First color pixel values is F1, F2, F3～F640 in regular turn in the 6th the original line data (L6).Therefore, utilize linear interpolation can obtain that first color pixel values is dn=(4/8) Cn+ (4/8) Dn in the 4th the interpolated line data (l4); First color pixel values is en=(7/8) Dn+ (1/8) En in the 5th the interpolated line data (l5); First color pixel values is fn=(2/8) Dn+ (6/8) En in the 6th the interpolated line data (l6); First color pixel values is gn=(5/8) En+ (3/8) Fn in the 7th the interpolated line data (l7); And the 8th interpolated line data (l8) are same as the 6th original line data (L6).And utilize identical method can obtain all 768 interpolated line data.
That is to say that the vertical linearity arithmetic element is the scale factor that utilizes vertical direction when carrying out the linear interpolation of vertical direction, obtains position and two pairing weights of original line data of interpolated line data, and and then calculate the interpolated line data.
Please with reference to Fig. 3 A and Fig. 3 B, its illustrate produces the sketch map of output line number certificate into horizontal linearity arithmetic element under the ideal state.Because horizontal linearity arithmetic element 140 can be 768 output line number certificates with 768 interpolated line data transaction; Wherein, The data volume of each interpolated line data is 1920 (640 * 3) bytes (bytes), and the data volume of each output line number certificate is positions, 3072 (1024 * 3).Therefore, the scale factor of horizontal direction (ratio factor) is 5/8 (640/1024).Moreover first color pixel values in the first stroke interpolated line data (l1) (for example red pixel value) is a1, a2, a3～a 640 in regular turn; And the first stroke output line number after the conversion is aa1, aa2, aa3～aa640 according to first color pixel values in (ll1) in regular turn.
Because the distance in the first stroke interpolated line data (l1) between wantonly two first color pixel values is 1 unit length, and conversion back the first stroke output line number is one (5/8) unit length according to the distance between wantonly two first color pixel values in (ll1).And horizontal linearity arithmetic element 140 is promptly carried out linear interpolation according to the scale factor of this horizontal direction.
Please refer to Fig. 3 A, distance relation sketch map when its illustrate is carried out the linear interpolation of horizontal direction for the horizontal linearity arithmetic element.Can know that by Fig. 3 A 5 unit lengths equal 8 (5/8) unit lengths.That is to say that per 5 first color pixel values need be converted into 8 first color pixel values of the first stroke output line number according to (ll1) in the first stroke interpolated line data (l1).In like manner, ((aa9～aa1024) relation is identical, repeats no more according to the distance between first color pixel values of (ll1) with the first stroke output line number for the distance between the a7～a640) for first color pixel values in follow-up the first stroke interpolated line data (l1).
Moreover; Please refer to the 3rd figure B; Suppose that first color pixel values in the first interpolated line data (l1) (for example red pixel value) is a1, a2, a3～a6 in regular turn; Because the first stroke output line number is positioned at (5/8) unit length according to first first color pixel values (aa1) in (ll1); It is positioned between first first color pixel values (a1) and second first color pixel values (a2) of the first stroke interpolated line data (l1), so utilize linear interpolation can obtain the first stroke output line number according to first first color pixel values aa1=(3/8) a1+ (5/8) a2 in (ll1).That is to say that the first stroke output line number is according to first first color pixel value (aa1) in (ll1), is to utilize that first first color pixel value (a1) obtains with second first color pixel values (a2) in the first stroke interpolated line data (l1).And the first stroke output line number is far away apart from first first color pixel value (a1) in the first stroke interpolated line data (l1) according to first first color pixel value (aa1) in (ll1), has lower weight (3/8); The first stroke output line number is nearer apart from second first color pixel value (a2) in the first stroke interpolated line data (l1) according to first first color pixel value (aa1) in (ll1), has higher weight (5/8).
In like manner, the first stroke output line number is according to second first color pixel values aa2=(6/8) a2+ (2/8) a3 in (ll1); The first stroke output line number is according to the 3rd first color pixel values aa3=(1/8) a2+ (7/8) a3 in (ll1); The first stroke output line number is according to the 4th first color pixel values aa4=(4/8) a3+ (4/8) a4 in (ll1); The first stroke output line number is according to the 5th first color pixel values aa5=(7/8) a4+ (1/8) a5 in (ll1); The first stroke output line number is according to the 6th first color pixel values aa6=(2/8) a4+ (6/8) a5 in (ll1); The first stroke output line number is according to the 7th first color pixel values aa7=(5/8) a5+ (3/8) a6 in (ll1); The first stroke output line number is according to the 8th first color pixel values aa8=a6 in (ll1).
Certainly, other first color pixel values in the first stroke interpolated line data (a7～a640) be converted into output line number according in other first color pixel values (method of aa9～aa1024) is also same as described above.In like manner, the first stroke output line number also is to calculate with identical method according to other color pixel values (for example green pixel values and blue pixel value) in (ll1), repeats no more.
From the above; During the linear interpolation of horizontal linearity arithmetic element executive level direction is the scale factor that utilizes horizontal direction; Obtain output line number according in the position of each pixel value, and then obtain in the interpolated line data the corresponding weight of two pixel values and calculate the pixel value of output line number certificate.And utilize identical method promptly can obtain all 1024 first color pixel values.
As everyone knows, all be to utilize digital circuit (digital circuit) to realize in vertical linearity arithmetic element 130 and the horizontal linearity arithmetic element 140.And in the above-mentioned picture amplification control method; The scale factor of its vertical direction and the scale factor of horizontal direction all can be digital circuit and accept (acceptable); It is that the denominator numerical value in the scale factor of scale factor and horizontal direction of vertical direction is 8 (be 2 power power); Ideal position and the output line number that therefore can correctly obtain the interpolated line data according in the ideal position of each pixel value, and utilize linear interpolation to calculate correct pixel value.Yet when scale controller 100 carried out the picture amplification, when the scale factor of its vertical direction or the scale factor of horizontal direction can't be accepted (unacceptable) by digital circuit, the pixel value that linear interpolation is calculated is error to some extent.
For instance; It is 640 * 480 original image signal and when to change into resolution be 1440 * 1050 output image signal that display will receive resolution; The correct proportions factor of vertical direction (exact ratio factor) is 16/35 (480/1050); The correct proportions factor of horizontal direction is 4/9 (640/1440), and this two scale factor all can't be accepted by digital circuit.Because vertical direction is identical with the linear interpolation principle of horizontal direction, therefore, following description is that example is explained with the linear interpolation of vertical direction all.
Suppose that the distance between the original line data is 1 unit length (U), the ideal position of every interpolated line data should come to increase progressively in regular turn with (16/35) unit length (U).Yet; Suppose that vertical linearity arithmetic element 130 is to handle with 10 (bit); Then vertical linearity arithmetic element 130 only can with near 16/35 468/1024 be used as vertical direction approach scale factor (approached ratio factor); And the physical location of every interpolated line data is to increase progressively in regular turn with (468/1024) unit length (U), and carries out the computing of linear interpolation according to this.So the first stroke interpolated line data can produce the site error of Δ, Δ=(16/35) U-(468/1024) U=0.000111607U wherein.
Because the position of the first stroke interpolated line data can produce the site error (E) of Δ, error is caused the error of all pixel numbers in the first stroke interpolated line data; In like manner, the position of n interpolated line data can produce the site error (E) of (n * Δ), and will cause the error of all pixel numbers in n the interpolated line data bigger.Certainly, the n value is big more, and the site error of n interpolated line data (E) is big more, and the error of all pixel numbers is also big more in n interpolated line data.
Because the correct proportions factor of vertical direction can know that for (16/35) 16 unit lengths (U) length equals 35 (16/35) unit lengths (U).In order not allow the unconfined expansion of site error (E); Known vertical linearity arithmetic element 130 adopts a kind of overall locking mechanism (global lock); Control position error (E) is arrived (34 * Δ) at most, and pressure is set, and all pixel values equal the 16th all pixel value in the original line data in the 35th the interpolated line data.
Please, when carrying out linear interpolation for known vertical linearity arithmetic element, its illustrate utilizes the flow chart of overall locking mechanism with reference to Fig. 4 A.Step S410 is to be used for setting initial value.Wherein, n=1, unit length=U, X=0, E=0, wherein n is that natural number, X are that physical location, the E of n interpolated line data is site error.
In step S420, vertical linearity arithmetic element 130 obtains the correct proportions factor (B/A) of vertical direction according to the resolution of original image signal and output image signal, and vertical direction approach scale factor (C/D), and can calculate margin of error Δ.According to above-mentioned example, the correct proportions factor (B/A)=(16/35), wherein, A and B are the computing (reduction of a fraction) that can't reduce again of natural number and molecule and denominator.Moreover because vertical linearity arithmetic element 130 handles with 10 (bit), then vertical direction approaches scale factor (C/D)=(468/1024) and margin of error Δ=(16/35) U-(468/1024) U=0.000111607U.
Like step S430, judge at first whether n is the integral multiple of A (=35), if set up, then the 35th interpolated line data, the 70th interpolated line data, the 105th interpolated line data are being handled in representative ....At this moment, like step S440, the physical location (X) that must force to set these interpolated line data equals the integral multiple (n/A) of B (B=16) unit length (U), and forces to set the site error (E)=0 of this moment, and step S440 is carrying out overall locking mechanism.Otherwise, if when being false, like step S450, the physical location of n interpolated line data (X) each distance that increases [(C/D) U] that can continue to add up, and the site error between physical location and the ideal position (E) each Δ that increases that also can continue to add up.
Like step S460, carry out linear interpolation with the physical location (X) of above-mentioned n interpolated line data, and obtain all pixel values of interpolated line data.
Like step S470, judge whether that all interpolated line data produce all, as not, then n is added 1 and get into step S440 like step S480; In this way, then finish all flow processs like step S490.
With the above-mentioned correct proportions factor (B/A)=(16/35) is example; The practice of the overall locking mechanism of known vertical linearity arithmetic element 130; To cause the 34th interpolated line data to have the site error (E) of maximum (34 * Δ), and the 35th interpolated line data have 0 site error (E).Afterwards, the 36th interpolated line data have the site error (E) of Δ, and continue accumulation site error (E) once more.
Please, when carrying out linear interpolation for known 10 vertical linearity arithmetic elements, its illustrate utilizes the site error sketch map of overall locking mechanism with reference to Fig. 4 B.Clearly, because the correct proportions factor of vertical direction is 16/35, so the site error (E) when known vertical linearity arithmetic element can force to set the 35th interpolated line data is 0; And maximum site error (E) can be accumulate to the 34th interpolated line data (34 * Δ).In like manner, the site error (E) of the 69th interpolated line data is (34 * Δ); And the site error (E) during the 70th line data is 0.And be accumulated to the 768th interpolated line data with identical rule.
In like manner, if the correct proportions factor of horizontal direction can't be accepted by horizontal linearity arithmetic element 140, then horizontal linearity arithmetic element 140 must produce the scale factor that approaches of horizontal direction.Therefore, with producing site error between physical location that causes each pixel in the output line number certificate and the ideal position.And when utilizing overall locking mechanism, the considerable site error of meeting accumulation too.
Because site error is big more, with making that pixel value and ideal value gap that linear interpolation is calculated are big more, causes the picture quality in the output image signal not good, and can't amplify original image accurately.
Moreover; Can know that by Fig. 2 A known line buffer control unit 110 must be earlier be temporary in the first stroke original line data and second original line data and just can exports vertical linearity arithmetic element 130 to after the line buffer 120 and calculate the first stroke interpolated line data that are positioned at (5/8) unit length.So will delay vertical linearity arithmetic element 130 and calculate the time point of the first stroke interpolated line data.And, the situation generation that the pixel value in the interpolated line data can't be finished dealing with in real time might take place.
Summary of the invention
The object of the invention is exactly to be to provide a kind of picture amplification control method and device that applies to display.This display includes a scale controller; It can utilize linear interpolation to produce output image signal original image signal; And when carrying out linear interpolation, except having used positive lock mechanism, and increase the physical location that local locks with respect mechanism (local lock) decides interpolated pixel, make that the site error of location of pixels is less; And pixel value that calculates and ideal value gap are less, and the picture quality in the output image signal is preferable.
The present invention proposes a kind of picture amplification control method that applies to display; Be converted into an interpolated image signal of second resolution earlier in order to a original image signal with one first resolution; Be an output image signal of one the 3rd resolution again with this interpolated image conversion of signals; The distance that comprises the following steps: to set between two contiguous pixels of a first direction in this original image signal is a unit length, and this unit length is U; Set n and equal 1, X equals 0, and E equals 0, and wherein n is that natural number, X are that a physical location, the E of a n data is a site error; Correct proportions factor according to this first resolution and this first direction of the 3rd resolution calculating is approached scale factor (C/D) for one of (B/A) and this first direction; And calculate this correct proportions factor according to this and this approaches a margin of error of scale factor; This margin of error is a Δ; Wherein, A and B are natural number and should (B/A) can't carry out a reduction of a fraction computing again; (a) when n is not equal to A, make X increase (C/D) U, and make E increase Δ,, n carries out an overall locking mechanism when equaling A; (b) as E during greater than L_min, X is moved L_min, and make E reduce L_min, wherein L_min one can distinguish length; (c) carry out a linear interpolation according to this original image signal or this interpolated image signal and X, calculate at least one pixel value of these n data; And (d) n=n+1, and get into should (a) step.
The present invention proposes a kind of picture amplification control device that applies to display, comprising: a line buffer control unit receives an original image signal of one first resolution, and comprises many original line data in this original image signal; One line buffer is electrically connected to this line buffer control unit, temporary those original line data; One vertical linearity arithmetic element; Be electrically connected to this line buffer control unit; Indicate this line buffer control unit to read continuous two the original line data in those original line data in this line buffer; And according to an overall locking mechanism and the machine-processed interpolated image signal that produces one second resolution of a local locks with respect, and comprise many interpolated line data in this interpolated image signal; And; One horizontal linearity arithmetic element; Be electrically connected to this vertical linearity arithmetic element; Receive those interpolated line data in this interpolated image signal in regular turn, and produce an output image signal of one the 3rd resolution, and comprise many output line number certificates in this output image signal according to this overall locking mechanism and this local locks with respect mechanism.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 illustrate is carried out the sketch map that picture amplifies for known scale controller.
Fig. 2 A and Fig. 2 B, its illustrate produces the sketch map of interpolated line data into vertical linearity arithmetic element under the ideal state.
Fig. 3 A and Fig. 3 B illustrate produce the sketch map of output line number certificate into horizontal linearity arithmetic element under the ideal state.
Fig. 4 A utilizes the flow chart of overall locking mechanism when its illustrate is carried out linear interpolation for known vertical linearity arithmetic element.
Fig. 4 B utilizes the site error sketch map of overall locking mechanism when its illustrate is carried out linear interpolation for known 10 vertical linearity arithmetic elements.
When carrying out linear interpolation for vertical linearity arithmetic element of the present invention, Fig. 5 A illustrate utilizes the flow chart of overall locking mechanism and local locks with respect mechanism.
When carrying out linear interpolation for 10 vertical linearity arithmetic elements of the present invention, Fig. 5 B illustrate utilizes the site error sketch map of overall locking mechanism and local locks with respect mechanism.
Fig. 6 illustrate is the relation of the running between line buffer control unit of the present invention and the vertical linearity arithmetic element.
[main element label declaration]
100: scale controller
110: the line buffer control unit
120: line buffer
122: the first line buffer cells
124: the second line buffer cells
126: the three-way buffer cells
130: the vertical linearity arithmetic element
140: the vertical linearity arithmetic element
150: time generator
Embodiment
Vertical linearity arithmetic element and horizontal linearity arithmetic element with 10 (bit) are example; It is 640 * 480 original image signal and when to change into resolution be 1440 * 1050 output image signal that display receives resolution; The correct proportions factor of vertical direction is 16/35 (480/1050); The correct proportions factor of horizontal direction is 4/9 (640/1440); And this two scale factor all can't be accepted by the vertical linearity arithmetic element of digital circuit and horizontal linearity arithmetic element; Therefore can produce site error between the physical location of every interpolated line data and the ideal position, and output line number according in also can produce site error between physical location and the ideal position of every pixel value.Wherein, above-mentioned correct proportions factor 1 6/35 and 4/9, molecule and the denominator computing (reduction of a fraction) that can't reduce again.
Linear interpolation with vertical direction is an example, supposes that the distance between the original line data is 1 unit length (U), and the ideal position between every interpolated line data should increase progressively with (16/35) unit length (U).Yet the vertical linearity arithmetic element only can be with near 16/35 468/1024 scale factor that approaches as vertical direction.Therefore, the correct proportions factor and approach the difference that has Δ between the scale factor, wherein Δ=(16/35) U-(468/1024) U=0.000111607U.Wherein, the distance between above-mentioned two continuous original line data is 1 unit length, and the distance that also can be interpreted as between the same pixel in continuous two original line data (first pixels in for example continuous two original line data) is 1 unit length.
Therefore, the overall locking mechanism of known utilization can produce maximum site error (E) (=34 * Δ) in the position of the 34th interpolated line data.Afterwards, the site error (E) of the 35th interpolated line data can be forced returns 0, and begins accumulation by Δ once more in the site error (E) of the 36th interpolated line data.
According to embodiments of the invention, because 10 vertical linearity arithmetic element, (minimum distinguishable length L_min) is (U/1024=0.0009765625U) unit length to its I difference length.Therefore, the present invention more proposes local locks with respect mechanism (local lock) under overall locking mechanism framework, the site error (E) that its meeting persistent surveillance vertical linearity arithmetic element is accumulated.When site error (E) accumulation surpasses this I difference length (L_min), then recomputate the physical location of interpolated line data, and carry out linear interpolation with the physical location of the interpolated line data after the corrigendum.
Please, when carrying out linear interpolation for vertical linearity arithmetic element of the present invention, its illustrate utilizes the flow chart of overall locking mechanism and local locks with respect mechanism with reference to Fig. 5 A.Wherein, step S552 and step S554 are the local locks with respect mechanism flow process that the present invention increases newly.And carry out once can carrying out local locks with respect mechanism repeatedly before the overall locking mechanism.
Step S510 is to be used for setting initial value.Wherein, n=1, unit length=U, X=0, E=0, wherein n is that natural number, X are that physical location, the E of n interpolated line data is site error.
In step S520, the vertical linearity arithmetic element obtains the correct proportions factor (B/A) of vertical direction according to the resolution of original image signal and output image signal, and vertical direction approach scale factor (C/D), and calculate margin of error Δ.According to above-mentioned example, the correct proportions factor (B/A)=(16/35), wherein, A and B are the computing (reduction of a fraction) that can't reduce again of natural number and molecule and denominator.Moreover because vertical linearity arithmetic element 130 handles with 10 (bit), then vertical direction approaches scale factor (C/D)=(468/1024) and Δ=(16/35) U-(468/1024) U=0.000111607U.
Like step S530, judge at first whether n is the integral multiple of A (=35), if set up, then handling the 35th interpolated line data, the 70th interpolated line data, the 105th interpolated line data ....At this moment, like step S540, the physical location (X) that must force to set these interpolated line data equals the integral multiple (n/A) of B (B=16) unit length (U), and forces to set the site error (E)=0 of this moment, and step S540 is carrying out overall locking mechanism.Otherwise if when being false, like step S550, the physical location of n interpolated line data (X) can increase the distance of [(C/D) U], and site error (E) also can increase Δ.
Like step S552, whether the site error (E) that the vertical linearity arithmetic element is judged n interpolated line data is greater than I difference length (L_mi n).In definite site error (E) during greater than I difference length; The vertical linearity arithmetic element increases I difference length (L_min) with the physical location (X) of n interpolated line data; That is move I difference length (L_min) toward the ideal position (ideal position) of n interpolated line data, so site error (E) can further reduce I difference length (L_min).Otherwise during less than I difference length, the vertical linearity arithmetic element is not handled the physical location (X) and the site error (E) of n interpolated line data in definite site error (E).
Like step S560, carry out linear interpolation and obtain all pixel values of interpolated line data with the physical location (X) of above-mentioned n interpolated line data.
Like step S570, judge whether that all interpolated line data produce all, as not, then n is added 1 and get into step S540 like step S580; In this way, then finish all flow processs like step S590.
Can be known by above embodiments of the invention, be example with the above-mentioned correct proportions factor (B/A)=(16/35), and the vertical linearity arithmetic element has the practice of overall locking mechanism and local locks with respect mechanism simultaneously, will make site error (E) reduce effectively.That is to say that within overall locking mechanism once, the vertical linearity arithmetic element continues to monitor the relation between site error (E) and the I difference length (L_min).When the site error (E) of n interpolated line data surpasses I difference length (L_min); Then directly change physical location (X) when n interpolated line data; Make it more near the ideal position of n interpolated line data, and position potential difference (E) is also with can side by side reducing.
Please, when carrying out linear interpolation for 10 vertical linearity arithmetic elements of the present invention, its illustrate utilizes the site error sketch map of overall locking mechanism and local locks with respect mechanism with reference to Fig. 5 B.Clearly, because the correct proportions factor of vertical direction is 16/35, so the physical location (X) that known vertical linearity arithmetic element can force to set the 35th interpolated line data makes that putting error is 0; Moreover, because the present invention adds local locks with respect mechanism, therefore, when site error (E) is accumulate to I difference length (L_mi n), changes the physical location (X) of n interpolated line data and thereby reduce the site error (E) of n interpolated line data.Therefore, only use overall locking mechanism can site error be accumulate to (34 * Δ) compared to known, the present invention uses overall locking mechanism and local locks with respect mechanism can make site error (E) dwindle below I difference length (L_min) simultaneously.
Can know that by above-mentioned explanation vertical linearity arithmetic element of the present invention increases local locks with respect mechanism in addition except positive lock mechanism when carrying out linear interpolation, therefore can make that site error (E) is less.In like manner; The present invention also can be in the horizontal linearity arithmetic element; When carrying out linear interpolation, also utilize positive lock mechanism and local locks with respect mechanism simultaneously; Therefore can make that also site error (E) is less, and pixel value that calculates and ideal value gap are less, the picture quality in the output image signal is preferable.
Moreover; Because known line buffer control unit is the first stroke original line data and second original line data to be temporary in just can export the vertical linearity arithmetic element to after the line buffer and calculate the first stroke interpolated line data that are positioned at (5/8) unit length, so will delay the time point of vertical linearity arithmetic element output the first stroke interpolated line data.
Please with reference to Fig. 6, its illustrate is the relation of the running between line buffer control unit of the present invention and the vertical linearity arithmetic element.Wherein, (timing diagram) can know by the sequential that writes the original line data, and the first stroke original line data (L1) in the original image signal, second original line data (L2) write (W) first line buffer cell and the slow unit of second line in regular turn.And when the 3rd original line data (L3) write the 3rd buffer cell, the vertical linearity arithmetic element promptly calculated two penholder lambda line data (l1, l2) according to the first stroke original line data (L1) and second original line data (L2).That is to say that in fact, the first stroke inserts line data (l1) and promptly is same as the first stroke original line data (L1), and the second penholder lambda line data (l2) to be the proportion of utilization factor carry out linear interpolation calculates.
Therefore, compared to known function mode, the first stroke interpolated line data of the present invention can produce in advance, therefore, can make follow-up all interpolated line data all can produce ahead of time.
In sum, picture amplification control method of the present invention is an interpolated image signal that an original image signal of one first resolution is converted into second resolution earlier, is an output image signal of one the 3rd resolution again with this interpolated image conversion of signals.No matter vertical linearity arithmetic element or horizontal linearity arithmetic element all can utilize following mode to carry out local locks with respect mechanism.
At first, the distance in the setting original image signal between two contiguous pixels of first direction is a unit length, and this unit length is U; Then, set n and equal 1, X equals 0, and E equals 0, and wherein n is that natural number, X are that physical location, the E of n data is site error; Then; Correct proportions factor according to first resolution and the 3rd resolution calculating first direction is approached scale factor (C/D) for one of (B/A) and first direction; And the margin of error calculating the correct proportions factor according to this and approach scale factor; This margin of error is a Δ, and wherein, A and B are natural number and (B/A) computing that can't reduce again; (a) when n is not equal to A, X is increased (C/D) U, and E increase Δ,, n carries out an overall locking mechanism when equaling A; (b) as E during greater than L_min, X is moved L_min, and make E reduce L_min, wherein L_min one can distinguish length; (c) carry out a linear interpolation according to original image signal or interpolated image signal and X, calculate at least one pixel value of n data; And (d) n=n+1, and get into (a) step.
In the running of vertical linearity arithmetic element; N data are the n interpolated line data in the interpolated image signal, and two contiguous pixels of first direction are the distance between first pixel in the continuous the first stroke original line data of a vertical direction and second the original line data.
In the running of horizontal linearity arithmetic element; N data be output line number according in arbitrary output line number according to n interior pixel, and the distance between continuous two pixels in two contiguous pixels values of first direction any interpolated line data that are a horizontal direction.
Moreover, when vertical linearity arithmetic element or horizontal linearity arithmetic element are when utilizing the m position to carry out computing, the I difference length that can distinguish length and be, it is U/2
m
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Any those skilled in the art; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (5)
1. picture amplification control device that applies to display comprises:
The line buffer control unit receives the original image signal of first resolution, and comprises many original line data in this original image signal;
Line buffer is electrically connected to this line buffer control unit, temporary these many original line data;
The vertical linearity arithmetic element; Be electrically connected to this line buffer control unit; Indicate this line buffer control unit to read continuous two the original line data in these many original line data in this line buffer; And according to overall locking mechanism and the machine-processed interpolated image signal that produces second resolution of local locks with respect, and comprise many interpolated line data in this interpolated image signal; And
The horizontal linearity arithmetic element; Be electrically connected to this vertical linearity arithmetic element; Receive these many interpolated line data in this interpolated image signal in regular turn; And according to this overall locking mechanism and the machine-processed output image signal that produces the 3rd resolution of this local locks with respect, and comprise many output line number certificates in this output image signal.
2. picture amplification control device according to claim 1, wherein, this vertical linearity arithmetic element is carried out the following step:
The distance of setting between two continuous original line data of a vertical direction in this original image signal is a unit length, and this unit length is U;
Set n and equal 1, X equals 0, and E equals 0, and wherein n is that natural number, X are that a physical location, the E of a n interpolated line data is site error;
The correct proportions factor of calculating a vertical direction according to this first resolution and the 3rd resolution is approached scale factor (C/D) for (B/A) and this vertical direction; And calculate this correct proportions factor according to this and this approaches the margin of error of scale factor; This margin of error is a Δ; Wherein, A and B are the natural number and the computing that should (B/A) can't reduce again;
(a) when n is not equal to A, make X increase (C/D) U, and make E increase Δ,, n carries out overall locking mechanism when equaling A;
(b) as E during greater than L_min, X is moved L_min, and make E reduce L_min, wherein L_min is for can distinguish length;
(c) carry out linear interpolation according to this original image signal and X, calculate a plurality of pixel values of these n interpolated line data; And
(d) n=n+1, and entering should (a) step.
3. picture amplification control device according to claim 1, when wherein this vertical linearity arithmetic element was carried out computing for utilizing the m position, this can distinguish length was U/2
m
4. picture amplification control device according to claim 1, wherein, this horizontal linearity arithmetic element is carried out the following step:
The distance of setting in this interpolated image signal in arbitrary interpolated line data between two contiguous pixels is a unit length, and this unit length is U;
Set n and equal 1, X equals 0, and E equals 0, wherein n be natural number, X be arbitrary output line number according in a physical location, the E of a n pixel value be a site error;
The correct proportions factor of calculating a horizontal direction according to this first resolution and the 3rd resolution is approached scale factor (C/D) for (B/A) and this horizontal direction; And calculate this correct proportions factor according to this and this approaches a margin of error of scale factor; This margin of error is a Δ; Wherein, A and B are the natural number and the computing that should (B/A) can't reduce again;
(a) when n is not equal to A, make X increase (C/D) U, and make E increase Δ,, n carries out overall locking mechanism when equaling A;
(b) as E during greater than L_min, X is moved L_min, and make E reduce L_min, wherein L_min is for can distinguish length;
(c) carry out linear interpolation according to these many interpolated line data and X, calculate a pixel value of this n pixel; And
(d) n=n+1, and entering should (a) step.
5. picture amplification control device according to claim 1, when wherein this horizontal linearity arithmetic element was carried out computing for utilizing the m position, this can distinguish length was U/2
m
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| CN1812552A (en) * | 2005-07-28 | 2006-08-02 | 钰创科技股份有限公司 | Image second band interpolation apparatus and method for up regulation display equipment |
| CN1860788A (en) * | 2003-05-16 | 2006-11-08 | 比卡萨有限公司 | Methods and systems for image sharing over a network |
| CN101303763A (en) * | 2007-12-26 | 2008-11-12 | 公安部上海消防研究所 | Method for amplifying image based on rarefaction representation |
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| CN1860788A (en) * | 2003-05-16 | 2006-11-08 | 比卡萨有限公司 | Methods and systems for image sharing over a network |
| CN1812552A (en) * | 2005-07-28 | 2006-08-02 | 钰创科技股份有限公司 | Image second band interpolation apparatus and method for up regulation display equipment |
| CN101303763A (en) * | 2007-12-26 | 2008-11-12 | 公安部上海消防研究所 | Method for amplifying image based on rarefaction representation |
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