CN102546852B - Address automatic configuration method of fault-tolerant data center network - Google Patents

Abstract

The invention belongs to the technical field of data centers in computer network, which includes: step 1 designing a blueprint to generate a logic diagram; step 2 generating a physical diagram through physical topology; step 3 detecting errors; step 4 generating equipment drawing; step 5 matching the logic diagram and the equipment drawing; and step 6 configuring an equipment drawing address. The matching step of the logic diagram and the equipment drawing mainly comprises decomposition and verification. In the verification process, an electronic temperature and acceleration controller (TEAC) method designs three acceleration search judgment strategies to guarantee correctness, and the method achieves automatic and rapid configuration of the address of fault-tolerant data center network.

Description

The address automatic distributing method of fault tolerant data center network

Technical field

This method is to realize in fault tolerant data center, if exist hardware reason or connection error to cause actual physical topology and devise and draw the blueprint when different, the address that the method still can realize for Ci Zhong fault tolerant data center configures automatically, and this method belongs to computer network field.

Background technology

In large-scale data center, there is ten hundreds of servers and switch, for the fail safe at this large-scale data center and the consideration of high usage route, positional information and topology information (are for example usually encoded in the network address of data center, in distributed file system GFS, many data blocks will be replicated many parts, and be stored on different servers, convenience for data manipulation, data center need to understand the server how going from closer and obtain data, therefore data center can be encoded to positional information convenient operation in the network address).Although this addressing mode greatly facilitates some operation of data center, for address configuration is brought difficulty.Because the scale at available data center is extremely huge, and DHCP agreement can not be applied again when address configuration.Address human configuration will be a very long process, and there will be a lot of mistakes.So need to do the configuration fast automatically of an address to these servers and switch when configuration data center.

When actual arrangement data center, due to machine network interface card problem, or Miswire between two physical machines, or lack line etc. reason, actual physical topology is connected different from the definition devising and drawing the blueprint.Be directed to this, the address that ETAC method realizes for this fault tolerant data center network configures automatically.Owing to carrying out in ETAC method after error detection step, for not having the data center network of wrong node also can carry out the automatic configuration of address, so ETAC method is equally applicable to the right-on data center network of line.

Summary of the invention

In large-scale data, the allocation problem of address can be conceptualized as a logic diagram and the topological node correspondence problem that is connected the physical map generating of actual physics that devises and draw the blueprint and generate in the heart.Will be before wiring, the figure that physical topology should connect is called and devises and draw the blueprint, and the connection layout of actual physical machine is physical map (generally can pass through Physical topology Protocol, PCP agreement is collected).Yet due to physical machine hardware damage or Miswire etc., all can there is mistake with respect to devising and drawing the blueprint in general actual physical topology.If actual physical topology does not have mistake, ETAC method can be carried out to this kind of network the rapid configuration of address.If there is Miswire in actual physical topology, first ETAC method is removed vicious node and is generated equipment drawing in physical map, then for residue, connecting correct node and carry out the fast automatic configuration of address, is exactly for the node in logic diagram and these two figure of equipment drawing, to carry out the coupling of a respective nodes.Because equipment drawing is an induced subgraph of logic diagram, this is called an induced subgraph isomorphism problem on mathematics.ETAC method is carried out in the process of node matching, can apply the character that some induced subgraphs have search matching process is simplified.When the node in equipment drawing all corresponds on logic diagram, just can go the respective nodes in equipment drawing to carry out address configuration according to the node address marking on logic diagram.Finally again ETAC method is applied on the topological structure of various data centers, figure after deleting for different topological structures and wrong node and the limit that is connected thereof carries out the automatic Rapid matching of address, and experimental result shows that ETAC method is respond well for the automatic rapid configuration in address of fault tolerant data center.

ETAC method specifically comprises the following steps:

Step 1: logic diagram generates step, generates a logic diagram according to devising and drawing the blueprint of described data center network;

Step 2: physical map generates step, generates physical map according to actual physical topology;

Step 3: error detection step, described physical map and logic diagram are contrasted, find out physical map and whether exist and can not normally carry out the node of address configuration with respect to logic diagram; If exist, forward step 4 to; If there is no, physical map is defined as to an equipment drawing, forwards step 5 to;

Step 4: equipment drawing generates step, by described can not normal configuration node and connected limit in physical map, delete, for residue node, press adjacency matrix or adjacency list storage, generation equipment drawing;

Step 5: coupling step, the node in described equipment drawing is mated with the node in described logic diagram, find each node in equipment drawing corresponding to the node in logic diagram;

Step 6: configuration address step, for the node in equipment drawing, find the node in counterlogic figure, can to the node in equipment drawing, carry out by the address marking in logic diagram the relative set of address.

The step 1 formation logic figure that devises and draw the blueprint, wherein, devising and drawing the blueprint is the annexation connecting the physical machine defining before actual server and switch, devises and draw the blueprint by adjacency matrix or adjacency list storage, is denoted as logic diagram; Logic diagram node identification is sever or network logical address corresponding to swith.

Step 2 physical topology generates physical map, after actual physics topology connects, according to physical topology, collects agreement, obtains actual physical topology annexation, and this annexation is pressed adjacency matrix or adjacency list storage, is denoted as physical map; Physical map node identification is sever or physical address corresponding to swith.

Described physical topology is collected the realization of agreement, the information that a communication channel removes to collect physical topology of setting up on actual physical network, a controller is set and sets up a spanning tree, the physical topology information of all nodes is up transmitted the leaf node by spanning tree by spanning tree successively by communication channel, until root node.

Step 3 is specifically carried out in accordance with the following steps: step 3.1: first select a part of node in physical map, then to these each selected nodes, calculate the absolute value of difference of the SPLD of all nodes in itself and logic diagram, node note in the point of the difference absolute value minimum of SPLD in logic diagram and this physical map is done to a node pair, and the SPLD of a node is this node to the beeline of every other node in figure; Step 3.2: to the node pair described in step 3.1, in physical map and logic diagram respectively from these two points at a distance of 1 all nodes of jumping, verify whether isomorphism of these all nodes, until and these two points when x jumps, these isomorphisms, and when x+1 jumps, these put not isomorphism, the node of jumping for these x+1, adds one to their counter value; Step 3.3: after finishing the detection of all test nodes, the node that has counter value for those is by the descending of counter value, and counter value is larger, and its probability of makeing mistakes is larger; For the keeper of data center, from the large node of counter value, start to detect whether have Miswire.

The node that can not normally carry out matching addresses described in step 3 is due to hardware reason or connection error generation.

Step 5 is specifically carried out in accordance with the following steps, and division logic diagram Gl and the equipment drawing Gd of this step recurrence are less set, until each point in Gd has found the point matching in Gl, successfully returns; Or at back, found matching error, recalled, then gone to attempt mating with the next node in Gl along another direction; Because the point in logic diagram Gl generally can be more than the point in equipment drawing Gd (while there is no wrong node in physical map, the nodes of two figure be not the same), so in matching process, by empty set, those correspondences in Gd are given to correspondence less than the set in Gl, matching process guarantees the number that the set number in Gd equals to gather in Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise and decomposing and two processes of checking.

Described decomposable process is, at every turn a some v set O in the Gd of its place be separated into O { v} and { v}, other set remain unchanged, accordingly, a point u in set O ' corresponding with Gd set O in Gl is divided out, be divided into O ' { u} and { u}, in this process, claims every pair of emerging singleton { corresponding { u} of v}.

The process of described checking is, decomposite v}, { after u}, proof procedure is tested to current division, in Gd, each set is used with { annexation of v} is divided into { v} is connected and two set that are not connected; at every turn Correspondingly in Gl, each set is used with { annexation of u} is divided into { u} is connected and two set that are not connected; For emerging every pair of singleton, all go to carry out whether corresponding judgement, until do not have new singleton to occur successfully returning, or find that coupling is made mistakes and return.

Described proof procedure adopts three kinds of acceleration search cor-responding identified theorems: first theorem is: for each emerging singleton v} ∈ Gd, { u} ∈ Gl, establishes f (v)=u, i.e. u node in v node counterlogic figure in equipment drawing; To v} and each the single set element vs being connected in Gd, and and if only if, and u is connected with single set element f (vs) corresponding in Gl, and progressively coupling is gone down, and result is necessarily correct; Second theorem is: to each emerging singleton pair, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than the { number of degrees of u}; The 3rd theorem is: to each emerging singleton pair, { v} ∈ Gd, { u} ∈ Gl, v each the nonempty set O (i) in Gd be divided into the part Oc (i) that is connected with v and with the disjunct part Onc of v (i), u the nonempty set O ' corresponding with O (i) in Gl (i) be divided into the part Oc ' that is connected with u (i) and with the disjunct part Onc ' of u (i), should meet the following conditions: | Oc (i) |≤| Oc ' (i) | and|Onc (i) |≤| Onc ' (i) |, wherein | O| represents to gather the element number in O.

The invention has the beneficial effects as follows: this ETAC method is respond well for the automatic rapid configuration in address of fault tolerant data center.

Accompanying drawing explanation

Fig. 1 is the whole step block diagram of ETAC method.

Fig. 2 is for devising and drawing the blueprint, a concrete example of the physical map of actual line and equipment drawing.

Fig. 3 is that ETAC method is for an implementation procedure of Fig. 2 example shown.Comprising decomposing and verifying two main process and go to carry out split operation by corresponding points.

Fig. 4 be ETAC method for four kinds of classical data center network structures, at wrong nodes, be controlled at 50 o'clock, the variation relation between its algorithm execution time and data center's scale.

Fig. 5 is four kinds of different data center network structures in the situation that of fixing scale, and mistake is counted and the relation between the ETAC method time of implementation.

Fig. 6 is for the Bcube structure of data center network and Dcell structure, for server and switch according to a certain percentage during wrong situation, and for fixedly BCube structure and the Dcell structure of scale, the time of implementation of ETAC method.

Embodiment

Below in conjunction with accompanying drawing, the present invention is illustrated.

Fig. 1 is that ETAC method is carried out the entire block diagram of address configuration for data center network.It is containing the 1 formation logic figure that devises and draw the blueprint in steps; Step 2 physical topology generates physical map; Step 3 error detection; Step 4 equipment drawing generates; Step 5 equipment drawing and logic diagram mate; Step 6 configuration device figure address.

The step 1 formation logic figure that devises and draw the blueprint.Devising and drawing the blueprint is the annexation connecting the physical machine defining before actual server and switch, devises and draw the blueprint and can, by adjacency matrix or adjacency list storage, be denoted as logic diagram.

Step 2 physical topology generates physical map.After actual physics topology connects, according to physical topology, collect agreement (Physical topology Collection Protocol, PCP), can obtain the annexation of actual physical topology, this annexation figure can, by adjacency matrix or adjacency list storage, be denoted as physical map.

The realization that physical topology is collected agreement is the information that a communication channel removes to collect physical topology of setting up on actual physical network, for all physical topology information, there is an ETAC manager to go to set up a spanning tree, all physical topology information is up transmitted the leaf node by spanning tree successively, until root node ETAC manager.

Step 3 error detection, it is carried out in accordance with the following steps:

Step 3.1: when the actual physics topology of data center exists Miswire, ETAC method can be first according to shortest path length distribution (the shortest path length distribution of some nodes in logic diagram and physical map, SPLD), select in these two figure node that a part has identical SPLD as test node set, the SPLD of a node is this node to the distance of every other node in figure;

Step 32: compare the test node for every a pair of correspondence in logic diagram and physical map, calculate when and they are apart during x jumping figure, these two same Subgraph Isomorphisms of figure maximal phase now, yet when and they are when the x+1 jumping figure, scheme not isomorphism of maximum same sub-image for these two, the node of jumping for these x+1, adds one to their counter value;

Step 3.3: after finishing the detection of all test nodes, the node that has counter value for those carries out by the descending of counter value, and counter value is larger, and its error probability is larger; For the keeper of data center, from the large node of counter value, start to detect whether have Miswire.

It is after carrying out step 3 error detection that step 4 equipment drawing generates, determine in actual physical connection figure, due to hardware reason, or connection error etc., can not normally carry out the node of address configuration, it is deleted in physical map, for residue node, press adjacency matrix or adjacency list storage, be denoted as equipment drawing.

Step 5 equipment drawing and logic diagram coupling step is for equipment drawing and logic diagram, to carry out the matching process of corresponding node, the division logic diagram Gl of this step recurrence and equipment drawing Gd are less set, until each point in Gd has found the point matching in Gl, successfully return; Or at back, found matching error, recalled, then gone to attempt mating with the next node in Gl along another direction; Because the point in logic diagram Gl generally can be more than the point in equipment drawing Gd (while there is no wrong node in physical map, the nodes of two figure be not the same), so in matching process, by empty set, those correspondences in Gd are given to correspondence less than the set in Gl, matching process guarantees that the set number in Gd equals the set number in Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise two processes of decomposition and refinement.

The false code that equipment drawing and logic diagram mate step is as follows:

Fig. 2 is logic diagram, an example of physical map and equipment drawing.Devise and draw the blueprint and defined the annexation of server and switch, and give a logical address for each server and switch.(a) part in Fig. 2 is for having devising and drawing the blueprint of 8 nodes; (b) part is actual physical connection figure, and physical connection figure can pass through Physical topologyCollection Protocol, and PCP agreement is collected.(b) in part, between node 7 and 8, lacked an actual physical connection line; (c) partly for to have removed after 7 and 8 nodes that have Miswire, the equipment drawing of formation.

Fig. 3 is the little example of the algorithm of ETAC method in carrying out logic diagram and equipment drawing isomorphism corresponding process.Wherein, solid arrow has represented decomposition operation, and dotted arrow has represented refinement operation, and P1～P8 is a series of processes.For Gd and Gl, ETAC method, first according to the difference of server and switch, is divided into Gd { 1,2,3}, { 4,5,6}; Gl is divided into { A, B, C, D}, { E, F, G, H}.In P1 process, first ETAC method selects 2 nodes in Gd and the A node in Gl to carry out decomposition operation, and set now becomes { 2}, { 1,3}, { 4,5,6} and set { A}, { B, C, D}, { E, F, G, H}.In carrying out the process of refinement, due in Gd, what be connected with 2 is 3 and 4 nodes, belongs to respectively set { 1,3} and { 4,5,6}.The E being connected with A and G node, belong to set { E, F, G, H}.According to the acceleration strategy of the 3rd judgement search, should recall.Then along other direction to 2 and C carry out decomposition operation, set is divided into { 2}, { 1,3}, { 4,5,6} and set { C}, { A, B, D}, { E, F, G, H}.According to 2 and 3, 4 are connected, C and D, E, F is connected, set can be divided into { 2}, { 3}, { 1}, { 4}, { 5, 6} and { C}, { D}, { A, B}, { E, F}, { G, H}, P4 has occurred that new singleton is to 3--> D, then according to the relation of being connected, divide other set, set remains unchanged, in P6 process, 5 and G be decomposed out, enter P7 process, by a pair of two the emerging singleton pair of theorem: 5--> G, 6--> H carries out verifying correctness, , result is correct, then carry out division operation, G divides { A, B} is { A}, { B}, corresponding, { 1} is { 1} and { } in 5 divisions, to keep Gd identical with Gl set number, in P8 process, by emerging singleton, 1--> A is divided to other nonempty sets and obtain final result.So just obtained devising and drawing the blueprint and the corresponding relation of equipment drawing, thereby carried out corresponding to the configuration fast automatically of the address of node in devising and drawing the blueprint for the node in equipment drawing.

Decomposition process described in Fig. 3, be at every turn a some v set O in the Gd of its place be separated into O { v} and { v}, other set remains unchanged.Accordingly, a some u in set O ' corresponding with Gd set O in Gl is divided out, be divided into O ’ { u} and { u}.In this process, claim each emerging singleton { corresponding { u} of v}.

Refinement process described in Fig. 3, be carry out at every turn decomposition go out v}, and after u}, the once check of refinement process to current division.In subgraph Gd, each set is used with { annexation of v} is divided into { v} is connected and two set that are not connected.In the Blueprint Gl that devises and draw the blueprint, each set is used with { annexation of u} is divided into { u} is connected and two set that are not connected.For emerging every pair of singleton, all go to carry out whether corresponding judgement, until do not have new singleton to occur successfully returning, or find that coupling is made mistakes and return.

In the process that the point of ETAC method in carrying out figure Gl and Gd mating, because the point devising and drawing the blueprint in Gl generally can be more than the point in equipment drawing Gd, so in the process of mating in cutting, ETAC method will give correspondence to the corresponding set less than Gl in Gd by empty set.

ETAC method is cut all non-NULL small set A (i) until each small set becomes single singleton cell, an and singleton in the corresponding Gl of the singleton of each non-NULL, ETAC method has just realized the coupling for figure Gl and Gd like this, thereby carries out the coupling of address.

In equipment drawing, because for node, { choosing the effectiveness affects of algorithm of v} is very large, is guaranteeing, under the prerequisite of algorithmic match correctness, to increase substantially the search efficiency of algorithm so ETAC proposes three theorems.

First theorem is: for each emerging singleton, { v} ∈ Gd, { u} ∈ Gl establishes f (v)=u (being the u node that in equipment drawing, v node correspondence devises and draw the blueprint in blueprint).To v} and each the single set element vs being connected in Gd, and and if only if, and u is connected with single set element f (vs) corresponding in Gl, and progressively coupling is gone down, and result is necessarily correct.

Second theorem is: to each emerging singleton pair, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than the { number of degrees of u};

The 3rd theorem is: to each emerging singleton pair, { v} ∈ Gd, { u} ∈ Gl, v each the nonempty set O (i) in Gd be divided into the part Oc (i) that is connected with v and with the disjunct part Onc of v (i), u the nonempty set O ' corresponding with O (i) in Gl (i) be divided into the part Oc ' that is connected with u (i) and with the disjunct part Onc ' of u (i), should meet the following conditions: | Oc (i) |≤| Oc ' (i) | and|Onc (i) |≤| Onc ' (i) |, wherein | O| represents to gather the element number in O.

In fault tolerant data center, address automatically configures ETAC method and is equally applicable to carry out, after error detection step, do not find the situation of wrong node.Now equipment drawing and physical map are same figure.

The Address automatic matching method for fault tolerant data center that this method proposes, by for the vicious situation of actual physics topology line, remove node and the limit of those connection errors, for remaining correct node, carry out the method for Rapid matching, can in actual data center, be applied.Result of the test shows, for all data center's topological structures, ETAC method can complete the automatic Rapid matching for data center address in the time about 1 minute.

Experimental verification

In order to verify that ETAC method is effective fast for the address configuration of fault tolerant data center, the Fattree of data center and VL2 structure for switch-centric have been designed, for the wrong address of node configuring condition being distributed between different layers.In experiment, use Fattree (60)=58500 node and VL2 (20,100)=52650 node to carry out experimental verification.Experiment is fixed 50 wrong nodes between adjacent two layers,, repeat 100 experiments, match time is as following table:

Layer	Fattree(60)	VL2(20，100)
				Tl Ta Tu	Tl Ta Tu
1-2	17.36 17.40 17.49	12.51 12.55 12.60
			2-3	16.91 17.03 17.15	12.07 12.10 12.14

3-4

17.30 17.37 17.57

12.24 12.43 12.62

Wherein, 1-2 layer represents that the server-edge in Fattree and VL2 is two-layer, and layer 2-3 represents the edge-aggregation layer in Fattree and VL2, and 3-4 layer represents the aggregation-core layer in Fattree and VL2.Tl, Ta, Tu represents respectively the shortest match time, average match time and the longest match time.

In experiment, also design data center network structure BCube and DCell for server-centric.Analysis is for switch mistake and the relation of matching addresses between the time of different proportion.In test, same fixed error nodes is 50, uses BCube (8,4)=52650 and DCell (3,3)=32656 node., repeat 100 experiments.In experiment, the ratio of mistake switch is by 0%, 20%, and 40%, 60%, 80%, 100%.Be that wrong switch number is 0,10,20,30,40,50.The match time of address as shown in Figure 6.

From upper table and Fig. 6, can find out, the position of mistake node and ratio all can not affect ETAC method for the rapid configuration of fault tolerant data center network address.

Embodiment 1

In data center network, mistake nodes is fixed on 50, different data center network structure BCube, Dcell, fattree and VL2, the scale of Dang Qi data center is changed from small to big, and ETAC method is for the time of implementation (time of implementation surpasses a certain set point and thinks that address configuration is failed) of this kind of fault tolerant data center network address configuration and the relation between data center's scale.In this embodiment, ETAC method is all random generation for 50 wrong nodes of each appearance, and under network configuration and same structure for Mei Zhong data center, different node scales has all carried out repeating the simulation of 100 times.

In this embodiment, the scale of BCube structure is respectively: BCube (5,4)=6250, and BCube (6,4)=14256, on BCube (7,4)=18812 and BCube (8,4)=53248; The scale of Fattree structure is respectively: Fattree (20)=2500, and, Fattree (40)=18000, Fattree (60)=58500 and Fattree (80)=136000; The scale of VL2 structure is respectively: VL2 (10,100)=27650, VL2 (20,100)=52650, VL2 (40,100)=102650 and VL2 (60,100)=152650; The scale of Dcell structure is respectively: Dcell (4,2)=525, Dcell (2,3)=2709, Dcell (3,3)=32656 and Dcell (4,3)=221025.

Four kinds of different topology structures that occur in this embodiment and under different topology structure the node scale at different pieces of information center, ETAC method can be in the short period of time configures automatically fast for the address of this fault tolerant data center network.Fig. 4 is under four kinds of different pieces of information division centers, the relation between average time of implementation of ETAC method and data center's scale.Under four kinds of structures of data center, ETAC method is all about 1 minute, just to realize greatly the correct coupling of address.Four kinds of curves have shown at wrong nodes and have been fixed on 50, and wrong node is in data center random distribution in the situation that, and the scale of the time of implementation of ETAC method with data center increases.

In this embodiment, in order to carry out the required maximum memory space of address configuration, be respectively: Fattree needs 27.2MB, and VL2 needs 26.4MB, and BCube needs 7.6MB, and Dcell needs 24.4MB.

Embodiment 2

In data center network, four kinds of different data center network structures.When the network for every kind of structure is selected a fixedly nodes for scale.And change successively wrong nodes is ascending, observe ETAC method whether can be fine very fast this fault tolerant data center network is carried out to the automatic rapid configuration of address.The nodes of mistake is followed successively by 10,20, and 30,40,50.In node Dou Shi data center, produce at random.And under network configuration and same structure for Mei Zhong data center, same node point scale has all repeated 100 simulations.

In experiment, selecting the scale of BCube is BCube (8,4)=53248, the scale of Fattree is Fattree (60)=58500, and the scale of Dcell is Dcell (3,3)=32656, the scale of VL2 is VL2 (20,100)=52650.

In this experiment, for wrong nodes, be followed successively by 10,20,30,40,50 o'clock, ETAC method was 12s left and right for the address configuration time of Fattree structure, the address configuration time of VL2 structure is 17s left and right.And for the setup time of BCube be 41.60s～72.96s, average time 46.67s.Be 2.33s～5.17s the setup time of DCell, average time 3.57s.

Experimental result shows that ETAC method can be in the short period of time configures automatically fast for the address of this fault tolerant data center network.Fig. 5 is under four kinds of different pieces of information division centers, the relation between average time of implementation of ETAC method and wrong nodes.

In this embodiment, in order to carry out the required maximum memory space of address configuration, be respectively: Fattree needs 12.6MB, and VL2 needs 10.1MB, and BCube needs 7.6MB, and Dcell needs 3.8MB.

Claims (3)

1. an address automatic distributing method for fault tolerant data center network, the method is data center, and every server and switch arrange correct network logical address, it is characterized in that, and it comprises the following steps:

Step 1: logic diagram generates step, generates a logic diagram according to devising and drawing the blueprint of described data center network; Devising and drawing the blueprint is the annexation connecting the physical machine defining before actual server and switch, devising and drawing the blueprint can be by adjacency matrix or adjacency list storage, be denoted as logic diagram, logic diagram node identification is server or network logical address corresponding to switch;

Step 2: physical map generates step, generates physical map according to actual physical topology; Described physical topology generates physical map, after actual physics topology connects, according to physical topology, collects agreement, obtains actual physical topology annexation, and this annexation is pressed adjacency matrix or adjacency list storage, is denoted as physical map; Physical map node identification is server or physical address corresponding to switch; Described physical topology is collected the realization of agreement, the information that a communication channel removes to collect physical topology of setting up on actual physical network, a controller is set and sets up a spanning tree, the physical topology information of all nodes is up transmitted the leaf node by spanning tree by spanning tree successively by communication channel, until root node;

Step 3: error detection step, described physical map and logic diagram are contrasted, find out physical map and whether exist and can not normally carry out the node of address configuration with respect to logic diagram; If exist, forward step 4 to; If there is no, physical map is defined as to an equipment drawing, forwards step 5 to;

Step 4: equipment drawing generates step is deleted the described node that can not normally be configured and connected limit thereof in physical map, for residue node, presses adjacency matrix or adjacency list storage, generates equipment drawing;

Step 5: coupling step, the node in described equipment drawing is mated with the node in described logic diagram, find each node in equipment drawing corresponding to the node in logic diagram;

Specifically carry out in accordance with the following steps, division logic diagram Gl and the equipment drawing Gd of this step recurrence are less set, until each point in Gd has found the point matching in Gl, successfully return; Or at back, found matching error, recalled, then gone to attempt mating with the next node in Gl along another direction; Because the point in logic diagram Gl generally can be more than the point in equipment drawing Gd, so in matching process, those correspondences in Gd are given to correspondence less than the set in Gl by empty set, matching process guarantees the number that the set number in Gd equals to gather in Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise and decomposing and two processes of checking;

Described decomposable process is, at every turn a some v set O in the Gd of its place be separated into O { v} and { v}, other set remain unchanged, accordingly, a point u in set O ' corresponding with Gd set O in Gl is divided out, be divided into O ' { u} and { u}, in this process, claims each emerging singleton to the { corresponding { u} of v};

The process of described checking is, decomposite v}, { after u}, proof procedure is tested to current division, in Gd, each set is used with { annexation of v} is divided into { v} is connected and two set that are not connected; at every turn Correspondingly in Gl, each set is used with { annexation of u} is divided into { u} is connected and two set that are not connected; For emerging every pair of singleton, all go to carry out whether corresponding judgement, until do not have new singleton to occur successfully returning, or find that coupling is made mistakes and return;

Described proof procedure adopts three kinds of acceleration search cor-responding identified theorems:

First theorem is: for each emerging singleton pair, v} ∈ Gd, { u} ∈ Gl, establishes f (v)=u, i.e. u node in v node counterlogic figure in equipment drawing; To v} and each the single set element vs being connected in Gd, and and if only if, and u is connected with single set element f (vs) corresponding in Gl, and progressively coupling is gone down, and result is necessarily correct;

Second theorem is: for each emerging singleton pair, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than the { number of degrees of u};

The 3rd theorem is: for each emerging singleton pair, { v} ∈ Gd, { u} ∈ Gl, v each the nonempty set O (i) in Gd be divided into the part Oc (i) that is connected with v and with the disjunct part Onc of v (i), u the nonempty set O ' corresponding with O (i) in Gl (i) be divided into the part Oc ' that is connected with u (i) and with the disjunct part Onc ' of u (i), should meet the following conditions: | Oc (i) |≤| Oc'(i) | and|Onc (i) |≤| Onc'(i) |, wherein | O| represents to gather the element number in O;

Step 6: configuration address step, for the node in equipment drawing, find the node in counterlogic figure, by the address marking in logic diagram, the node in equipment drawing is carried out the relative set of address.

2. method according to claim 1, is characterized in that: step 3 is specifically carried out in accordance with the following steps:

Step 3.1: first according to the shortest path length distribution SPLD of some nodes in logic diagram and physical map, select in these two figure node that a part has identical SPLD as test node set, then to these each selected nodes, calculate the absolute value of difference of the shortest path length distribution SPLD of all nodes in itself and logic diagram, node note in the point of the difference absolute value minimum of SPLD in logic diagram and this physical map is done to a node pair, and the SPLD of a node is this node to the beeline of every other node in figure;

Step 3.2: to the node pair described in step 3.1, in physical map and logic diagram respectively from these two points at a distance of 1 all nodes of jumping, verify whether isomorphism of these all nodes, until and these two points when x jumps, these two same Subgraph Isomorphisms of figure maximal phase now, and when x+1 jumps, these two maximum same sub-image of figure are isomorphism not, the node of jumping for these x+1, adds one to their counter value;

Step 3.3: after finishing the detection of all test nodes, the node that has counter value for those is by the descending of counter value, and counter value is larger, and its probability of makeing mistakes is larger; For the keeper of data center, from the large node of counter value, start to detect whether have Miswire.

3. method according to claim 1, is characterized in that: the node that can not normally carry out address configuration described in step 3 is due to hardware reason or connection error generation.