CN102546852A - Address automatic configuration method of fault-tolerant data center network - Google Patents

Address automatic configuration method of fault-tolerant data center network Download PDF

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CN102546852A
CN102546852A CN2011104155703A CN201110415570A CN102546852A CN 102546852 A CN102546852 A CN 102546852A CN 2011104155703 A CN2011104155703 A CN 2011104155703A CN 201110415570 A CN201110415570 A CN 201110415570A CN 102546852 A CN102546852 A CN 102546852A
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node
logic diagram
physical
address
equipment drawing
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CN102546852B (en
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胡成臣
张彻
张宏涛
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Xian Jiaotong University
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Xian Jiaotong University
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Abstract

The invention belongs to the technical field of data centers in computer network, which includes: step 1 designing a blueprint to generate a logic diagram; step 2 generating a physical diagram through physical topology; step 3 detecting errors; step 4 generating equipment drawing; step 5 matching the logic diagram and the equipment drawing; and step 6 configuring an equipment drawing address. The matching step of the logic diagram and the equipment drawing mainly comprises decomposition and verification. In the verification process, an electronic temperature and acceleration controller (TEAC) method designs three acceleration search judgment strategies to guarantee correctness, and the method achieves automatic and rapid configuration of the address of fault-tolerant data center network.

Description

The address automatic distributing method of fault tolerant data center network
Technical field
This method is to be implemented in the fault tolerant data center; If exist hardware reason or connection error to cause the actual physical topology and devise and draw the blueprint not simultaneously; This method still can realize disposing automatically for the address of this kind fault tolerant data center, and this method belongs to computer network field.
Background technology
In large-scale data center; Have ten hundreds of servers and switch, for the fail safe at this large-scale data center and the consideration of high usage route, positional information and topology information (for example usually are encoded in the network address of data center; In distributed file system GFS; Many data blocks will be replicated many parts, and are stored on the different servers, for the convenience of data manipulation; Data center need understand the server that how to go from closer and obtain data, thus data center can with positional information be encoded to be convenient in the network address operation).Though this addressing mode greatly facilitates some operation of data center, for address configuration is brought difficulty.Because the scale at available data center is extremely huge, and the DHCP agreement can not be used again when address configuration.The address human configuration will be a very long process, and a lot of mistakes can occur.So when the configuration data center, need do the configuration fast automatically of an address to these servers and switch.
When actual arrangement data center, because machine network interface card problem, perhaps Miswire between two physical machines perhaps lacks line or the like reason, makes the actual physical topology connect different with the definition that devises and draw the blueprint.Be directed to this, the ETAC method realizes disposing automatically for the address of this fault tolerant data center network.Owing to after carrying out the wrong detection step in the ETAC method, also can carry out the automatic configuration of address for the data center network that does not have wrong node, so the ETAC method is equally applicable to the right-on data center network of line.
Summary of the invention
In the large-scale data in the heart the allocation problem of address can be conceptualized as the logic diagram that generates of devising and drawing the blueprint is connected the physical map of generation with the actual physics topology node correspondence problem.Will be before wiring, the figure that physical topology should connect is called and devises and draw the blueprint, and the connection layout of actual physical machine is physical map (generally can pass through Physical topology Protocol, the PCP agreement is collected).Yet because physical machine hardware damage or Miswire etc., all can there be mistake in general actual physical topology with respect to devising and drawing the blueprint.If the actual physical topology does not have mistake, then the ETAC method can be carried out the quick configuration of address to this kind network.If there is Miswire in the actual physical topology; Then the ETAC method is at first removed vicious node and is generated equipment drawing in physical map; Connecting correct node for residue then and carry out the fast automatic configuration of address, promptly is exactly the coupling of carrying out a respective nodes for the node among logic diagram and these two figure of equipment drawing.Because equipment drawing is an induced subgraph of logic diagram, this is called an induced subgraph isomorphism problem on mathematics.The ETAC method is carried out in the process of node matching, can use the character that some induced subgraphs have the search matched process is simplified.When the node in equipment drawing all corresponds on the logic diagram, just can go the respective nodes in the equipment drawing has been carried out address configuration according to the node address that marks on the logic diagram.Again the ETAC method is applied on the topological structure of various data centers at last; Carry out the coupling fast automatically of address for the figure after different topological structures and wrong node and the limit deletion that links to each other thereof, experimental result shows the ETAC method, and allocative effect is good fast automatically for the address of fault tolerant data center.
The ETAC method specifically may further comprise the steps:
Step 1: logic diagram generates step, generates a logic diagram according to devising and drawing the blueprint of said data center network;
Step 2: physical map generates step, generates physical map according to the actual physical topology;
Step 3: the wrong detection step, said physical map and logic diagram are compared, find out physical map and whether have the node that can not normally carry out address configuration with respect to logic diagram; If exist, then forward step 4 to; If do not exist, then physical map is defined as an equipment drawing, forward step 5 to;
Step 4: equipment drawing generates step, and said node and continuous limit thereof that can not normal configuration be deleted in physical map, press adjacency matrix or adjacency list storage, generation equipment drawing for the residue node;
Step 5: the coupling step, the node in node in the said equipment drawing and the said logic diagram is mated, find each node in the equipment drawing corresponding to the node in the logic diagram;
Step 6: the configuration address step, find the node among the counterlogic figure for the node in the equipment drawing, then can carry out the relative set of address by the address that marks in the logic diagram to the node in the equipment drawing.
The step 1 formation logic figure that devises and draw the blueprint, wherein, devising and drawing the blueprint is the annexation of the physical machine of definition before connecting actual server and switch, devises and draw the blueprint by adjacency matrix or adjacency list storage, remembers and makes logic diagram; The logic diagram node identification is sever or the corresponding network logical address of swith.
Step 2 physical topology generates physical map, after the actual physics topology connects, collects agreement according to physical topology, obtains the actual physical topological connection relation, and this annexation is pressed adjacency matrix or adjacency list storage, and note is made physical map; The physical map node identification is sever or swith physical address corresponding.
Said physical topology is collected the realization of agreement; Be the information that a communication channel removes to collect physical topology of on the actual physical network, setting up; A controller is set sets up a generation tree; The physical topology information of all nodes will up be transmitted by generating tree through communication channel by the leaf node that generates tree successively, up to root node.
Step 3 is specifically carried out according to following steps: step 3.1: at first in physical map, select a part of node; Then to these each selected nodes; Calculate its with logic diagram in the absolute value of difference of SPLD of all nodes; It is right that the point that the difference absolute value of SPLD in the logic diagram is minimum and the node note in this physical map are done a node, the beeline of the SPLD of a node every other node that be this node in scheme; Step 3.2: right to the described node of step 3.1, in physical map and logic diagram,, verify whether isomorphism of these all nodes respectively from beginning at a distance of 1 all nodes of jumping with these two points; When apart x jumps with these two points; These isomorphisms, and when x+1 jumped, these put not isomorphism; The node of then jumping for these x+1 adds one to their counter value; Step 3.3: after the detection that finishes all test nodes, by the descending of counter value, the counter value is big more for those nodes with counter value, and its probability of errors is big more; For the keeper of data center, begin to detect whether have Miswire from the big node of counter value.
The said node that can not normally carry out matching addresses of step 3 is because hardware reason or connection error produce.
Step 5 is specifically carried out according to following steps, and the division logic diagram Gl and the equipment drawing Gd of this step recurrence are littler set, and each point in Gd has all found the point that is complementary in Gl, then successfully return; Perhaps found matching error, then recalled, then gone to mate along the next node among another direction trial and the Gl at back; Because the point among the logic diagram Gl generally can be more than the point among the equipment drawing Gd (the node number of two figure be not the same when having wrong node in the physical map); So in matching process; With empty set those correspondences among the Gd are given correspondence less than the set among the Gl, matching process guarantees the number that the set number among the Gd equals to gather among the Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise decomposition and verify two processes.
Said decomposable process does; At every turn a some v by the set O of its place among the Gd be separated into {v} with v}, other set remain unchanged, and are corresponding; Divide a some u among the set O ' corresponding among the Gl out with Gd set O; Be divided into O ' {u} with { u} in this process, claims every pair of emerging singleton { v} correspondence { u}.
The process of said checking does, decomposite v}, { after the u}, proof procedure is tested to current division, in Gd, uses each set with { annexation of v} is divided into { v} links to each other and two set that do not link to each other; at every turn Correspondingly in Gl, use each set with { annexation of u} is divided into { u} links to each other and two set that do not link to each other; For emerging every pair of singleton, all go to carry out whether corresponding judgement, up to there not being new singleton to occur then successfully returning, find perhaps that coupling is made mistakes to return.
Said proof procedure adopts three kinds of acceleration search cor-responding identified theorems: first theorem is: for each emerging singleton v} ∈ Gd, and u} ∈ Gl, establish f (v)=u, i.e. u node among the v node counterlogic figure in the equipment drawing; To each the single set element vs that links to each other among v} and the Gd, and if only if u all with Gl in corresponding single set element f (vs) link to each other, then progressively coupling is gone down, the result is necessarily correct; Second theorem is: right to each emerging singleton, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than { the number of degrees of u}; The 3rd theorem is: right to each emerging singleton; { v} ∈ Gd; { u} ∈ Gl; V each the nonempty set O (i) among the Gd be divided into the part of O c (i) that links to each other with v and with the disjunct part of O nc of v (i); U the nonempty set O ' corresponding among the Gl with O (i) (i) be divided into the part of O c ' that links to each other with u (i) and with the disjunct part of O nc ' of u (i), then should meet the following conditions: | Oc (i) |≤| Oc ' (i) | and|Onc (i) |≤| Onc ' (i) |, wherein | O| representes to gather the element number among the O.
The invention has the beneficial effects as follows: this ETAC method is good for the automatically quick allocative effect in the address of fault tolerant data center.
Description of drawings
Fig. 1 is the whole step block diagram of ETAC method.
Fig. 2 is for devising and drawing the blueprint a concrete example of the physical map of actual line and equipment drawing.
Fig. 3 is used for an implementation procedure of example shown in Figure 2 for the ETAC method.Comprising decomposing and verifying two main processes and go to carry out the split operation with corresponding points.
Fig. 4 is used for the data center network structure of four kinds of classics for the ETAC method, in wrong node numerical control built in 50 o'clock, the variation relation between its algorithm execution time and the data center's scale.
Fig. 5 is four kinds of different data center network structures under the situation of fixing scale, and mistake is counted and the relation between the ETAC method time of implementation.
Fig. 6 is for the Bcube structure of data center network and Dcell structure, during for the wrong according to a certain percentage situation of server and switch, and for fixedly the BCube structure and the Dcell structure of scale, the time of implementation of ETAC method.
Embodiment
Below in conjunction with accompanying drawing the present invention is done and to specify.
Fig. 1 is the address configuration of the entire block diagram ETAC method is carried out to(for) data center network.It contains in steps the 1 formation logic figure that devises and draw the blueprint; Step 2 physical topology generates physical map; Step 3 wrong detection; Step 4 equipment drawing generates; Step 5 equipment drawing and logic diagram mate; Step 6 configuration device figure address.
The step 1 formation logic figure that devises and draw the blueprint.Devising and drawing the blueprint is the annexation of the physical machine of definition before connecting actual server and switch, and devising and drawing the blueprint can be by adjacency matrix or adjacency list storage, and note is made logic diagram.
Step 2 physical topology generates physical map.After the actual physics topology connects; (Physical topology Collection Protocol PCP), can obtain the annexation of actual physical topology to collect agreement according to physical topology; This annexation figure can be by adjacency matrix or adjacency list storage, and note is made physical map.
The realization that physical topology is collected agreement is the information that a communication channel removes to collect physical topology of on the actual physical network, setting up; For all physical topology information; There is an ETAC manager to go to set up one and generates tree; All physical topology information will up be transmitted by the leaf node that generates tree successively, up to root node ETAC manager.
Step 3 wrong detection, it is carried out according to following steps:
Step 3.1: when there is Miswire in the actual physics topology of data center; The ETAC method is shortest path length distribution (the shortest path length distribution of basis some nodes in logic diagram and physical map at first; SPLD); Select among these two figure the node that a part has identical SPLD and gather, the distance of the SPLD of a node every other node that be this node in scheme as test node;
Step 32: in logic diagram and physical map, compare for each test node to correspondence; Calculate when with they apart during the x jumping figure; This moment these two the maximum same sub-image isomorphisms of figure, yet when with they when the x+1 jumping figure, scheme not isomorphism of maximum same sub-image for these two; The node of then jumping for these x+1 adds one to their counter value;
Step 3.3: after the detection that finishes all test nodes, carry out by the descending of counter value for those nodes with counter value, the counter value is big more, and its error probability is big more; For the keeper of data center, begin detection from the big node of counter value and whether exist Miswire to get final product.
It is after carrying out step 3 wrong detection that step 4 equipment drawing generates; Confirm in the actual physical connection layout, because hardware reason, perhaps connection error etc.; Can not normally carry out the node of address configuration; It is deleted in physical map, press adjacency matrix or adjacency list storage for the residue node, note is made equipment drawing.
Step 5 equipment drawing and logic diagram coupling step is the matching process that carries out corresponding node for equipment drawing and logic diagram; The division logic diagram Gl of this step recurrence and equipment drawing Gd are littler set; Each point in Gd has all found the point that is complementary in Gl, then successfully return; Perhaps found matching error, then recalled, then gone to mate along the next node among another direction trial and the Gl at back; Because the point among the logic diagram Gl generally can be more than the point among the equipment drawing Gd (the node number of two figure be not the same when having wrong node in the physical map); So in matching process; With empty set those correspondences among the Gd are given correspondence less than the set among the Gl, matching process guarantees that the set number among the Gd equals the set number among the Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise two processes of decomposition and refinement.
The false code that equipment drawing and logic diagram mate step is following:
Fig. 2 is a logic diagram, an instance of physical map and equipment drawing.Devising and drawing the blueprint has defined the annexation of server and switch, and gives a logical address for each server and switch.(a) part among Fig. 2 is for having devising and drawing the blueprint of 8 nodes; (b) part is the actual physical connection layout, and physical connection figure can pass through Physical topologyCollection Protocol, and the PCP agreement is collected.(b) lacked an actual physical connecting line between the node 7 and 8 in the part; (c) part is after having removed 7 and 8 nodes that Miswire is arranged, the equipment drawing of formation.
Fig. 3 is the little instance of the algorithm of ETAC method in carrying out logic diagram and equipment drawing isomorphism corresponding process.Wherein, solid arrow has been represented the decomposition operation, and dotted arrow has been represented the refinement operation, and P1~P8 is a series of processes.For Gd and Gl, the ETAC method is different according to server and switch at first, Gd is divided into 1,2,3}, and 4,5,6}; Gl is divided into { A, B, C, D}, { E, F, G, H}.In the P1 process, the ETAC method at first selects 2 nodes and the A node among the Gl among the Gd to carry out the decomposition operation, set now become 2}, and 1,3}, 4,5,6} and set { A}, { B, C, D}, { E, F, G, H}.In the process of carrying out refinement, because in Gd, what link to each other with 2 is 3 and 4 nodes, belong to respectively set 1,3} and 4,5,6}.E that links to each other with A and G node belong to set { E, F, G, H}.According to the 3rd acceleration strategy of judging search, then should recall.Carry out decomposition operation to 2 with C along other direction then, set is divided into 2}, 1,3}, 4,5,6} and set { C}, { A, B, D}, { E, F, G, H}.Link to each other according to 2 and 3,4, C and D, E, F links to each other, and set can be divided into { 2}, { 3}; 1}, 4}, 5,6} and { C}, { D}, { A; B}, { { G, H}, P4 new singleton occurred to 3-->D for E, F}; Divide other set according to the relation of linking to each other then, set remains unchanged, and in the P6 process, 5 are decomposed out with G, get into the P7 process, right with a pair of two the emerging singleton of theorem: 5-->G; 6-->H carries out verifying correctness,, the result is correct, carries out division operation then, and { A, B} are { A} in the G division; B}, corresponding, { 1} is that { 1} and { } to keep Gd and Gl set number identical, in the P8 process, divide other nonempty sets with emerging singleton to 1-->A and obtain final result in 5 divisions.So just obtained devising and drawing the blueprint corresponding relation with equipment drawing, thus carry out corresponding to the configuration fast automatically of the address of node in devising and drawing the blueprint for the node in the equipment drawing.
The described decomposition process of Fig. 3, be at every turn a some v by the set O of its place among the Gd be separated into {v} with { v}, other set remains unchanged.Accordingly, divide a some u among the set O ' corresponding among the Gl out, be divided into O ' and { u} with Gd set O.In this process, claim each emerging singleton { corresponding { u} of v}.
The described refinement process of Fig. 3 is to go out that { v}, { after the u}, the refinement process is to the once check of current division carrying out decomposition at every turn.In subgraph Gd, use each set with { annexation of v} is divided into { v} links to each other and two set that do not link to each other.In the Blueprint Gl that devises and draw the blueprint, use each set with { annexation of u} is divided into { u} links to each other and two set that do not link to each other.For emerging every pair of singleton, all go to carry out whether corresponding judgement, up to there not being new singleton to occur then successfully returning, find perhaps that coupling is made mistakes to return.
In the process that the point of ETAC method in carrying out figure Gl and Gd mating; Point owing to devise and draw the blueprint among the Gl generally can be more than the point among the equipment drawing Gd; So in the process that cutting is mated, the ETAC method will be given correspondence to corresponding among the Gd less than the set of Gl with empty set.
The all non-NULL small set A (i) of ETAC method cutting become single singleton cell up to each small set; An and singleton among all corresponding Gl of the singleton of each non-NULL; The ETAC method has just realized the coupling for figure Gl and Gd like this, thereby carries out the coupling of address.
In equipment drawing, because { choosing the effectiveness affects of algorithm of v} is very big, so ETAC proposes three theorems under the prerequisite that guarantees the algorithmic match correctness, increases substantially the search efficiency of algorithm for node.
First theorem is: for each emerging singleton v} ∈ Gd, and u} ∈ Gl, establish f (v)=u (be in the equipment drawing v node correspondence devise and draw the blueprint the u node among the blueprint).To each the single set element vs that links to each other among v} and the Gd, and if only if u all with Gl in corresponding single set element f (vs) link to each other, then progressively coupling is gone down, the result is necessarily correct.
Second theorem is: right to each emerging singleton, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than { the number of degrees of u};
The 3rd theorem is: right to each emerging singleton; { v} ∈ Gd; { u} ∈ Gl; V each the nonempty set O (i) among the Gd be divided into the part of O c (i) that links to each other with v and with the disjunct part of O nc of v (i); U the nonempty set O ' corresponding among the Gl with O (i) (i) be divided into the part of O c ' that links to each other with u (i) and with the disjunct part of O nc ' of u (i), then should meet the following conditions: | Oc (i) |≤| Oc ' (i) | and|Onc (i) |≤| Onc ' (i) |, wherein | O| representes to gather the element number among the O.
After the address disposes the ETAC method automatically and is equally applicable to carry out the wrong detection step in the fault tolerant data center, do not find the situation of wrong node.This moment, equipment drawing and physical map were same figure.
The address automatic matching method that this method proposes for fault tolerant data center; Through for the vicious situation of actual physics topology line; Remove the node and the limit of those connection errors; Method for remaining correct node matees fast can be applied in the data center of reality.Result of the test shows that for all data center's topological structures, the ETAC method can both be accomplished mating fast automatically for the data center address in the time about 1 minute.
Experimental verification
In order to verify that the ETAC method is effective fast for the address configuration of fault tolerant data center, Fattree of data center and VL2 structure have been designed, for the wrong address of node configuring condition that is distributed between the different layers for switch-centric.Use the checking that experimentizes of Fattree (60)=58500 node and VL2 (20,100)=52650 node in the experiment.Experiment is fixed 50 wrong nodes between adjacent two layers,, repeat 100 experiments, match time such as following table:
Layer Fattree(60) VL2(20,100)
Tl ?Ta ?Tu Tl ?Ta ?Tu
1-2 17.36 17.40 17.49 12.51 12.55 12.60
2-3 16.91 17.03 17.15 12.07 12.10 12.14
3-4 17.30 17.37 17.57 12.24 12.43 12.62
Wherein, the 1-2 layer represents the server-edge among Fattree and the VL2 two-layer, and layer 2-3 is represented the edge-aggregation layer among Fattree and the VL2, and the 3-4 layer is represented the aggregation-core layer among Fattree and the VL2.Tl, Ta, Tu represent the shortest match time respectively, average match time and the longest match time.
Also design data center network structure BCube and DCell in the experiment for server-centric.Analysis is for the switch mistake and the relation of matching addresses between the time of different proportion.Same fixed error node number is 50 in the test, uses BCube (8,4)=52650 and DCell (3,3)=32656 node., repeat 100 experiments.In the experiment, the ratio of mistake switch is by 0%, 20%, and 40%, 60%, 80%, 100%.Promptly wrong switch number is 0,10,20,30,40,50.The match time of address is as shown in Figure 6.
Can find out that from last table and Fig. 6 the position of mistake node and ratio all can not influence the quick configuration of ETAC method for fault tolerant data center network address.
Embodiment 1
In data center network; Mistake node number is fixed on 50; Different data center network structure BCube, Dcell, fattree and VL2; When the scale of its data center is changed from small to big, the ETAC method is for the relation between time of implementation of this kind fault tolerant data center network address configuration (time of implementation surpass a certain set point then think address configuration failure) and the data center's scale.In this embodiment, the ETAC method all produces for 50 wrong nodes of each appearance at random, and for the network configuration of every kind of data center with under a kind of structure, the different nodes scale has all carried out repeating 100 times simulation.
Among this embodiment, the scale of BCube structure is respectively: BCube (5,4)=6250, and BCube (6,4)=14256 is on BCube (7,4)=18812 and the BCube (8,4)=53248; The scale of Fattree structure is respectively: Fattree (20)=2500, and, Fattree (40)=18000, Fattree (60)=58500 and Fattree (80)=136000; The scale of VL2 structure is respectively: VL2 (10,100)=27650, VL2 (20,100)=52650, VL2 (40,100)=102650 and VL2 (60,100)=152650; The scale of Dcell structure is respectively: Dcell (4,2)=525, Dcell (2,3)=2709, Dcell (3,3)=32656 and Dcell (4,3)=221025.
Four kinds of different topology structures that occur among this embodiment and under the different topology structure node scale at different pieces of information center, the ETAC method can both be in the short period of time disposes for the address of this fault tolerant data center network automatically fast.Fig. 4 is under four kinds of different pieces of information division centers, the relation between average time of implementation of ETAC method and the data center's scale.Under four kinds of structures of data center, the ETAC method all is the big correct match of address that just can realize about 1 minute.Four kinds of curve display be fixed on 50 at wrong node number, and under the situation of wrong node random distribution in data center, the scale of the time of implementation of ETAC method with data center increases.
In this embodiment, be respectively in order to carry out the required maximum memory space of address configuration: Fattree needs 27.2MB, and VL2 needs 26.4MB, and BCube needs 7.6MB, and Dcell needs 24.4MB.
Embodiment 2
In data center network, four kinds of different data center network structures.When for the fixing node number of scale of one of the network selecting of every kind of structure.And change successively the node number of mistake is ascending, observe the ETAC method whether can be fine very fast this fault tolerant data center network is carried out the configuration fast automatically of address.The node number of mistake is followed successively by 10,20, and 30,40,50.Node all is in data center, to produce at random.And for the network configuration of every kind of data center with under a kind of structure, the same node point scale has all repeated 100 simulations.
In experiment, selecting the scale of BCube is BCube (8,4)=53248, and the scale of Fattree is Fattree (60)=58500, and the scale of Dcell is Dcell (3,3)=32656, and the scale of VL2 is VL2 (20,100)=52650.
In this experiment, be followed successively by 10,20 for wrong node number, 30,40,50 o'clock, the ETAC method was about 12s for the address configuration time of Fattree structure, the address configuration time of VL2 structure is about 17s.And for the setup time of BCube be 41.60s~72.96s, average time 46.67s.Be 2.33s~5.17s the setup time of DCell, average time 3.57s.
Experimental result shows that the ETAC method can both be in the short period of time disposes for the address of this fault tolerant data center network automatically fast.Fig. 5 is under four kinds of different pieces of information division centers, the relation between average time of implementation of ETAC method and the wrong node number.
In this embodiment, be respectively in order to carry out the required maximum memory space of address configuration: Fattree needs 12.6MB, and VL2 needs 10.1MB, and BCube needs 7.6MB, and Dcell needs 3.8MB.

Claims (10)

1. the address automatic distributing method of a fault tolerant data center network, this method are that every the sever and the swith of data center is provided with correct network logical address, it is characterized in that it may further comprise the steps:
Step 1: logic diagram generates step, generates a logic diagram according to devising and drawing the blueprint of said data center network;
Step 2: physical map generates step, generates physical map according to the actual physical topology;
Step 3: the wrong detection step, said physical map and logic diagram are compared, find out physical map and whether have the node that can not normally carry out address configuration with respect to logic diagram; If exist, then forward step 4 to; If do not exist, then physical map is defined as an equipment drawing, forward step 5 to;
Step 4: equipment drawing generates step, and said node and continuous limit thereof that can not normal configuration be deleted in physical map, press adjacency matrix or adjacency list storage, generation equipment drawing for the residue node;
Step 5: the coupling step, the node in node in the said equipment drawing and the said logic diagram is mated, find each node in the equipment drawing corresponding to the node in the logic diagram;
Step 6: the configuration address step, find the node among the counterlogic figure for the node in the equipment drawing, then can carry out the relative set of address by the address that marks in the logic diagram to the node in the equipment drawing.
2. method according to claim 1; It is characterized in that: the step 1 formation logic figure that devises and draw the blueprint, wherein, devising and drawing the blueprint is the annexation connecting the physical machine that defines before actual server and the switch; Devise and draw the blueprint by adjacency matrix or adjacency list storage, note is made logic diagram; The logic diagram node identification is sever or the corresponding network logical address of swith.
3. method according to claim 1; It is characterized in that: step 2 physical topology generates physical map; After the actual physics topology connects, collect agreement according to physical topology, obtain the actual physical topological connection relation; This annexation is pressed adjacency matrix or adjacency list storage, and note is made physical map; The physical map node identification is sever or swith physical address corresponding.
4. method according to claim 3; It is characterized in that: said physical topology is collected the realization of agreement; Be the information that a communication channel removes to collect physical topology of on the actual physical network, setting up; A controller is set sets up a generation tree, the physical topology information of all nodes will be pressed to generate to set up through communication channel and transmitted by the leaf node of generation tree successively, up to root node.
5. method according to claim 1 is characterized in that: step 3 is specifically carried out according to following steps:
Step 3.1: at first in physical map, select a part of node; Then to these each selected nodes; Calculate its with logic diagram in the absolute value of difference of SPLD of all nodes; It is right that the point that the difference absolute value of SPLD in the logic diagram is minimum and the node note in this physical map are done a node, the beeline of the SPLD of a node every other node that be this node in scheme;
Step 32: right to the described node of step 3.1, in physical map and logic diagram,, verify whether isomorphism of these all nodes respectively from beginning at a distance of 1 all nodes of jumping with these two points; When apart x jumps with these two points; These isomorphisms, and when x+1 jumped, these put not isomorphism; The node of then jumping for these x+1 adds one to their counter value;
Step 3.3: after the detection that finishes all test nodes, by the descending of counter value, the counter value is big more for those nodes with counter value, and its probability of errors is big more; For the keeper of data center, begin to detect whether have Miswire from the big node of counter value.
6. method according to claim 1 is characterized in that: the said node that can not normally carry out matching addresses of step 3 is because hardware reason or connection error produce.
7. method according to claim 1; It is characterized in that: step 5 is specifically carried out according to following steps; The division logic diagram Gl and the equipment drawing Gd of this step recurrence are littler set, and each point in Gd has all found the point that is complementary in Gl, then successfully return; Perhaps found matching error, then recalled, then gone to mate along the next node among another direction trial and the Gl at back; Because the point among the logic diagram Gl generally can be more than the point among the equipment drawing Gd (the node number of two figure be not the same when having wrong node in the physical map); So in matching process; With empty set those correspondences among the Gd are given correspondence less than the set among the Gl, matching process guarantees the number that the set number among the Gd equals to gather among the Gl; When carrying out logic diagram and equipment drawing coupling, mainly comprise decomposition and verify two processes.
8. method according to claim 7 is characterized in that: said decomposable process does, at every turn a some v by the set O among the Gd of its place be separated into {v} with { v}; Other set remain unchanged; Accordingly, divide a some u among the set O ' corresponding among the Gl out, be divided into O ' and { u} with Gd set O; In this process, claim every pair of emerging singleton { corresponding { u} of v}.
9. method according to claim 7; It is characterized in that: the process of said checking does, decomposites at every turn that { v} is { after the u}; Proof procedure is tested to current division, in Gd, uses each set with { annexation of v} is divided into { v} links to each other and two set that do not link to each other; Correspondingly in Gl, use each set with { annexation of u} is divided into { u} links to each other and two set that do not link to each other; For emerging every pair of singleton, all go to carry out whether corresponding judgement, up to there not being new singleton to occur then successfully returning, find perhaps that coupling is made mistakes to return.
10. method according to claim 9 is characterized in that: said proof procedure adopts three kinds of acceleration search cor-responding identified theorems:
First theorem is: for each emerging singleton v} ∈ Gd, and u} ∈ Gl, establish f (v)=u, i.e. u node among the v node counterlogic figure in the equipment drawing; To each the single set element vs that links to each other among v} and the Gd, and if only if u all with Gl in corresponding single set element f (vs) link to each other, then progressively coupling is gone down, the result is necessarily correct;
Second theorem is: right to each emerging singleton, v} ∈ Gd, and u} ∈ Gl, { number of degrees of v} are greater than { the number of degrees of u};
The 3rd theorem is: right to each emerging singleton; { v} ∈ Gd; { u} ∈ Gl; V each the nonempty set O (i) among the Gd be divided into the part of O c (i) that links to each other with v and with the disjunct part of O nc of v (i); U the nonempty set O ' corresponding among the Gl with O (i) (i) be divided into the part of O c ' that links to each other with u (i) and with the disjunct part of O nc ' of u (i), then should meet the following conditions: | Oc (i)≤| Oc ' (i) | and|Onc (i) |≤| Onc ' (i) |, wherein | O| representes to gather the element number among the O.
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