CN102546852A - Address automatic configuration method of fault-tolerant data center network - Google Patents

Abstract

The method belongs to the technical field of data center in computer network, and it comprises step 1: design blueprint to generate logical diagram; step 2, physical topology to generate physical diagram; step 3, error detection; step 4, equipment diagram to generate; step 5, logic diagram and equipment diagram to match, Step 6 Configure the device map address. Wherein, the step of matching the logic diagram and the equipment diagram mainly includes two processes of decomposition and verification. During the verification process, the ETAC method designed three accelerated search and judgment strategies to ensure correctness. This method realizes the automatic and rapid address configuration of the fault-tolerant data center network.

Description

Address auto-configuration method for fault-tolerant data center network

technical field

This method is implemented in a fault-tolerant data center. If there are hardware reasons or connection errors that cause the actual physical topology to be different from the design blueprint, this method can still realize the automatic configuration of the address of this fault-tolerant data center. This method belongs to the computer network field.

Background technique

In a large-scale data center, there are tens of thousands of servers and switches. For the sake of security and efficient routing of this large-scale data center, location information and topology information are often encoded into the network address of the data center ( For example, in the distributed file system GFS, many data blocks have to be replicated in multiple copies and stored on different servers. For the convenience of data operations, the data center needs to know how to obtain data from relatively close servers. Therefore, the data center will encode the location information into the network address for easy operation). Although this addressing method greatly facilitates certain operations in the data center, it brings difficulties to address configuration. Because the scale of the existing data center is extremely large, and the DHCP protocol cannot be applied during address configuration. Address manual configuration will be a very long process, and there will be many mistakes. Therefore, when configuring the data center, it is necessary to automatically and quickly configure the addresses of these servers and switches.

When actually laying out the data center, the actual physical topology connection is different from the definition in the design blueprint due to the problem of the network card of the machine, or the connection error between two physical machines, or the lack of connection, etc. Aiming at this, the ETAC method implements automatic address configuration for this kind of fault-tolerant data center network. After the error detection step in the ETAC method, the address can also be automatically configured for the data center network without error nodes, so the ETAC method is also applicable to the data center network with completely correct connections.

Contents of the invention

The problem of address allocation in large-scale data centers can be abstracted as a node correspondence between the logical graph generated by the design blueprint and the physical graph generated by the actual physical topology connection. Before wiring, the diagram that the physical topology should be connected is called the design blueprint, and the connection diagram of the actual physical machine is the physical diagram (generally, it can be collected through the Physical topology Protocol, PCP protocol). However, due to physical machine hardware damage or wiring errors, there will generally be errors in the actual physical topology relative to the design blueprint. If there is no error in the actual physical topology, the ETAC method can quickly configure addresses for such a network. If there are wiring errors in the actual physical topology, the ETAC method first removes the wrong nodes in the physical graph to generate a device graph, and then quickly and automatically configures the addresses of the remaining nodes with correct connections, that is, for the logical graph and the device graph. Nodes in the two graphs are matched by a corresponding node. Because the device graph is a derived subgraph of the logic graph, this is called a derived subgraph isomorphism problem in mathematics. In the process of node matching in ETAC method, some properties of derived subgraphs can be applied to simplify the search and matching process. When all the nodes in the device diagram correspond to the logic diagram, address configuration can be performed on the corresponding nodes in the device diagram according to the node addresses marked on the logic diagram. Finally, the ETAC method is applied to the topological structures of various data centers, and the addresses are automatically and quickly matched for different topological structures and error nodes and their connected edges. The experimental results show that the ETAC method is suitable for fault-tolerant data. The automatic and quick configuration of the center's address works well.

The ETAC method specifically includes the following steps:

Step 1: a logic diagram generation step, generating a logic diagram according to the design blueprint of the data center network;

Step 2: a physical map generation step, generating a physical map according to the actual physical topology;

Step 3: an error detection step, comparing the physical graph with the logical graph to find out whether there is a node that cannot normally perform address configuration in the physical graph relative to the logical graph; if it exists, go to step 4; if it does not exist, then Define the physical graph as a device graph, go to step 5;

Step 4: a device graph generation step, deleting the nodes that cannot be configured normally and their connected edges in the physical graph, and storing the remaining nodes in an adjacency matrix or adjacency list to generate a device graph;

Step 5: a matching step, matching the nodes in the device graph with the nodes in the logic graph, finding that each node in the device graph corresponds to a node in the logic graph;

Step 6: In the step of configuring addresses, find the nodes in the corresponding logic diagram for the nodes in the equipment diagram, and then set the addresses of the nodes in the equipment diagram according to the addresses marked in the logic diagram.

Step 1: Generate a logical diagram from the design blueprint, where the design blueprint is the connection relationship between physical machines defined before connecting the actual server and switch, and the design blueprint is stored in an adjacency matrix or adjacency list, which is recorded as a logical diagram; the node in the logical diagram is identified as server Or the network logical address corresponding to switch.

Step 2. The physical topology generates a physical graph. After the actual physical topology is connected, the actual physical topology connection relationship is obtained according to the physical topology collection protocol. This connection relationship is stored in an adjacency matrix or adjacency list, and is recorded as a physical graph; the node identification of the physical graph It is the physical address corresponding to sever or switch.

The realization of the physical topology collection protocol is to set up a communication channel on the actual physical network to collect the information of the physical topology, set a controller to build a spanning tree, and the physical topology information of all nodes will be generated by the leaves of the spanning tree Nodes pass up the spanning tree sequentially through the communication channel until the root node.

Step 3 is specifically performed as follows: Step 3.1: first select a part of nodes in the physical graph, and then calculate the absolute value of the SPLD difference between it and all nodes in the logical graph for each of these selected nodes, and convert the logical The point with the smallest absolute value of SPLD difference in the graph and the node in this physical graph is recorded as a node pair, and the SPLD of a node is the shortest distance from this node to all other nodes in the graph; step 3.2: for the nodes described in step 3.1 Yes, in the physical graph and the logical graph, start from all nodes that are 1 hop away from these two points, and verify whether all these nodes are isomorphic, until they are x hops away from these two points, these points are isomorphic, and When these points are not homogeneous when they are x+1 hops away, add one to their counter values for these nodes of x+1 hops; Step 3.3: After finishing the detection of all test nodes, press The counter values are arranged in descending order. The larger the counter value, the greater the probability of error. For the administrator of the data center, check whether there is a connection error from the node with a large counter value.

The nodes that cannot normally perform address matching in step 3 are caused by hardware reasons or connection errors.

Step 5 is specifically executed according to the following steps. This step recursively divides the logic graph G1 and the device graph Gd into smaller sets until each point in Gd finds a matching point in G1, then returns successfully; or in The previous step finds that the matching is wrong, then backtracking, and then try to match with the next node in Gl along another direction; because the points in the logical graph Gl are generally more than the points in the device graph Gd (there is no The number of nodes in the two graphs is the same when the node is wrong), so in the matching process, use the empty set to correspond to the sets in Gd that cannot be matched in Gl, and the matching process ensures that the number of sets in Gd is equal to the number of sets in Gl number; when matching logic diagrams and equipment diagrams, it mainly includes two processes of decomposition and verification.

The decomposition process is to separate a point v from its set O in Gd into O\{v} and {v} each time, and keep other sets unchanged. Correspondingly, the set O corresponding to Gd set O in G1 A point u in the set O' is divided into O'\{u} and {u}. In the process, each pair of new single-element set {v} corresponds to {u}.

The process of verification is that after decomposing {v} and {u} each time, the verification process checks this split, and in Gd, each set is divided into {v} and {v} by the connection relationship with {v} } are connected and not connected; correspondingly, in Gl, each set is divided into two sets connected with {u} and not connected with {u}; for each new pair of single-element sets, It is necessary to judge whether it is corresponding, until no new single-element set appears, then return successfully, or return if a matching error is found.

The verification process adopts three kinds of accelerated search decision theorems: the first theorem is: for each new single-element set {v}∈Gd, {u}∈Gl, set f(v)=u, that is, the device graph The v node in the middle corresponds to the u node in the logic graph; for each single-set element vs connected to {v} in Gd, if and only if u is connected to the corresponding single-set element f(vs) in Gl, then match step by step Go on, the result must be correct; the second theorem is: for each new pair of single-element sets, {v}∈Gd, {u}∈Gl, the degree of {v} is greater than the degree of {u}; the third The theorem is: for each new pair of single-element sets, {v}∈Gd, {u}∈Gl, v divides each non-empty set O(i) in Gd into a part Oc(i) connected to v ) and the part Onc(i) not connected to v, u divides the non-empty set O'(i) corresponding to O(i) in Gl into the part Oc'(i) connected to u and the part not connected to u Part of Onc'(i), the following conditions should be met: |Oc(i)|≤|Oc'(i)|and|Onc(i)|≤|Onc'(i)|, where |O| The number of elements in O.

The beneficial effect of the present invention is that: the ETAC method has a good effect on the automatic and fast address configuration of the fault-tolerant data center.

Description of drawings

Figure 1 is a block diagram of the overall steps of the ETAC method.

Figure 2 is a specific example of the physical diagram of the actual wiring and the diagram of the equipment for the design blueprint.

FIG. 3 is an implementation process of the ETAC method used in the example shown in FIG. 2 . It includes the two main processes of decomposing and verifying and performing split operations with corresponding points.

Figure 4 shows the relationship between the execution time of the algorithm and the size of the data center when the ETAC method is used in four classic data center network structures and the number of error nodes is controlled at 50.

Figure 5 shows the relationship between the number of error points and the execution time of the ETAC method for four different data center network structures at a fixed scale.

Figure 6 shows the execution time of the ETAC method for a fixed-scale BCube structure and Dcell structure when the server and switch are wrong in a certain proportion for the Bcube structure and Dcell structure of the data center network.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is an overall block diagram of address configuration for a data center network by the ETAC method. It contains step 1: design blueprint to generate logic diagram; step 2: physical topology to generate physical diagram; step 3 to detect errors; step 4 to generate device diagram; step 5 to match device diagram with logic diagram; step 6 to configure device diagram address.

Step 1 Design the blueprint to generate a logic diagram. The design blueprint is the connection relationship of physical machines defined before connecting the actual server and switch. The design blueprint can be stored in an adjacency matrix or adjacency list, which is recorded as a logic diagram.

Step 2. Physical topology generates a physical map. After the actual physical topology is connected, according to the physical topology collection protocol (Physical topology Collection Protocol, PCP), the connection relationship of the actual physical topology can be obtained. This connection relationship graph can be stored in an adjacency matrix or adjacency list, which is recorded as a physical graph.

The realization of the physical topology collection protocol is to establish a communication channel on the actual physical network to collect the information of the physical topology. For all the physical topology information, there is an ETAC manager to build a spanning tree, and all the physical topology information will be generated by The leaf nodes of the tree are passed up one by one until the root node ETAC manager.

Step 3 error detection, it is carried out according to the following steps:

Step 3.1: When there are wiring errors in the actual physical topology of the data center, the ETAC method can first select the two graphs according to the shortest path length distribution (SPLD) of some nodes in the logical graph and the physical graph A part of the nodes with the same SPLD is used as a test node set, and the SPLD of a node is the distance from this node to all other nodes in the graph;

Step 32: Compare in the logical graph and the physical graph. For each pair of corresponding test nodes, calculate when they are x hops away from them. At this time, the two graphs have the largest identical subgraph isomorphism. When the number of hops is 1, the two graphs have the same maximum sub-graphs and different structures, then for these nodes with x+1 hops, add one to their counter value;

Step 3.3: After finishing the detection of all test nodes, arrange the nodes with counter value in descending order according to the counter value. The larger the counter value, the greater the error probability; Start to detect whether there is a connection error.

In step 4, the device map generation is to delete the nodes in the actual physical connection map that cannot normally perform address configuration due to hardware reasons or connection errors after the error detection in step 3, and delete them from the physical map. Nodes are stored in an adjacency matrix or adjacency list, which is recorded as a device graph.

Step 5: The equipment graph and logical graph matching step is to match the corresponding nodes between the equipment graph and the logical graph. This step recursively divides the logical graph G1 and the device graph Gd into smaller sets until each point in Gd is in If a matching point is found in Gl, it will return successfully; or if it finds a matching error in the previous step, it will backtrack, and then try to match the next node in Gl along another direction; because the point in the logic graph Gl Generally, there will be more points in the device graph Gd (the number of nodes in the two graphs is the same when there are no error nodes in the physical graph), so in the matching process, the empty set is used to correspond to those sets in Gd that do not correspond to the sets in Gl , the matching process ensures that the number of sets in Gd is equal to the number of sets in Gl; when matching logic diagrams and equipment diagrams, it mainly includes two processes of decomposition and refinement.

The pseudocode of the matching steps between the equipment diagram and the logic diagram is as follows:

Figure 2 is an example of a logical diagram, a physical diagram and a device diagram. The design blueprint defines the connection relationship between server and switch, and gives a logical address to each server and switch. Part (a) in Figure 2 is the design blueprint with 8 nodes; part (b) is the actual physical connection diagram, which can be collected through the Physical topologyCollection Protocol, PCP protocol. Part (b) lacks an actual physical connection line between nodes 7 and 8; part (c) is the device diagram formed after removing nodes 7 and 8 with connection errors.

Figure 3 is a small example of an algorithm in the process of isomorphic correspondence between logic diagrams and equipment diagrams in the ETAC method. Among them, the solid line arrow represents the decomposition operation, the dotted line arrow represents the refinement operation, and P1 to P8 are a series of processes. For Gd and Gl, the ETAC method first divides Gd into {1, 2, 3}, {4, 5, 6} according to the difference between server and switch; divides Gl into {A, B, C, D}, { E, F, G, H}. In the process of P1, the ETAC method first selects 2 nodes in Gd and A nodes in Gl for decomposition operation, and now the set becomes {2}, {1, 3}, {4, 5, 6} and set {A} , {B, C, D}, {E, F, G, H}. In the process of refinement, because in Gd, nodes 3 and 4 are connected to 2, which belong to the sets {1, 3} and {4, 5, 6} respectively. The E and G nodes connected to A belong to the set {E, F, G, H}. According to the acceleration strategy of the third judgment search, backtracking should be performed. Then perform decomposition operation on 2 and C in the other direction, divide the set into {2}, {1, 3}, {4, 5, 6} and set {C}, {A, B, D}, {E , F, G, H}. According to 2 is connected with 3, 4, C is connected with D, E, F, the set can be divided into {2}, {3}, {1}, {4}, {5, 6} and {C}, {D} , {A, B}, {E, F}, {G, H}, a new single-element set pair 3-->D appears in P4, and then other sets are divided according to the connection relationship, and the set remains unchanged. In the process of P6 , 5 and G are decomposed, enter the P7 process, use theorem to check the correctness of two new pairs of single element sets: 5-->G, 6-->H, the result is correct, and then divide Operation, G divides {A, B} into {A}, {B}, correspondingly, 5 divides {1} into {1} and {}, so as to keep the number of Gd and Gl sets the same, in the process of P8, use The new single-element set pair 1-->A divides other non-empty sets to get the final result. In this way, the corresponding relationship between the design blueprint and the device diagram is obtained, so that the addresses corresponding to the nodes in the design blueprint are automatically and quickly configured for the nodes in the device diagram.

The decomposition process described in Figure 3 is to separate a point v from the set O in Gd where it is located into O\{v} and {v} each time, and the other sets remain unchanged. Correspondingly, a point u in the set O’ corresponding to the set O of Gd in Gl is divided into O’\{u} and {u}. In this process, we say that each new single-element set {v} corresponds to {u}.

The refinement process described in Figure 3 is a test of the split after each decomposition to produce {v}, {u}. In the subgraph Gd, each set is divided into two sets connected with {v} and not connected with {v} by the connection relationship with {v}. In the design blueprint Blueprint Gl, each set is divided into two sets connected with {u} and not connected with {u} by the connection relationship with {u}. For each new pair of single-element sets, it is judged whether it is corresponding, until no new single-element set appears, it returns successfully, or returns if a matching error is found.

In the process of matching the points in graphs Gl and Gd in the ETAC method, since the points in the design blueprint Gl are generally more than the points in the equipment graph Gd, in the process of cutting and matching, the ETAC method will use empty The set corresponds to the set in Gd that does not correspond to Gl.

The ETAC method cuts all non-empty small sets A(i) until each small set becomes a single single-element set cell, and each non-empty single-element set corresponds to a single-element set in Gl, so the ETAC method is The matching of the graphs G1 and Gd is realized, so as to match the addresses.

In the device graph, since the selection of node {v} has a great influence on the efficiency of the algorithm, ETAC proposed three theorems to greatly improve the search efficiency of the algorithm on the premise of ensuring the correctness of the algorithm matching.

The first theorem is: for each new single-element set {v}∈Gd, {u}∈Gl, set f(v)=u (that is, the v node in the device diagram corresponds to the u node in the design blueprint blueprint) . For each single-set element vs connected to {v} in Gd, if and only if u is connected to the corresponding single-set element f(vs) in Gl, then the matching will be carried out step by step, and the result must be correct.

The second theorem is: for each new pair of single-element sets, {v}∈Gd, {u}∈Gl, the degree of {v} is greater than the degree of {u};

The third theorem is: For each new pair of single-element sets, {v}∈Gd, {u}∈Gl, v divides each non-empty set O(i) in Gd into parts connected to v Oc(i) and the part Onc(i) not connected to v, u divides the non-empty set O'(i) corresponding to O(i) in Gl into the part Oc'(i) connected to u and the part connected to u Onc'(i), which is not connected to u, should satisfy the following conditions: |Oc(i)|≤|Oc'(i)|and|Onc(i)|≤|Onc'(i)|, where |O |Indicates the number of elements in the set O.

The ETAC method for address automatic configuration in the fault-tolerant data center is also applicable to the situation that no faulty node is found after the fault detection step is performed. At this time, the device diagram and the physical diagram are the same diagram.

This method proposes an automatic address matching method for a fault-tolerant data center. In the case of an error in the actual physical topology connection, remove those wrongly connected nodes and edges, and quickly match the remaining correct nodes. applied in the data center. The test results show that for all data center topologies, the ETAC method can complete the automatic and fast matching of data center addresses in about 1 minute.

Experimental verification

In order to verify that the ETAC method is fast and effective for fault-tolerant data center address configuration, the switch-centric data center Fattree and VL2 structures are designed, and the address configuration of faulty nodes distributed between different layers is designed. In the experiment, Fattree(60)=58500 nodes and VL2(20,100)=52650 nodes are used for experimental verification. The experiment fixed 50 error nodes between adjacent two layers, and repeated the experiment 100 times. The matching time is as follows:

Layer Fattree(60) VL2(20, 100) Tl Ta Tu Tl Ta Tu 1-2 17.36 17.40 17.49 12.51 12.55 12.60 2-3 16.91 17.03 17.15 12.07 12.10 12.14

3-4 17.30 17.37 17.57 12.24 12.43 12.62

Among them, layers 1-2 represent the server-edge layers in Fattree and VL2, layers 2-3 represent the edge-aggregation layers in Fattree and VL2, and layers 3-4 represent the aggregation-core layers in Fattree and VL2. Tl, Ta, Tu represent the shortest matching time, the average matching time and the longest matching time, respectively.

In the experiment, BCube and DCell are also designed for the server-centric data center network structure. Analyze the relationship between different proportions of switch errors and address matching time. In the experiment, the number of fixed error nodes is also 50, and BCube(8,4)=52650 and DCell(3,3)=32656 nodes are used. , repeat the experiment 100 times. In the experiment, the proportion of wrong switch is changed from 0%, 20%, 40%, 60%, 80%, 100%. That is, the number of wrong switches is 0, 10, 20, 30, 40, 50. The address matching time is shown in Figure 6.

It can be seen from the above table and Figure 6 that neither the position nor the proportion of the error node can affect the rapid configuration of the fault-tolerant data center network address by the ETAC method.

Example 1

For the data center network, the number of error nodes is fixed at 50. Different data center network structures BCube, Dcell, fattree and VL2, when the scale of the data center changes from small to large, the ETAC method is suitable for this kind of fault-tolerant data center network address configuration. The relationship between the execution time of (the address configuration fails if the execution time exceeds a certain set value) and the size of the data center. In this embodiment, the ETAC method randomly generates 50 error nodes for each occurrence, and for each data center network structure and under the same structure, different node sizes are simulated 100 times. .

In this embodiment, the scales of the BCube structure are respectively: BCube(5,4)=6250, BCube(6,4)=14256, BCube(7,4)=18812 and BCube(8,4)=53248; Fattree The scales of the structure are respectively: Fattree(20)=2500, Fattree(40)=18000, Fattree(60)=58500 and Fattree(80)=136000; the scales of the VL2 structure are respectively: VL2(10,100)=27650 , VL2(20,100)=52650, VL2(40,100)=102650 and VL2(60,100)=152650; the scale of Dcell structure is respectively: Dcell(4,2)=525, Dcell(2,3) =2709, Dcell(3,3)=32656 and Dcell(4,3)=221025.

For the four different topologies in this embodiment and the node scales of different data centers under different topologies, the ETAC method can automatically and quickly configure the address of this fault-tolerant data center network in a relatively short period of time. Figure 4 shows the relationship between the average execution time of the ETAC method and the size of the data center under four different data center structures. Under the four structures of the data center, the ETAC method can realize the correct matching of addresses in about 1 minute. The four curves show that the execution time of the ETAC method increases with the size of the data center when the number of error nodes is fixed at 50 and the error nodes are distributed randomly in the data center.

In this embodiment, the maximum storage space required for address configuration is: Fattree requires 27.2MB, VL2 requires 26.4MB, BCube requires 7.6MB, and Dcell requires 24.4MB.

Example 2

For the data center network, there are four different data center network structures. When choosing a fixed size node number for each structure of the network. And change the number of wrong nodes in order from small to large, and observe whether the ETAC method can quickly and automatically configure the address of this fault-tolerant data center network. The number of wrong nodes is 10, 20, 30, 40, 50 in sequence. Nodes are randomly generated in the data center. Moreover, 100 simulations were repeated for the network structure of each data center and the same node size under the same structure.

In the experiment, the scale of BCube is selected as BCube(8,4)=53248, the scale of Fattree is Fattree(60)=58500, the scale of Dcell is Dcell(3,3)=32656, and the scale of VL2 is VL2(20, 100) = 52650.

In this experiment, when the number of error nodes is 10, 20, 30, 40, and 50, the address configuration time of ETAC method for Fattree structure is about 12s, and the address configuration time of VL2 structure is about 17s. The configuration time for BCube is 41.60s to 72.96s, with an average time of 46.67s. The configuration time of DCell is 2.33s to 5.17s, and the average time is 3.57s.

The experimental results show that the ETAC method can automatically and quickly configure the address of this fault-tolerant data center network in a short period of time. Figure 5 shows the relationship between the average execution time of the ETAC method and the number of error nodes under four different data center structures.

In this embodiment, the maximum storage space required for address configuration is: Fattree requires 12.6MB, VL2 requires 10.1MB, BCube requires 7.6MB, and Dcell requires 3.8MB.

Claims (10)

1. An address automatic configuration method of a fault-tolerant data center network, the method sets correct network logic addresses for each sever and switch of the data center, it is characterized in that it comprises the following steps: Step 1: a logic diagram generation step, generating a logic diagram according to the design blueprint of the data center network; Step 2: a physical map generation step, generating a physical map according to the actual physical topology; Step 3: an error detection step, comparing the physical graph with the logical graph to find out whether there is a node that cannot normally perform address configuration in the physical graph relative to the logical graph; if it exists, go to step 4; if it does not exist, then Define the physical graph as a device graph, go to step 5; Step 4: a device graph generation step, deleting the nodes that cannot be configured normally and their connected edges in the physical graph, and storing the remaining nodes in an adjacency matrix or adjacency list to generate a device graph; Step 5: a matching step, matching the nodes in the device graph with the nodes in the logic graph, finding that each node in the device graph corresponds to a node in the logic graph; Step 6: In the step of configuring addresses, find the corresponding node in the logic diagram for the node in the equipment diagram, and then set the address of the node in the equipment diagram according to the address marked in the logic diagram. 2. method according to claim 1, it is characterized in that: step 1 design blueprint generates logic diagram, wherein, design blueprint is the connection relation of the physical machine defined before connecting actual server and switch, and design blueprint presses adjacency matrix or The adjacency list storage is recorded as a logical graph; the node identifier of the logical graph is the network logical address corresponding to sever or switch. 3. The method according to claim 1, characterized in that: step 2 physical topology generates a physical map, after the actual physical topology is connected, according to the physical topology collection protocol, the actual physical topology connection relationship is obtained, and this connection relationship is by adjacency The matrix or adjacency list storage is recorded as a physical graph; the node identifier of the physical graph is the physical address corresponding to sever or switch. 4. The method according to claim 3, characterized in that: the realization of the physical topology collection protocol is to set up a communication channel on the actual physical network to collect the information of the physical topology, and a controller is set to set up a In a spanning tree, the physical topology information of all nodes will be passed up from the leaf nodes of the spanning tree through the communication channel to the root node. 5. The method according to claim 1, characterized in that: step 3 is specifically performed according to the following steps: Step 3.1: First select some nodes in the physical graph, and then calculate the absolute value of the SPLD difference between it and all nodes in the logical graph for each of these selected nodes, and minimize the absolute value of the SPLD difference in the logical graph The point and the node in this physical graph are recorded as a node pair, and the SPLD of a node is the shortest distance from this node to all other nodes in the graph; Step 32: For the node pair described in step 3.1, start from all nodes that are 1 hop away from these two points in the physical graph and logical graph, and verify whether all these nodes are isomorphic until the distance between these two points When x hops, these points are isomorphic, but when they are x+1 hops apart, these points are not homogeneous, then for these x+1 hop nodes, add one to their counter value; Step 3.3: After finishing the detection of all test nodes, arrange the nodes with counter value in descending order of counter value, the larger the counter value, the greater the probability of error; for the administrator of the data center, start from the node with large counter value Start checking for wiring errors. 6. The method according to claim 1, characterized in that: the node that cannot normally perform address matching in step 3 is due to hardware reasons or connection errors. 7. The method according to claim 1, characterized in that: step 5 is specifically executed according to the following steps, the step recursively divides the logical graph G1 and the device graph Gd into smaller sets, until each point in Gd is in If a matching point is found in Gl, it will return successfully; or if it finds a matching error in the previous step, it will backtrack, and then try to match the next node in Gl along another direction; because the point in the logic graph Gl Generally, there will be more points in the device graph Gd (the number of nodes in the two graphs is the same when there are no error nodes in the physical graph), so in the matching process, the empty set is used to correspond to those sets in Gd that do not correspond to the sets in Gl , the matching process ensures that the number of sets in Gd is equal to the number of sets in Gl; when matching logic diagrams and equipment diagrams, it mainly includes two processes of decomposition and verification. 8. method according to claim 7, it is characterized in that: described decomposing process is, every time a point v is separated into O\{v} and {v} by the set O in its place Gd, other sets keep Correspondingly, divide a point u in the set O' corresponding to the Gd set O in Gl, and divide it into O'\{u} and {u}. In the process, each pair of newly appeared The single-element set {v} corresponds to {u}. 9. method according to claim 7, it is characterized in that: the process of described verification is, carry out decomposing {v} at every turn, after {u}, verification process checks this division, in Gd each A set is divided into two sets connected with {v} and not connected with {v} by the connection relationship with {v}; correspondingly in G1, each set is divided into two sets connected with {u} and not connected with {u} by the connection relationship with {u} Connect two collections; for each new pair of single-element collections, make a corresponding judgment until no new single-element collection appears, then return successfully, or return if a matching error is found. 10. The method according to claim 9, characterized in that: the verification process adopts three kinds of accelerated search decision theorems: The first theorem is: for each new single-element set {v}∈Gd, {u}∈Gl, set f(v)=u, that is, node v in the device graph corresponds to node u in the logic graph; {v} is connected to each single-set element vs in Gd, if and only if u is connected to the corresponding single-set element f(vs) in Gl, then the matching will be carried out step by step, and the result must be correct; The second theorem is: for each new pair of single-element sets, {v}∈Gd, {u}∈Gl, the degree of {v} is greater than the degree of {u}; The third theorem is: For each new pair of single-element sets, {v}∈Gd, {u}∈Gl, v divides each non-empty set O(i) in Gd into parts connected to v Oc(i) and the part Onc(i) not connected to v, u divides the non-empty set O'(i) corresponding to O(i) in Gl into the part Oc'(i) connected to u and the part connected to u The disjoint part Onc'(i) of u should satisfy the following conditions: |Oc(i)≤|Oc'(i)|and|Onc(i)|≤|Onc'(i)|, where |O| Indicates the number of elements in the set O.

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