CN102546401B - Universal serial bus (USB) 3.0 local area network top speed data switchboard - Google Patents
Universal serial bus (USB) 3.0 local area network top speed data switchboard Download PDFInfo
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Abstract
The invention provides a universal serial bus (USB) 3.0 local area network top speed data switchboard, which comprises a plurality of USB 3.0 nodes, a USB 3.0 node configuration storage, a switchboard intercommunication bus, a link configuration bus and a USB 3.0 link controller, wherein the switchboard configures special data exchange buses for all the USB 3.0 nodes. Compared with the prior art, the USB 3.0 local area network top speed data switchboard has the advantages of: (1) being so fast in transmission that the transmission speed of any one node can reach 3.2 Gb/s and no more than 3 seconds are needed for transmitting 1 GB data of a computer to another computer through the switchboard, (2) being strong in expandability, (3) having data error processing operation and being stable and reliable in data transmission, (4) being especially suitable for frequent data exchange inside a system composed of a plurality of computers, (5) being convenient to connect and supporting hot plug-pull and (6) being convenient to carry.
Description
Technical field
The present invention relates to a kind of data communication field, the data communication technology field of particularly communicating by letter between many computers, specifically refers to the very fast data switching exchane of USB3.0 local area network (LAN).
Background technology
USB is a kind of interfacing that is applied in computer realm, has the advantages such as hot plug, portable, transmission speed is fast.Due to the various advantages of USB, various operating system is all supported this interfacing as windows series, linux are serial, and this makes the application of USB technology more extensive.Along with the development of USB technology and perfect, USB transmission speed is more and more faster, and the bit rate of USB3.0 has reached 5Gbps especially.
Exchanges data between computer is mainly to complete by router, switch and two-shipper the Internet line at present, and its exchanges data speed is all below 10MB/s.Under general case, the exchanges data speed between the two computers connecting by router is often less than 500KB/S.In the system forming at multicomputer, frequent data exchange, data traffic is large, and existing exchanges data speed will become technical bottleneck.
Summary of the invention
For the demand, technical problem to be solved by this invention is to provide a kind ofly can realize USB3.0 limit transmission speed, improve many computer data exchange efficiencies, convenient and practical, the reliable and stable very fast data switching exchane of USB3.0 local area network (LAN).
For this reason, the present invention is by the following technical solutions:
The very fast data switching exchane of a kind of USB3.0 local area network (LAN), it is characterized in that: comprise a plurality of USB3.0 nodes, USB3.0 node config memory, switch internal communication bus, link configuration bus, USB3.0 link controller, described switch is the exchanges data bus of each USB3.0 node configure dedicated;
Described USB3.0 link controller is built and is removed for the communication link between each USB3.0 node of data switching exchane;
Described exchanges data bus is connected to the corresponding input and output pin of described USB3.0 link controller for the USB3.0 node that it is attached troops to a unit;
USB3.0 peripheral control unit is sent in real time building of communication link and removes instruction to USB3.0 link controller by described link configuration bus;
Described USB3.0 node config memory is for memory node configuration information;
Described USB3.0 node comprises USB3.0 interface and USB3.0 peripheral control unit, and USB3.0 interface is connected with USB3.0 peripheral control unit; Described USB3.0 peripheral control unit comprises USB3.0 end points, data buffer area, USB3.0PHY engine, USB3.0 microcontroller kernel, switch intercommunication controller and link configuration controller; Described USB3.0PHY engine is USB3.0 interface data transmitter/receiver circuit; Described USB3.0 microcontroller kernel is that USB3.0 peripheral control unit inside is for the treatment of the CPU processor of computing; Described switch intercommunication controller is for controlling the control data transmission in described switch internal communication bus; Described link configuration controller is for controlling building and the real-time transmission of removing instruction of communication link in described link configuration bus; Described USB3.0 end points is divided into that USB3.0 sends end points in real time and USB3.0 receives end points in real time; Described data buffer area is for depositing the data of carrying out exchanges data with other USB3.0 node of data switching exchane; Described data buffer area is divided into real-time transmission data buffer area and receives in real time data buffer area; Described real-time transmission data buffer area and described USB3.0 send in real time end points and form real time data sendaisle; Described real-time reception data buffer area and described USB3.0 receive in real time end points and form real time data receive path; Through USB3.0 peripheral control unit described in described real time data receive path initiate with this USB3.0 peripheral control unit under the data receiver of the computer that is connected of node; Through USB3.0 peripheral control unit described in described real time data sendaisle initiate with this USB3.0 peripheral control unit under the computer that is connected of node data from end points to the USB3.0 in this real time data sendaisle that send in real time send; When the real-time receiving terminal point of USB3.0 receive that real-time reception data buffer area transmits data length reach after a data packet length, USB3.0 peripheral control unit just initiates to receive in real time end points to the transfer of data of the connected computer of node under this USB3.0 peripheral control unit by described USB3.0 immediately; When USB3.0 sends data that end points sends a data packet length in real time to sending in real time behind data buffer area, USB3.0 peripheral control unit is just initiated immediately the affiliated connected computer of node of this USB3.0 peripheral control unit and to USB3.0, is sent in real time the transfer of data of end points, can guarantee thus the real-time Transmission of data;
Switch intercommunication controller in each USB3.0 peripheral control unit forms switch internal communication network together with being interconnected at by described switch internal communication bus with USB3.0 node config memory, realizes the transmission of controlling data.
Adopting on the basis of technique scheme, the present invention also can be by the following technical solutions simultaneously:
Described USB3.0 node also comprises bus converter, described bus converter is positioned in the exchanges data bus that USB3.0 peripheral control unit is connected with USB3.0 link controller, data/address bus between bus converter and USB3.0 peripheral control unit is wider than the data-bus width between bus converter and USB3.0 link controller, and the data/address bus transmission frequency in the data/address bus transfer of data frequency ratio between bus converter and USB3.0 peripheral control unit between bus converter and USB3.0 link controller is low.
The described very fast data switching exchane of USB3.0 local area network (LAN) also comprises USB3.0 gateway, and described USB3.0 gateway is realized the communication between switch and other networks.
USB3.0 end points in described USB3.0 peripheral control unit receives in real time end points and also divides and have non real-time USB3.0 end points except USB3.0 sends end points and USB3.0 in real time, data buffer area in described USB3.0 peripheral control unit is except sending in real time data buffer area and receiving data buffer area and also divide and have non-real-time data buffer area in real time, described non real-time USB3.0 end points and non-real-time data buffer area form non-real-time data interchange channel, the connected computer of node under described USB3.0 peripheral control unit is initiated the exchanges data with described non-real-time data interchange channel.
Described USB3.0 node config memory is EEPROM; Described link configuration bus is spi bus; Described switch internal communication bus is I
2c bus; Described USB3.0 link controller is fpga chip.
Described bus converter is bus switch chip; Exchanges data highway width between described bus switch chip and described USB3.0 peripheral control unit is 32, exchanges data frequency is for being 100MHZ, exchanges data highway width between described bus switch chip and described USB3.0 link controller is 16, and exchanges data frequency is 200MHZ.
Described USB3.0 node config memory is AT24C64 chip; Described USB3.0 peripheral control unit is CYUSB3014 chip.
Described bus switch chip is SN74ALVCHG162282 chip.
Owing to adopting technical scheme of the present invention, compared with prior art, it has the following advantages in the present invention:
1), transmission speed is fast, any one node data transmission speed can reach 3.2Gb/s, the data of a computer 1GB will be transferred on another computer by this switch, only need be less than 3 seconds;
2), extensibility is strong;
3), have error in data to process operation, transfer of data is reliable and stable;
4), be particularly suitable for the internal system that formed by many computers exchanges data frequently;
5), easy to connect, support hot plug;
6), easy to carry.
Accompanying drawing explanation
Fig. 1 is embodiment of the present invention application schematic diagram;
Fig. 2 is embodiment of the present invention exchanges data schematic diagram;
Fig. 3 is the structural representation of the embodiment of the present invention;
Fig. 4 is the structural representation of USB3.0 peripheral control unit in the present invention;
Fig. 5 is the circuit theory diagrams of node 1 of the present invention;
Fig. 6 is the internal structure schematic diagram of CYUSB3014;
Fig. 7 is the structural representation of bus switch chip;
Fig. 8 is the connection diagram of FPGA;
Fig. 9 is exchanges data control command code table;
Figure 10 is computer 1 and computer 2 data exchange operation flow charts;
Figure 11 is that the present embodiment Computer 1 and computer 2 error in data are processed operational flowchart.
Embodiment
In order more clearly to understand technology contents of the present invention, especially exemplified by following examples, describe in detail.
Please refer to Fig. 1, is embodiment of the present invention application schematic diagram.Many computers are connected on the very fast data switching exchane of USB3.0 local area network (LAN) by USB3.0 bus, have other network interfaces as RJ-45 on switch, by this interface, are connected with other networks.Be connected between the computer on switch swap data arbitrarily, the exchanges data speed on each computer reaches as high as 3.2Gb/s, that is to say that the data of 1GB on any computer just can pass on an other computer within 3 seconds.
Please refer to Fig. 2, it is embodiment of the present invention exchanges data schematic diagram, application program on a computer is opened up a plurality of real time datas and is sent, a plurality of real time datas receive and a plurality of non-real-time data exchange buffering, by a plurality of pipelines, send in real time end points with a plurality of USB3.0 in the connect USB3.0 peripheral control unit of USB3.0 node respectively, a plurality of USB3.0 receive end points and the non real-time end points swap data of a plurality of USB3.0 in real time, a plurality of USB3.0 of the link that the USB3.0 peripheral control unit of a USB3.0 node is put up by USB3.0 link controller again and the USB3.0 peripheral control unit of another USB3.0 node send end points in real time, a plurality of USB3.0 receive end points and the non real-time end points swap data of a plurality of USB3.0 in real time, a plurality of real time datas of opening up that the USB3.0 peripheral control unit of this another USB3.0 node is opened up with the application program in the computer being connected by a plurality of pipelines again send, a plurality of real time datas receive and a plurality of non-real-time data exchange buffering is realized exchanges data.
Please refer to Fig. 3, at the very fast data switching exchane of the USB3.0 of embodiment of the present invention local area network (LAN), mainly comprise a plurality of USB3.0 nodes, a node config memory, switch internal communication bus, link configuration bus, a USB3.0 link controller, a USB3.0 gateway, switch is the exchanges data bus of each USB3.0 node configure dedicated.USB3.0 link controller is built and is removed for the communication link between each USB3.0 node of data switching exchane.Exchanges data bus is connected to the corresponding input and output pin of described USB3.0 link controller for the USB3.0 node that it is attached troops to a unit.USB3.0 node config memory is for memory node configuration information.USB3.0 gateway is realized the communication between switch and other networks.
A USB3.0 node comprises a USB3.0 interface, a USB3.0 peripheral control unit and a bus converter.USB3.0 interface is connected by USB3.0 bus with USB3.0 peripheral control unit, between USB3.0 peripheral control unit and bus converter, be connected with exchanges data bus, bus converter is connected to a node on USB3.0 link controller by exchanges data bus again.Bus converter is positioned in the exchanges data bus that USB3.0 peripheral control unit is connected with USB3.0 link controller, data/address bus between bus converter and USB3.0 peripheral control unit is wider than the data-bus width between bus converter and USB3.0 link controller, and the data/address bus transmission frequency in the data/address bus transfer of data frequency ratio between bus converter and USB3.0 peripheral control unit between bus converter and USB3.0 link controller is low.
Each USB3.0 peripheral control unit forms switch internal communication network together with being interconnected at by switch internal communication bus with USB3.0 node config memory, realizes the transmission of controlling data.USB3.0 peripheral control unit in figure is by being connected to the link configuration bus on USB3.0 link controller, and the communication link of building and removing between each USB3.0 node of instruction control data switching exchane that sends communication link is built and removed.
Please refer to Fig. 4, is the structural representation of USB3.0 peripheral control unit in the present invention.This USB3.0 peripheral control unit comprises USB3.0 end points, data buffer area, USB3.0PHY engine, USB3.0 microcontroller kernel, switch intercommunication controller and link configuration controller; USB3.0PHY engine is USB3.0 interface data transmitter/receiver circuit; USB3.0 microcontroller kernel is that USB3.0 peripheral control unit inside is for the treatment of the CPU processor of computing; Switch intercommunication controller is for controlling the control data transmission in described switch internal communication bus; Link configuration controller is for controlling building and the real-time transmission of removing instruction of communication link in described link configuration bus; USB3.0 end points includes USB3.0 and sends in real time end points, USB3.0 and receive in real time end points and non real-time USB3.0 end points; Data buffer area is for depositing the data of carrying out exchanges data with other USB3.0 node of data switching exchane; Data buffer area includes real-time transmission data buffer area, receives data buffer area and non-real-time data buffer area in real time; Send in real time data buffer area and USB3.0 and send in real time end points formation real time data sendaisle; Receive in real time data buffer area and USB3.0 and receive in real time end points formation real time data receive path; Through real time data receive path, USB3.0 peripheral control unit initiate with this USB3.0 peripheral control unit under the data receiver of the computer that is connected of USB3.0 node; Through real time data sendaisle, USB3.0 peripheral control unit initiate with this USB3.0 peripheral control unit under the computer that is connected of USB3.0 node data from end points to the USB3.0 in this real time data sendaisle that send in real time send; When the real-time receiving terminal point of USB3.0, receive the data length that real-time reception data buffer area is transmitted and reach after a data packet length, USB3.0 peripheral control unit just initiates to receive in real time end points to the transfer of data of the connected computer of USB3.0 node under this USB3.0 peripheral control unit by described USB3.0 immediately; When USB3.0 sends data that end points sends a data packet length in real time to sending in real time behind data buffer area, USB3.0 peripheral control unit is just initiated immediately the affiliated connected computer of USB3.0 node of this USB3.0 peripheral control unit and to the USB3.0 in this real time data sendaisle, is sent in real time the transfer of data of end points, can guarantee thus the real-time Transmission of data; Non real-time USB3.0 end points and non-real-time data buffer area form non-real-time data interchange channel, and the connected computer of node under USB3.0 peripheral control unit is initiated the exchanges data with non-real-time data interchange channel.
According to USB3.0 agreement, real time data is transmitted and limited bandwidth, can not give the transmission of being initiated by USB3.0 peripheral control unit by whole allocated bandwidth.Therefore marked off in the present embodiment non-real-time data interchange channel, for developing to greatest extent USB3.0 bandwidth.
In actual applications, USB3.0 node receives the data that send out from connected computer, the data decode of USB3.0 form will be there is, then decoded data are sent to data reception node by the communication link of putting up, data reception node is dressed up packet USB3.0 form again, send on recipient's computer, thereby realized the exchange of data.
In actual applications, if USB3.0 bandwidth, all for exchanges data, because USB3.0 data signal bandwidth is 5Gb/s, is removed coding redundancy, actual data signal bandwidth can reach 4Gb/s, and any data link data throughput in the present invention is up to 3.2Gb/s.
In native system embodiment, USB3.0 node config memory adopts eeprom chip AT24C64; USB3.0 peripheral control unit adopts CYUSB3014 chip; USB3.0 link controller adopts fpga chip; Bus converter adopts bus switch chip SN74ALVCHG162282.Link configuration bus adopts spi bus, and switch internal communication bus adopts I
2c bus.
Please refer to Fig. 5, is the circuit theory diagrams of node.In figure, CYUSB3014 is USB3.0 peripheral control unit, this integrated chip SPI controller, I
2c controller.SPI controller is link configuration controller, I in the present embodiment
2c controller is switch intercommunication controller, and spi bus is link configuration bus, I
2c bus is switch internal communication bus.CYUSB3014 passes through I
2c bus and other nodes and node config memory form internal communication network, realize the transmission of controlling data; CYUSB3014 configures in real time FPGA by spi bus and realizes building and removing of link.
Please refer to Fig. 6, is the internal structure schematic diagram of CYUSB3014.CYUSB3014 inner also integrated ARM926EJ, USB3.0PHY engine, USB3.0 end points and data buffer area.ARM926EJ is USB3.0 microcontroller kernel, USB3.0PHY engine is for USB3.0 data serial sending and receiving, the data of the storage of USB3.0 end points and the exchange of direct-connected computer, computer can directly read the data in USB3.0 end points by USB3.0 bus, and data buffer area is for depositing by the data of bus converter and link controller and other node switching.
Please refer to Fig. 7.Bus converter adopts bus switch chip, and SN74ALVCHG162282 chip is the bus switch chip using in the present embodiment.Exchanges data highway width between bus switch chip and USB3.0 peripheral control unit is twice than the exchanges data highway width between bus switch chip and USB3.0 link controller in the present embodiment, and the exchanges data bus data exchange frequency between bus switch chip and USB3.0 peripheral control unit is more half as large than described bus switch chip and the exchanges data bus data exchange frequency between USB3.0 link controller.
The B group bus that SN74ALVCHG162282 comprises 32, is divided into B1 and B2; SN74ALVCHG162282 also comprises the A group bus of 16, has a SEL to select signal pins, has a DIR direction to control pin, has an OE output enable pin.When DIR is high level, represent that A organizes bus and organizes bus transfer to B, a SEL is in the cycle, first rising edge of CLK is organized data by A and is latched into B2, second rising edge of CLK organized data by A and is latched into B1, data when SEL is low level in B group bus will be read, thereby realize the transfer of data of B group bus to A group bus.When DIR is low level, represent that B organizes bus and organizes bus transfer to A, when SEL is high level, the rising edge of CLK is latched into the data in B1 bus in A group bus, when SEL is low level, the rising edge of CLK is latched into the data in B2 bus in A group bus, thereby realized B group bus, to A, organizes bus transfer.SEL connects the read-write clock of USB3.0 peripheral control unit in actual applications, and CLK connects the read-write clock of link controller, the read-write clock on USB3.0 peripheral control unit is received in FPGA simultaneously, realizes synchronous in stationary phase of SEL signal and CLK signal.
In native system embodiment, adopt bus switch chip SN74ALVCHG162282, the exchanges data highway width between bus switch chip and USB3.0 peripheral control unit is 32, exchanges data frequency is 100MHZ; Exchanges data highway width between bus switch chip and USB3.0 link controller is 16, and exchanges data frequency is 200MHZ.By bus switch chip SN74ALVCHG162282, the exchanges data bus that makes to be connected on link controller has shortened half, can make the link controller of identical input/output interface quantity can connect more node.
Please refer to Fig. 8, it is the connection diagram of FPGA in the present embodiment, in figure, FPGA separates n group link and controls data/address bus, networking pass data/address bus and one group of spi bus, USB3.0 peripheral control unit 1 arranges the control bit of FPGA by spi bus, FPGA is according to the coding to control bit, realize internal communication and the disconnection of any two data/address buss, thereby realize building and removing of link.
Node config memory is articulated in I
2in C bus, for memory node allocation list, the form that the node configuration record that Computer I D, computer name, node address and the corresponding physical interface address that node allocation list is served as reasons on each node forms forms.
At this, introduce dynamic node address assignment and static node address assignment.Node address distributes, and is exactly that each node to switch distributes an address, for distinguishing different nodes, when computer will be with another computer swap data, just can by node address determine will with which platform computer swap data.
Dynamic node address assignment is exactly that switch is operated in dynamic node mode of operation.This mode of operation is dynamically the computer distribution node address of access node, and the assigned node address of the each access switch node of computer is not necessarily identical.When a node of a computer access switch, switch just obtains Computer I D and computer name, and as a node configuration record, adds Computer I D, computer name, node address and corresponding physical interface address to node allocation list.When computer disconnected node, switch is just deleted this node configuration record from node allocation list.
Static node address assignment is exactly that switch is operated in static node mode of operation.Under this mode of operation, the good static node address of computer installation, and download in switch, exchange opportunity checks existing node allocation list, if node address does not overlap with existing node address, switch adds Computer I D, computer name, node address and corresponding physical interface address to node allocation list as a node configuration record; If switch is found the node address downloading and is overlapped with existing address, the conflict of exchange opportunity prompting computer address, and require to reset node address.When computer disconnected node, switch is not deleted this node configuration record from node allocation list.When computer is next time during access switch, need not reset node address.During computer installation static node address, if computer has been connected to switch, computer can be checked distributable node address in switch.
Switch is when being used for the first time, and acquiescence works in dynamic node mode of operation.Can be revised by computer the mode of operation of switch afterwards.
Node allocation list is comprised of node configuration record, and each node configuration record is the map record one by one of physical interface address, node address, Computer I D and computer name.
Please refer to Fig. 9, is exchanges data control command code table in the present embodiment.The coding that exchanges data control command code is control operation used.
Please refer to Figure 10, is the present embodiment Computer 1 and computer 2 data exchange operation flow charts, at this operation Computer 1, is connected to U3 node, and computer 2 is connected to U4 node, and computer 1 sends data to computer 2.This data exchange operation comprises following steps:
1. between two of exchanges data computers, set up exchanges data affairs,
2. the very fast data switching exchane of USB3.0 local area network (LAN) is set up exchanges data link,
3. log-on data exchange,
4. the data that constantly transmission will exchange, until transmitted, if find error in data in exchanges data, the described error in data of application is processed operation,
5. end data exchange,
6. cancel exchanges data link,
1. end data exchanges affairs.
Please refer to Figure 11, is that the present embodiment Computer 1 and computer 2 error in data are processed operational flowchart, at this operation Computer 1, is connected to U3 node, and computer 2 is connected to U4 node, and computer 1 sends data to computer 2.This error in data is processed operation and is comprised following steps:
1. recipient's detecting host error block,
2. send misdata block number to transmit leg,
3. transmit leg resends the data of described misdata block number,
4. end data mistake is processed operation.
In actual data transmission procedure, owing to taking full advantage of USB3.0 bus bandwidth, transmission rate has reached 3.2Gb/s.On a computer, the data of 1GB pass on another computer and only needed for 3 seconds, and owing to having taked error in data retransmission mechanism, error rates of data is 0.
In this specification, the present invention describes with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore specification and accompanying drawing should be considered to illustrative but not determinate.
it is as follows that annotation write a Chinese character in simplified form in English in the present invention:
The English Universal Serial of USB BUS(USB) abbreviation
RJ-45 RJ-45 interface can be used for connecting RJ-45 connector, the network that is applicable to be built by twisted-pair feeder, and this port is modal, in general ethernet concentrator all can provide this port.
PHY refers to physical layer, the bottom of OSI.Refer generally to the chip with external signal interface.
EEPROM (Electrically Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memo)--the storage chip that after a kind of power down, data are not lost.
The eeprom chip that AT24C64 Atmel company produces.
The USB3.0 peripheral control unit that CYUSB3014 Cypress company produces.
FPGA Field-Programmable Gate Array), i.e. field programmable gate array.
The bus switch chip that SN74ALVCHG162282 TI company produces.
SPI Serial Peripheral Interface SPI(serial peripheral interface) bussing technique is a kind of synchronous serial interface that motorola inc releases.
I
2the twin wire universal serial bus of C Inter-Integrated Circuit bus Shi You PHILIPS company exploitation, for connecting microcontroller and ancillary equipment thereof.
ARM926EJ arm processor.
ARM (Advanced RISC Machines) is the low risc processor of large quantity high performance, cheapness, power consumption of the ARM company design of microprocessor industry.
The abbreviation of the English IDentity of ID, the meaning of identify label number, the identify label number of different computers in this article.
Claims (8)
1. the very fast data switching exchane of USB3.0 local area network (LAN), it is characterized in that: comprise a plurality of USB3.0 nodes, USB3.0 node config memory, switch internal communication bus, link configuration bus, USB3.0 link controller, described switch is the exchanges data bus of each USB3.0 node configure dedicated;
Described USB3.0 link controller is built and is removed for the communication link between each USB3.0 node of data switching exchane;
Described exchanges data bus is connected to the corresponding input and output pin of described USB3.0 link controller for the USB3.0 node that it is attached troops to a unit;
Described USB3.0 node comprises USB3.0 interface and USB3.0 peripheral control unit, and USB3.0 interface is connected with USB3.0 peripheral control unit;
Each USB3.0 peripheral control unit is sent in real time building of communication link and removes instruction to USB3.0 link controller by described link configuration bus;
Described USB3.0 peripheral control unit comprises USB3.0 end points, data buffer area, USB3.0PHY engine, USB3.0 microcontroller kernel, switch intercommunication controller and link configuration controller; Described USB3.0PHY engine is USB3.0 interface data transmitter/receiver circuit; Described USB3.0 microcontroller kernel is that USB3.0 peripheral control unit inside is for the treatment of the CPU processor of computing; Described switch intercommunication controller is for controlling the control data transmission in described switch internal communication bus; Described link configuration controller is for controlling building and the real-time transmission of removing instruction of communication link in described link configuration bus; Described USB3.0 end points includes that USB3.0 sends end points in real time and USB3.0 receives end points in real time; Described data buffer area is for depositing the data of carrying out exchanges data with other USB3.0 node of data switching exchane; Described data buffer area includes real-time transmission data buffer area and receives in real time data buffer area; Described real-time transmission data buffer area and described USB3.0 send in real time end points and form real time data sendaisle; Described real-time reception data buffer area and described USB3.0 receive in real time end points and form real time data receive path; Through described real time data receive path, described USB3.0 peripheral control unit initiate with this USB3.0 peripheral control unit under the data receiver of the computer that is connected of USB3.0 node; Through described real time data sendaisle, described USB3.0 peripheral control unit initiate with this USB3.0 peripheral control unit under the computer that is connected of USB3.0 node data from end points to the USB3.0 in this real time data sendaisle that send in real time send; When the real-time receiving terminal point of USB3.0, receive the data length that real-time reception data buffer area is transmitted and reach after a data packet length, USB3.0 peripheral control unit just initiates to receive in real time end points to the transfer of data of the connected computer of USB3.0 node under this USB3.0 peripheral control unit by described USB3.0 immediately; When USB3.0 sends data that end points sends a data packet length in real time to sending in real time behind data buffer area, USB3.0 peripheral control unit is just initiated immediately the affiliated connected computer of USB3.0 node of this USB3.0 peripheral control unit and to the USB3.0 in this real time data sendaisle, is sent in real time the transfer of data of end points, can guarantee thus the real-time Transmission of data;
Switch intercommunication controller in each USB3.0 peripheral control unit forms switch internal communication network together with being interconnected at by described switch internal communication bus with USB3.0 node config memory, realizes the transmission of controlling data;
Described USB3.0 node config memory is for memory node configuration information.
2. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 1, it is characterized in that, described USB3.0 node also comprises bus converter, described bus converter is positioned in the exchanges data bus that USB3.0 peripheral control unit is connected with USB3.0 link controller, data/address bus between bus converter and USB3.0 peripheral control unit is wider than the data-bus width between bus converter and USB3.0 link controller, data/address bus transmission frequency in the data/address bus transfer of data frequency ratio between bus converter and USB3.0 peripheral control unit between bus converter and USB3.0 link controller is low.
3. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 1, is characterized in that, it also comprises USB3.0 gateway, and described USB3.0 gateway is realized the communication between switch and other networks.
4. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 1, it is characterized in that, USB3.0 end points in described USB3.0 peripheral control unit receives in real time and end points, also includes non real-time USB3.0 end points except USB3.0 sends end points and USB3.0 in real time, data buffer area in described USB3.0 peripheral control unit is except sending in real time data buffer area and receiving data buffer area and also include non-real-time data buffer area in real time, described non real-time USB3.0 end points and non-real-time data buffer area form non-real-time data interchange channel, the connected computer of node under described USB3.0 peripheral control unit is initiated the exchanges data with described non-real-time data interchange channel.
5. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 1, is characterized in that:
Described USB3.0 node config memory is EEPROM;
Described link configuration bus is spi bus bus;
Described switch internal communication bus is I
2c bus;
Described USB3.0 link controller is fpga chip.
6. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 2, is characterized in that, described bus converter is bus switch chip; Exchanges data highway width between described bus switch chip and described USB3.0 peripheral control unit is twice than the exchanges data highway width between described bus switch chip and described USB3.0 link controller, and the exchanges data bus data exchange frequency between described bus switch chip and described USB3.0 peripheral control unit is more half as large than the exchanges data bus data exchange frequency between described bus switch chip and described USB3.0 link controller.
7. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 1, is characterized in that:
Described USB3.0 node config memory is AT24C64 chip;
Described USB3.0 peripheral control unit is CYUSB3014 chip.
8. the very fast data switching exchane of USB3.0 local area network (LAN) according to claim 6, is characterized in that, described bus switch chip is SN74ALVCHG162282 chip.
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| CN201110435898.1A CN102546401B (en) | 2011-12-22 | 2011-12-22 | Universal serial bus (USB) 3.0 local area network top speed data switchboard |
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| CN201110435898.1A CN102546401B (en) | 2011-12-22 | 2011-12-22 | Universal serial bus (USB) 3.0 local area network top speed data switchboard |
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| CN102546401B true CN102546401B (en) | 2014-12-03 |
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| CN104361655A (en) * | 2014-11-24 | 2015-02-18 | 成都中远信电子科技有限公司 | Data recording device for aeronautical data recorder |
| CN104361656B (en) * | 2014-11-24 | 2016-10-26 | 成都中远信电子科技有限公司 | A kind of data logger for aviation |
| CN110519132A (en) * | 2019-08-28 | 2019-11-29 | 重庆德生鼎盛实业发展有限公司 | Data transmission method and system between a kind of computer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545004A (en) * | 2003-11-25 | 2004-11-10 | 浙江大学 | High speed USB data communication interface arrangement |
| CN201450512U (en) * | 2009-06-30 | 2010-05-05 | 无锡职业技术学院 | Switchboard with USB |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545004A (en) * | 2003-11-25 | 2004-11-10 | 浙江大学 | High speed USB data communication interface arrangement |
| CN201450512U (en) * | 2009-06-30 | 2010-05-05 | 无锡职业技术学院 | Switchboard with USB |
Non-Patent Citations (2)
| Title |
|---|
| CYPRESS PERFORM.CYUSB3014.《CYUSB3014》.2011,正文第1页、第6页. * |
| 晓辉.速度快10倍——走进USB3.0标准.《电脑知识与技术（经验技巧）》.2010,正文第57页. * |
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