CN102545844B - Delay circuit and method and device for controlling delay circuit to compensate power supply voltage drift - Google Patents
Delay circuit and method and device for controlling delay circuit to compensate power supply voltage drift Download PDFInfo
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Abstract
The invention provides a delay circuit, which comprises a switch circuit, a variable loading circuit, a charge-discharge circuit and an output control circuit. The switch circuit is used for being opened when receiving pulse input signals to control the charge-discharge circuit to conduct charging to power supply voltage and being closed after the pulse input signals to control the charge-discharge circuit to conduct discharging. The variable loading circuit is used for adjusting resistance of resistors in the variable loading circuit, changing discharging speed of the charge-discharge circuit, and further adjusting discharging time length to enable continuous time length of delay signals output by the delay circuit to reach a standard value. The discharging time length determines the continuous time length of the delay signals. The charge-discharge circuit is used for charging to the power supply voltage when the switch circuit is opened, discharging when the switch circuit is closed and transmitting analog signals formed in charging and discharging to the output control circuit. The output control circuit is used for outputting delay signals according to the analog signals formed in charging and discharging. A method and a device for controlling the delay circuit to compensate power supply voltage drift are further provided. The delay circuit, the method and the device ensure that signals passing through the delay circuit are delayed in constant mode.
Description
Technical field
The present invention relates to semiconductor circuit field, particularly method and the device of a kind of delay circuit and control delay circuit offset supply voltage drift.
Background technology
At present, in semiconductor device, can use delay circuit, pulse input signal is after delay circuit, and output has the time delayed signal of certain deration of signal (T), as shown in Fig. 1 solid line.But the signal through delay circuit does not often have constant time delay, and T can change with the variation of the various parameters such as supply voltage Vdd, ambient temperature and technical process.For instance, when if operating voltage Vdd is 1.8 volts, time delayed signal corresponding to output is in Fig. 1 shown in solid line, in the time of in being applied to actual time delay circuit, supply voltage can drift about, may be higher than 1.8 volts according to the difference of concrete delay circuit, also may be lower than 1.8 volts, at this moment will have influence on the width of the time delayed signal of actual output, the time delayed signal that makes actual output is shown in the dotted line or chain-dotted line in Fig. 1, and the time delayed signal width having is respectively T ' and T ".Above-mentioned parameter is larger than what depart under perfect condition, and the actual time delay signal obtaining is larger than the change width Δ T of standard signal, when semiconductor device is stricter to sequential requirement, even if the value of Δ T is very little, also can cause more serious consequence.As for T, can change with the variation of the various parameters such as supply voltage Vdd, ambient temperature and technical process, with parameter supply voltage wherein, the width of time delayed signal is that the analog signal that discharges and recharges of electric capacity determines in delay circuit, electric capacity is under the identical velocity of discharge, supply voltage is higher, and discharge time is longer, and the time delayed signal width of formation is wider, also just there is the situation shown in chain-dotted line in Fig. 1, otherwise just there will be situation shown in dotted lines in Figure 1.
Therefore how to guarantee that time delayed signal has constant time delay,, when above-mentioned parameter changes, make the value of Δ T minimum, become a key issue that needs solution.
Summary of the invention
In view of this, the technical problem that the present invention solves is: guarantee to have constant time delay through the signal of delay circuit.
For solving the problems of the technologies described above, technical scheme of the present invention is specifically achieved in that
The invention discloses a kind of delay circuit, comprising:
Switching circuit, for opening when receiving pulse input signal, controls charge-discharge circuit and charges to supply voltage; After pulse input signal, close, control charge-discharge circuit electric discharge;
Variable load circuits, for regulating the resistance of variable load circuits resistance, changes the speed of charge-discharge circuit electric discharge, and then adjusts electric discharge duration, makes the lasting duration of the time delayed signal of described delay circuit output reach standard value; Described electric discharge duration has determined the lasting duration of time delayed signal;
Charge-discharge circuit, for charging to supply voltage when switching circuit is opened; Electric discharge when switching circuit cuts out; And the analog signal that discharges and recharges formation is sent to output control circuit;
Output control circuit, for the analog signal output time delayed signal forming according to charge-discharge circuit.
This delay circuit further comprises the first NAND gate, one level input signal and described pulse input signal are carried out after NOT-AND operation, the signal that output one is anti-phase with described pulse input signal, sends to switching circuit and output control circuit, for cushioning pulse input signal.
Described switching circuit comprises the first transistor, and when grid receives the signal of the first NAND gate output, its source electrode and drain electrode conducting, control charge-discharge circuit and charge to supply voltage.
Described variable load circuits has first input end; Described charge-discharge circuit has the 3rd link; Described output control circuit has the second input and the 3rd input;
Wherein, the 3rd link of the first input end of described variable load circuits and charge-discharge circuit is, the 3rd input of output control circuit is connected in the drain electrode of the first transistor jointly; The second input of described output control circuit is connected with the output of the first NAND gate.
Described variable load circuits, also has selection signal input part, and this variable load circuits comprises the first load circuit, long raceway groove transistor seconds, the second load circuit and the 8th transistor of series connection successively; One end of described series circuit is first input end, and the other end is earth terminal;
Described the first load circuit and the second load circuit are connected in selection signal input part, and the resistance value of described the first load circuit or the second load circuit is according to selecting the selection signal of signal input part to regulate;
The drain electrode of described long raceway groove transistor seconds is connected with the second load circuit with the first load circuit respectively with source electrode, and its grid is connected with the output of the first NAND gate;
Described the 8th transistorized drain electrode is connected with earth terminal with the second load circuit respectively with source electrode, and its grid is connected with the output of the first NAND gate.
Described charge-discharge circuit comprises the 3rd transistor and the 4th transistor in parallel, and described the 3rd transistor is PMOS pipe, and its source electrode and drain electrode connect supply voltage; Described the 4th transistor is NMOS pipe, its source electrode and grounded drain; Described the 3rd transistorized grid and the 4th transistorized grid are connected in the drain electrode of the first transistor jointly.
Described output control circuit comprises the second NAND gate and the 5th transistor and the 6th transistor in parallel;
Described the 5th transistor is PMOS pipe, and its source electrode connects supply voltage; Described the 6th transistor is NMOS pipe, its source ground;
Described the second NAND gate has four-input terminal and the 5th input, and described the 5th input is connected with the second input of output control circuit;
Described four-input terminal is connected with the 6th transistorized drain electrode with the 5th transistor;
Described the 5th transistor and the 6th transistorized grid are connected in the 3rd input of output control circuit.
This delay circuit further comprises clear circuit, for before charge-discharge circuit charging and after electric discharge, to clear circuit input triggering signal, the electric weight in charge-discharge circuit is carried out to zero clearing.
Described clear circuit has triggering signal input, the first link and the second link, and described the first link is connected with the 3rd link of charge-discharge circuit, described the second link ground connection, and this clear circuit comprises an inverter and the 7th transistor;
The input that described triggering signal input is inverter, the output of inverter is connected with the 7th transistorized grid;
Described the 7th transistorized drain electrode and source electrode are respectively the first link and the second link.
The invention also discloses a kind of method of controlling described delay circuit offset supply voltage drift, the method comprises:
Detect in real time the drift value of supply voltage;
According to the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value, select the resistance value in variable load circuits.
The invention also discloses a kind of device of controlling described delay circuit offset supply voltage drift, this device comprises:
Memory cell, the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value;
Detecting unit, for detecting in real time the drift value of supply voltage;
Control unit, for receiving the drift value of supply voltage, according to the corresponding relation of the drift value of supply voltage and variable load circuits resistance value, selects the resistance value in variable load circuits.
As seen from the above technical solutions, delay circuit key of the present invention is to be provided with variable load circuits, the speed that charge-discharge circuit discharges by variable load circuits determines by the resistance of variable load circuits, and the size of variable load circuits resistance value is directly proportional to the width of the time delayed signal of output.The selection signal input part of variable load circuits is controlled and is selected signal input, and the resistance of variable load circuits is regulated, and for the signal that causes because of various parameter influences departing from standard time delayed signal width, compensates, and makes delay circuit have constant time delay.Wherein, for supply voltage, drift causes the problem that departs from standard time delayed signal width that a kind of method and apparatus of controlling this delay circuit offset supply voltage drift is also provided, adopt the method and device to because supply voltage drift causes the signal that departs from standard time delayed signal width accurately to compensate, to make delay circuit there is constant time delay.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the time delayed signal of delay circuit pulse input signal and output;
Fig. 2 is the structural representation of delay circuit of the present invention;
Fig. 3 is the structural representation of embodiment of the present invention delay circuit;
Fig. 4 is the embodiment of the present invention delay circuit working timing figure corresponding with Fig. 3;
Fig. 5 is the structural representation of the first load circuit or the second load circuit.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The invention provides a kind of delay circuit, its structural representation as shown in Figure 2.This delay circuit comprises:
Switching circuit 1, for opening when receiving pulse input signal, controls charge-discharge circuit and charges to supply voltage; After pulse input signal, close, control charge-discharge circuit electric discharge;
Variable load circuits 2, for regulating the resistance of variable load circuits resistance, changes the speed of charge-discharge circuit electric discharge, and then adjusts electric discharge duration, makes the lasting duration of the time delayed signal of described delay circuit output reach standard value; Described electric discharge duration has determined the lasting duration of time delayed signal;
Charge-discharge circuit 3, for charging to supply voltage when switching circuit is opened; Electric discharge when switching circuit cuts out; And the analog signal that discharges and recharges formation is sent to output control circuit;
Output control circuit 4, for the analog signal output time delayed signal forming according to charge-discharge circuit.
Based on foregoing description, enumerate specific embodiment below the structure of delay circuit of the present invention is described, but the structure of delay circuit of the present invention is not limited to a kind of structure below.
The structural representation of embodiment of the present invention delay circuit as shown in Figure 3.
It is high level input signal that the structure of this delay circuit is applicable to level input signal, and pulse input signal is while being positive pulse signal, by the width extending of described positive pulse signal to predetermined value.Below in conjunction with Fig. 4, be elaborated, Fig. 4 is the embodiment of the present invention delay circuit working timing figure corresponding with Fig. 3.
The first NAND gate 101, carries out level input signal and pulse input signal after NOT-AND operation, the signal that output one is anti-phase with described pulse input signal, and send to switching circuit and output control circuit, for cushioning pulse input signal.It should be noted that, above-mentioned the first NAND gate is not necessary for technical scheme of the present invention, can be to the direct input pulse input signal of switching circuit, still arranging of the first NAND gate can further reach the effect that cushions pulse input signal, and circuit is optimized.Further, for adapting with the first NAND gate, input a level input signal with pulse input signal simultaneously.
Switching circuit 102 can be the first transistor, is PMOS pipe TP1, and the grid of this PMOS pipe TP1 is connected with the output of the first NAND gate; Source electrode connects supply voltage; Drain with the first input end of variable load circuits, the first link of the 3rd link of charge-discharge circuit, clear circuit and the 3rd input of output control circuit are connected.This switching circuit is when its grid receives the signal of the first NAND gate output, and its source electrode and drain electrode conducting, control charge-discharge circuit and charge to supply voltage.
Charge-discharge circuit 103 can be the 3rd transistor and the 4th transistor in parallel, wherein, the 3rd transistor is PMOS pipe TP3, the 4th transistor is NMOS pipe TN4, this PMOS pipe TP3 is connected with the grid of NMOS pipe TN4, is the 3rd link, is connected to the first input end of variable load circuits, source electrode and the drain electrode of PMOS pipe TP3 are connected to supply voltage Vdd, and the source electrode of NMOS pipe and drain electrode are connected to ground Vss.The 3rd transistor and the 4th transistor in parallel in this charge-discharge circuit are equivalent to two electric capacity in parallel, and by opening with disconnected of switching circuit, electric capacity carries out charging and discharging, forms and discharges and recharges analog signal.
Output control circuit 104 has the second input and the 3rd input, and described the second input is connected with the output of the first NAND gate, and described the 3rd input is connected with the 3rd link of charge-discharge circuit.Wherein output control circuit comprises the second NAND gate 41 and the 5th transistor and the 6th transistor in parallel.The second NAND gate has four-input terminal and the 5th input, described the 5th input is connected with the second input of output control circuit, the 5th transistor can be PMOS pipe TP5, the 6th transistor can be NMOS pipe TN6, the 5th transistor and the 6th transistorized grid are connected in the 3rd input, the 5th transistorized source electrode connects supply voltage, the 6th transistorized source ground, and the 5th transistor AND gate the 6th transistorized drain electrode is connected in four-input terminal.The four-input terminal of the second NAND gate is input as high level signal or low level signal, relevant by TP5 or TN6 conducting, and when TP5 conducting, the four-input terminal of the second NAND gate is input as high level signal; When TN6 conducting, the four-input terminal of the second NAND gate is input as low level signal.Further, transistor all has threshold voltage, and its grid of TP5 conducting is input as low level signal, and the signal lower than TP5 threshold voltage is considered as to low level signal; Its grid of TN6 conducting is input as high level signal, and the signal higher than TN6 threshold voltage is considered as to high level signal.
Variable load circuits 105, there is signal input part, first input end and the earth terminal of selection, the first load circuit 51, long raceway groove transistor seconds, the second load circuit 52 and the 8th transistor that comprise series connection successively, the two ends of this series circuit are considered as respectively first input end and earth terminal.Long raceway groove transistor seconds has certain resistance value, although area occupied is little during Butut, relative the first load circuit of resistance or the second load circuit are unstable.Long raceway groove transistor seconds can be NMOS pipe TN2, and drain electrode is connected with the first load circuit, and source electrode is connected with the second load circuit, and grid is connected with the output of the first NAND gate.The 8th transistor can be NMOS pipe TN8, and the output of its source electrode and output control circuit is connected to ground; Grid is connected with the output of the first NAND gate; Drain electrode is connected with the second load circuit.Select signal input part to be connected in the first load circuit and the second load circuit, to the first load circuit and the second load circuit, provide selection signal.The resistance value of the first load circuit and the second load circuit is adjustable, can be according to selecting the input of signal to control.Charge-discharge circuit discharges by this variable load circuits, that is to say that the resistance value that the first load circuit, TN2 and the first load circuit are together in series has determined the speed that charge-discharge circuit discharges.
The structural representation of the first load circuit or the second load circuit as shown in Figure 5.In the present embodiment, select signal input part can input 4 simultaneously and select signal, be respectively signal S0, S1, S2 and S3.Resistance R 1 to R5 is connected successively, and the two ends of the transistor AND gate resistance R 1 of being controlled by signal S0 are in parallel; The transistor AND gate series resistance R1 being controlled by signal S1 and the two ends of R2 are in parallel; Transistor AND gate series resistance R1, the R2 being controlled by signal S2 and the two ends of R3 are in parallel; The two ends of transistor AND gate series resistance R1, R2, R3 and the R4 being controlled by signal S3 are in parallel.Transistor can be that NMOS pipe can be also PMOS pipe, is NMOS pipe TN in the present embodiment.During this circuit working, when while input select signal S0, S1, S2 and S3, the output resistance of the first load circuit (the second load circuit) is R5; When while input select signal S0, S1 and S2, the output resistance of the first load circuit (the second load circuit) is R4+R5; When while input select signal S0 and S1, the output resistance of the first load circuit (the second load circuit) is R3+R4+R5.By that analogy, according to Fig. 3, those skilled in the art can need to obtain corresponding resistance according to circuit.
Clear circuit 106, there is triggering signal input, the first link and the second link, comprise an inverter INV and the 7th transistor, triggering signal input is the input of inverter, the output of inverter is connected with the 7th transistorized grid, and the 7th transistor can be NMOS pipe TN7, and its drain electrode is connected with the 3rd link of charge-discharge circuit, be connected in the 3rd transistor and the 4th transistorized grid, source ground.This clear circuit, according to the triggering signal of triggering signal input, before charge-discharge circuit charging and after electric discharge, by TN7 conducting ground connection, carries out zero clearing to the electric weight in charge-discharge circuit.It should be noted that above-mentioned clear circuit is not necessary for technical scheme of the present invention, but arranging of clear circuit can make whole delay circuit export regular signal waveform.
Delay circuit structure based on shown in Fig. 3, following process is followed in the formation of time delayed signal:
First, before charge-discharge circuit charging, the triggering signal input input undersuing of clear circuit, this undersuing, after inverter is anti-phase, is exported positive pulse signal, and described positive pulse signal is by the 7th transistor NMOS pipe conducting, because its drain electrode is connected with charge-discharge circuit, source ground, so if there is dump energy in charge-discharge circuit, this dump energy is discharged completely through the 7th transistor of conducting.
1) high level input signal sig1 and positive pulse signal sig2 input to after NAND gate, through NOT-AND operation output undersuing, the first transistor PMOS manages conducting, source electrode connection supply voltage due to PMOS pipe, the PMOS pipe of conducting can be pulled up to Vdd by C point voltage, so electric capacity starts to charge to supply voltage.Now C point voltage constantly raises with charging process, before not being elevated to the 5th transistor and the 6th transistorized threshold voltage, C point voltage value is considered as low level, this low level signal is by the 5th transistor PMOS pipe conducting, because the 5th transistorized source electrode connects supply voltage, so A point voltage is pulled up to Vdd, when undersuing is between ac point, A point is high level.When C point voltage is increased to over the 5th transistor and the 6th transistorized threshold voltage with charging process, C point voltage value is considered as high level, this high level signal is by the 6th transistor NMOS pipe conducting, due to the 6th transistorized source ground, so A point voltage is reduced to Vss, when undersuing is between cb point, A point is low level.
Undersuing is between ab point time, and B point is always low level, so after the second NAND gate of output control circuit, Z point is output as high level.
2) in the time of between the high level signal bd point after undersuing, the first transistor PMOS manages cut-off, long raceway groove transistor seconds TN2 conducting, the 8th also conducting of transistor T N8, make the first load circuit, TN2 and the second load circuit resistance series connection ground connection, and charge-discharge circuit starts electric discharge by variable load circuits.Different according to the resistance value of variable load circuits, the speed of its electric discharge is also different.Now C point voltage constantly reduces with discharge process, this point voltage is when being not less than the 5th transistor and the 6th transistorized threshold voltage, C point voltage value is still considered as high level, this high level signal is by the 6th transistor NMOS pipe conducting, due to the 6th transistorized source ground, so A point is low level.
In the time of between high level signal bd point after undersuing, B point is always high level, so after the second NAND gate of output control circuit, Z point is output as high level.
3) in the time of between the high level signal de point after undersuing, the still cut-off of the first transistor PMOS pipe, charge-discharge circuit continues electric discharge by variable load circuits, C point voltage reduces with discharge process, during lower than the 5th transistor and the 6th transistorized threshold voltage, C point voltage value is considered as low level, this low level signal is by the 5th transistor PMOS pipe conducting, because the 5th transistorized source electrode connects supply voltage, so A point voltage is pulled up to Vdd, in the time of between de point, A point is high level.
In the time of between high level signal de point after undersuing, B point is always high level, so after the second NAND gate of output control circuit, Z point is output as low level.
Because the width of time delayed signal is the width between ad, and the speed that charge-discharge circuit discharges by variable load circuits after d point is slow, so clear circuit is triggered when d point, charge-discharge circuit discharges by discharge circuit.The triggering signal input of this clear circuit is inputted undersuing again, this undersuing is after inverter is anti-phase, output positive pulse signal, described positive pulse signal is by the 7th transistor NMOS pipe conducting, because its drain electrode is connected with charge-discharge circuit, source ground, so by the dump energy in charge-discharge circuit, through clear circuit, electric discharge is complete rapidly.
In summary, the width of the time delayed signal of Z point output, for the deration of signal between ad, by the resistance value of variable load circuits and the 5th transistor and the 6th transistorized threshold voltage, determined, the resistance value of variable load circuits has determined the speed of charge-discharge circuit through variable load circuits electric discharge, resistance value is less, discharge faster, slope k is larger, easier the 5th transistor and the 6th transistorized threshold voltage of reaching within the relatively short time, making Z point is low level by high level saltus step, and the width between ad is also just narrower so; Otherwise principle is also identical, resistance value is larger, discharges slower, and slope k is less, will within the relatively long time, reach the 5th transistor and the 6th transistorized threshold voltage, and making Z point is low level by high level saltus step, and the width between ad is also just wider so.General transistorized threshold voltage is fixed, therefore just can be by regulating the resistance of variable load circuits, and the width of control time delayed signal, reaches the constant delay of delay circuit, thereby compensates the impact of other parameters that this delay circuit is subject to.
For example, when detecting Vdd and have drift, the time delayed signal width of actual output will be variant with standard time delayed signal width, and this standard time delayed signal width is the desirable time delayed signal width that Vdd obtains during without drift.Therefore, the present invention is according to the corresponding relation between the drift value of Vdd and variable load circuits resistance value, input select signal is controlled the resistance value of variable load circuits input, under this resistance value, the change width of time delayed signal is compensated, thereby obtain standard time delayed signal width, under this delay circuit, make time delayed signal not be subject to the impact of the various parameters such as Vdd, ambient temperature and technical process, obtain having the signal of constant delay.
Therefore, the present invention is based on above-mentioned delay circuit, proposed a kind of method of controlling delay circuit offset supply voltage drift, the method comprises:
Detect in real time the drift value of supply voltage;
According to the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value, select the resistance value in variable load circuits.
For realizing said method, the present invention also provides a kind of device of controlling this delay circuit offset supply voltage drift, and this device comprises:
Memory cell, the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value;
Detecting unit, for detecting in real time the drift value of supply voltage;
Control unit, for receiving the drift value of supply voltage, according to the corresponding relation of the drift value of supply voltage and variable load circuits resistance value, selects the resistance value in variable load circuits.
Variable load circuits in Fig. 5 is a specific embodiment of the present invention, can also be according to circuit need to connect a plurality of the first load circuits or the second load circuit.The first load circuit in Fig. 5 or the second load circuit also can have other structure, for example, the number of while input select signal are changed, as long as can reach, can control flexibly the resistance value in this circuit according to the needs of time delayed signal length.
Clear circuit can have other structure, for example, NMOS pipe is replaced with to PMOS pipe, when clear circuit is worked, inputs undersuing, makes source electrode and the drain electrode conducting of PMOS pipe, and the dump energy zero clearing by charge-discharge circuit, equally also can achieve the goal.
In addition, for switching circuit, also PMOS pipe can be replaced with to NMOS pipe, correspondence replaces with PMOS pipe by long raceway groove transistor seconds and the 8th transistor.The 3rd transistor and the 4th transistor in parallel in charge-discharge circuit are equivalent to two electric capacity in parallel, the object of the invention is to realize discharging and recharging of electric capacity, so the 3rd transistor and the 4th transistor can be replaced with to a simple electric capacity, or replace with a single transistor as electric capacity.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (8)
1. a delay circuit, comprising:
Switching circuit, for opening when receiving pulse input signal, controls charge-discharge circuit and charges to supply voltage; After pulse input signal, close, control charge-discharge circuit electric discharge;
Variable load circuits, for regulating the resistance of variable load circuits resistance, changes the speed of charge-discharge circuit electric discharge, and then adjusts electric discharge duration, makes the lasting duration of the time delayed signal of described delay circuit output reach standard value; Described electric discharge duration has determined the lasting duration of time delayed signal;
Charge-discharge circuit, for charging to supply voltage when switching circuit is opened; Electric discharge when switching circuit cuts out; And the analog signal that discharges and recharges formation is sent to output control circuit;
Output control circuit, for the analog signal output time delayed signal forming according to charge-discharge circuit;
This delay circuit further comprises the first NAND gate, one level input signal and described pulse input signal are carried out after NOT-AND operation, the signal that output one is anti-phase with described pulse input signal, sends to switching circuit and output control circuit, for cushioning pulse input signal;
Described switching circuit comprises the first transistor, and when grid receives the signal of the first NAND gate output, its source electrode and drain electrode conducting, control charge-discharge circuit and charge to supply voltage;
Described variable load circuits has first input end; Described charge-discharge circuit has the 3rd link; Described output control circuit has the second input and the 3rd input;
Wherein, the 3rd link of the first input end of described variable load circuits and charge-discharge circuit is, the 3rd input of output control circuit is connected in the drain electrode of the first transistor jointly; The second input of described output control circuit is connected with the output of the first NAND gate.
2. delay circuit as claimed in claim 1, it is characterized in that, described variable load circuits, also has selection signal input part, and this variable load circuits comprises the first load circuit, long raceway groove transistor seconds, the second load circuit and the 8th transistor of series connection successively; One end of described series circuit is first input end, and the other end is earth terminal;
Described the first load circuit and the second load circuit are connected in selection signal input part, and the resistance value of described the first load circuit or the second load circuit is according to selecting the selection signal of signal input part to regulate;
The drain electrode of described long raceway groove transistor seconds is connected with the second load circuit with the first load circuit respectively with source electrode, and its grid is connected with the output of the first NAND gate;
Described the 8th transistorized drain electrode is connected with earth terminal with the second load circuit respectively with source electrode, and its grid is connected with the output of the first NAND gate.
3. delay circuit as claimed in claim 1, is characterized in that, described charge-discharge circuit comprises the 3rd transistor and the 4th transistor in parallel, and described the 3rd transistor is PMOS pipe, and its source electrode and drain electrode connect supply voltage; Described the 4th transistor is NMOS pipe, its source electrode and grounded drain; Described the 3rd transistorized grid and the 4th transistorized grid are connected in the drain electrode of the first transistor jointly.
4. delay circuit as claimed in claim 1, is characterized in that, described output control circuit comprises the second NAND gate and the 5th transistor and the 6th transistor in parallel;
Described the 5th transistor is PMOS pipe, and its source electrode connects supply voltage; Described the 6th transistor is NMOS pipe, its source ground;
Described the second NAND gate has four-input terminal and the 5th input, and described the 5th input is connected with the second input of output control circuit;
Described four-input terminal is connected with the 6th transistorized drain electrode with the 5th transistor;
Described the 5th transistor and the 6th transistorized grid are connected in the 3rd input of output control circuit.
5. delay circuit as claimed in claim 1, is characterized in that, this delay circuit further comprises clear circuit, for before charge-discharge circuit charging and after electric discharge, to clear circuit input triggering signal, the electric weight in charge-discharge circuit is carried out to zero clearing.
6. delay circuit as claimed in claim 5, it is characterized in that, described clear circuit has triggering signal input, the first link and the second link, described the first link is connected with the 3rd link of charge-discharge circuit, described the second link ground connection, this clear circuit comprises an inverter and the 7th transistor;
The input that described triggering signal input is inverter, the output of inverter is connected with the 7th transistorized grid;
Described the 7th transistorized drain electrode and source electrode are respectively the first link and the second link.
7. a method of controlling delay circuit offset supply voltage drift described in claim 1, the method comprises:
Detect in real time the drift value of supply voltage;
According to the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value, select the resistance value in variable load circuits.
8. a device of controlling delay circuit offset supply voltage drift described in claim 1, this device comprises:
Memory cell, the corresponding relation of the drift value of pre-stored supply voltage and variable load circuits resistance value;
Detecting unit, for detecting in real time the drift value of supply voltage;
Control unit, for receiving the drift value of supply voltage, according to the corresponding relation of the drift value of supply voltage and variable load circuits resistance value, selects the resistance value in variable load circuits.
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| CN201010580808.3A CN102545844B (en) | 2010-12-09 | 2010-12-09 | Delay circuit and method and device for controlling delay circuit to compensate power supply voltage drift |
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| CN114429747B (en) * | 2022-01-26 | 2023-10-17 | Tcl华星光电技术有限公司 | display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1086941A (en) * | 1992-11-11 | 1994-05-18 | 凌阳科技股份有限公司 | Charging or discharging current and test voltage ratio changeable delay circuit |
| KR20030081621A (en) * | 2002-04-12 | 2003-10-22 | 삼성전자주식회사 | Semiconductor integrated circuit device capable of securing time delay insensitive to temperature variation |
| CN101546178A (en) * | 2008-03-24 | 2009-09-30 | 纬创资通股份有限公司 | Timing control device |
| CN101908867A (en) * | 2009-06-03 | 2010-12-08 | 联发科技股份有限公司 | Fine delay adjustment device and voltage controlled oscillator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4986299B2 (en) * | 2008-04-10 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and timing adjustment method for semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1086941A (en) * | 1992-11-11 | 1994-05-18 | 凌阳科技股份有限公司 | Charging or discharging current and test voltage ratio changeable delay circuit |
| KR20030081621A (en) * | 2002-04-12 | 2003-10-22 | 삼성전자주식회사 | Semiconductor integrated circuit device capable of securing time delay insensitive to temperature variation |
| CN101546178A (en) * | 2008-03-24 | 2009-09-30 | 纬创资通股份有限公司 | Timing control device |
| CN101908867A (en) * | 2009-06-03 | 2010-12-08 | 联发科技股份有限公司 | Fine delay adjustment device and voltage controlled oscillator |
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| CN102545844A (en) | 2012-07-04 |
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