CN102544304A - Carrier, semiconductor package and manufacturing method for semiconductor package - Google Patents
Carrier, semiconductor package and manufacturing method for semiconductor package Download PDFInfo
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- CN102544304A CN102544304A CN2010106129427A CN201010612942A CN102544304A CN 102544304 A CN102544304 A CN 102544304A CN 2010106129427 A CN2010106129427 A CN 2010106129427A CN 201010612942 A CN201010612942 A CN 201010612942A CN 102544304 A CN102544304 A CN 102544304A
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- substrate
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- semiconductor package
- semiconductor element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Led Device Packages (AREA)
Abstract
The invention provides a carrier, a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package comprises a substrate, a solder mask, a first metal layer, a semiconductor element and a packaging material, wherein the solder mask is arranged on the surface, and is provided with an opening for exposing the surface of the substrate; the first metal layer is arranged on the surface of the solder mask; the semiconductor element is arranged on the substrate in the opening, and is electrically connected with the substrate; and the packaging material is arranged in the opening, and covers the semiconductor element. The opening for placing the semiconductor element is directly formed in the solder mask, so that etching can be realized without an etching solution and additional time, and cost is further effectively decreased.
Description
Technical field
The present invention relates to a kind of bearing part, semiconductor package part and method for making thereof, bearing part, semiconductor package part and method for making thereof that particularly a kind of cost is low.
Background technology
Along with the progress of electronics industry and the arriving of digital age, the trend development that various electronic product is day by day integrated towards effect, expectation can be with various product integration on single portable apparatus; To promote the easy-to-use of user; And then break through original spatial constraints, therefore, be disposed at for each electronic product for for example having light-emitting diode (LED) or a laser diode (Laser Diode) etc.; How its device towards slimming is integrated, be undoubtedly the trend of present electronic industry.
See also Fig. 1, Fig. 1 is the sketch map of the packaging part of existing tool light-emitting component.This packaging part forms groove 100 with inclined wall 100a to carry the semiconductor element 11 like light-emitting diode (LED) or laser diode (Laser Diode) on silicon substrate 10; And this semiconductor element 11 electrically connects this silicon substrate 10 with the routing mode, and on the inclined wall 100a of this groove 100, form insulating layer of silicon oxide 12 in regular turn, with the made reflector 13 of the high materials of light reflex rate such as aluminium or silver, and insulating layer of silicon oxide 14.
Please consult Fig. 2 A to 2C again, Fig. 2 A to 2C is the method for making sketch map of No. 6531328 silicon substrate with groove that United States Patent (USP) disclosed.Shown in Fig. 2 A, on silicon substrate 10, be coated with photoresist layer 15 earlier, and utilize the mask lithography mode to remove part photoresist layer 15 to form opening 150, the part surface of this silicon substrate 10 is exposed in this opening 150.Shown in Fig. 2 B, silicon substrate 10 surfaces that wet etching exposes, with formation groove 100, and this groove 100 has inclined wall 100a.Shown in Fig. 2 C, remove this photoresist layer 15.
The forming mode of the groove 100 of existing silicon substrate 10 is the wet etching Patternized technique, thereby makes this groove 100 have the inclined wall 100a of inclination angle 54.74 degree, and this is that chemical lattice arrangement because of the silicon crystal lattice of this silicon substrate 10 causes.But, if desire to etch other angles, need are expended the more time and use more multiple medicines liquid to reach better luminous reflection efficiency or to reduce height (angle is bigger, highly lower, is beneficial to the thinning design), cause the technology cost to improve.
Moreover, use the wet etching Patternized technique to form this groove 100, need purchase Wet-type etching equipment and soup, cause production cost significantly to improve.
Therefore, how to avoid the variety of problems of prior art, real is current target to be solved.
Summary of the invention
For overcoming the disadvantages of prior art, the present invention provides a kind of semiconductor package part, comprising: substrate; The resistance layer is located on this substrate, and is had opening, to expose outside the surface of this substrate; The first metal layer is located on this resistance laminar surface; Semiconductor element is located on the substrate in this opening, and electrically connects this substrate; The encapsulation material is located in this opening, with this semiconductor element that is covered.
The present invention also discloses a kind of method for making of semiconductor package part, comprising: a substrate is provided; On this substrate, form the resistance layer, and on this resistance layer, form at least one opening, to expose outside the surface of this substrate; On this resistance laminar surface, form the first metal layer; On the substrate in this opening semiconductor element is set, and makes this semiconductor element electric connect this substrate; And in this opening, form the encapsulation material, with this semiconductor element that is covered.
In addition, the present invention also provides a kind of bearing part, comprising: substrate; Resistance layer is located on this substrate, and is had opening, and exposing outside the surface of this substrate, and the bore of this opening is towards this substrate surface convergent; And the first metal layer, be located on this resistance laminar surface.
In aforesaid semiconductor package part, its method for making and the bearing part, this substrate can be silicon substrate, and this resistance layer can be photoresist layer, and the bore of this opening is good to taper to towards this substrate surface, and the material that forms this first metal layer can be silver, aluminium or nickel.
In aforesaid semiconductor package part, its method for making and the bearing part, this semiconductor element is a light-emitting diode chip for backlight unit, and this semiconductor element is with the routing mode or cover crystal type and electrically connect this substrate.
In aforesaid semiconductor package part, its method for making and the bearing part; Also be included in this semiconductor element is set before; Form second metal level, be located on this substrate or the part resistance layer, and be connected with this semiconductor element electric; For example this semiconductor element can be located on this second metal level, and the material that forms this second metal level is gold or nickel.
By on can know; Bearing part of the present invention, semiconductor package part and method for making thereof; On this resistance layer, form the opening of placing this semiconductor element through direct, replacement is made opening like prior art with the wet etching mode on substrate, not only need not to use etching solution; And need not to expend extra time and carry out etching, effectively reduce the technology cost.
Moreover through the opening that directly on this resistance layer, forms, the angle of inclination of the hole wall of this opening is unrestricted, and the angle of inclination is increased, and is highly lower to reduce, and effectively reaches the purpose of thinning.
In addition,, therefore need not to purchase Wet-type etching equipment and soup, effectively reduce production costs owing to need not to use the wet etching Patternized technique.
Description of drawings
Fig. 1 is the generalized section of the packaging part of existing tool light-emitting component;
Fig. 2 A to 2C is the sketch map of the method for making of United States Patent (USP) notification number US 6531328B1; And
Fig. 3 A to 3E is the generalized section of the method for making of semiconductor package part of the present invention.
The main element symbol description
10 silicon substrates
100 grooves
The 100a inclined wall
11 semiconductor elements
12,14 insulating layer of silicon oxide
13 reflector
15 photoresist layers
150 openings
20 substrates
21 resistance layers
210 openings
22 the first metal layers
220 flutings
23 semiconductor elements
230 second metal levels
24 encapsulation materials
Embodiment
Below through particular specific embodiment execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
Below cooperate in the execution mode of Fig. 3 A to 3E explanation; So-called " one ", " on ", D score only is referential data and the relative reference direction of being convenient to explain technical characterictic of the present invention; Be not in order to limit execution mode of the present invention and protection range, close chat earlier bright.
See also Fig. 3 A to 3E, disclosed the method for making of semiconductor package part of the present invention.
Shown in Fig. 3 A, a substrate 20 is provided, to make the usefulness of carrying, in the present embodiment, this substrate 20 can be silicon substrate or wiring board, and has the conducting wire in the substrate 20.
Shown in Fig. 3 B, form resistance layer 21 on this substrate 20, this resistance layer 21 can be photoresist, forms many openings 210 with the mode through exposure imaging on this resistance layer 21, exposes outside this opening 210 with the part surface that makes this substrate 20.In the present embodiment, the bore of this opening 210 is towards these substrate 20 surperficial convergents, and promptly convergent from top to bottom is inclination with the hole wall that makes this opening 210.
Shown in Fig. 3 C figure; Form the first metal layer 22 in these resistance layer 21 surfaces, in the present embodiment, this first metal layer 22 also extends to form on substrate 20 surfaces in this opening 210; And have the fluting 220 that exposes outside these substrate 20 surfaces, to form bearing part of the present invention.In the present embodiment, the material that forms this first metal layer 22 is the material with high index of refraction, for example: silver, aluminium or nickel, with usefulness as the reflector.
Shown in Fig. 3 D figure, be provided with on the substrate 20 of semiconductor element 23 in opening 210.In the present embodiment, semiconductor element 23 is located on substrate 20 surfaces in the fluting 220 in this opening 210, and makes this semiconductor element 23 electrically connect this substrate 20.In the present embodiment, this semiconductor element 23 is a light-emitting diode chip for backlight unit, and this semiconductor element 23 electrically connects this substrate 20 with the routing mode, also can cover crystal type and electrically connect this substrate 20.Moreover, also can, this semiconductor element 23 form second metal level 230 before being set; Be located on this substrate 20 or the part resistance layer 21; And electrically connect with semiconductor element 23, for example this semiconductor element 23 is located on this second metal level 230, and the material that forms this second metal level 230 is the material with heat conduction and conductive characteristic; For example: gold or nickel reach the usefulness when electrical conducting path for these semiconductor element 23 heat radiations.
Shown in Fig. 3 E, the encapsulation material 24 that formation wherein is dispersed with fluorescent material is in this opening 210, with this semiconductor element 23 that is covered.
The present invention through this first metal layer 22 to reflect the light that this semiconductor element 23 is produced.
Moreover the present invention forms the opening 210 of placing this semiconductor element 23 through the mode with exposure imaging on this resistance layer 21, not only need not to use etching solution; And need not to expend extra time and carry out etching; Effectively reduce the technology cost, and the angle of inclination of the hole wall of this opening 210 is unrestricted, the angle of inclination is increased; Highly lower to reduce, effectively reach the purpose of thinning.
In addition,, therefore need not to purchase Wet-type etching equipment and soup, effectively reduce production costs owing to need not to use the wet etching Patternized technique.
The present invention also provides a kind of semiconductor package part, comprising: the light-emitting component bearing part comprises substrate 20, is located at the resistance layer 21 on this substrate 20 and is located at this resistance layer 21 lip-deep the first metal layers 22; Be located at the semiconductor element 23 on this substrate 20; And the encapsulation material 24 of this semiconductor element 23 that is covered.
Described resistance layer 21 has the opening 210 of the part surface that exposes outside this substrate 20.
In the present embodiment, described the first metal layer 22 also is located on substrate 20 surfaces in this opening 210, and the first metal layer 22 in this opening 210 have the fluting 220, to expose outside the surface of this substrate 20.
Described semiconductor element 23 is located on substrate 20 surfaces in the fluting 220 in this opening 210, and electrically connects this substrate 20.
Described encapsulation material 24 is located in this opening 210, with this semiconductor element 23 that is covered.
Described semiconductor package part also can comprise second metal level 230; Be located on this substrate 20 or the part resistance layer 21; And electrically connect with semiconductor element 23, and the material that forms this second metal level 230 is the material with heat conduction and conductive characteristic, for example: gold or nickel.
In sum, semiconductor package part of the present invention and method for making thereof through directly on this resistance layer, forming the opening of placing this semiconductor element, not only need not to use etching solution, and need not to expend extra time and carry out etching, effectively reduce the manufacturing approach cost.
Moreover through the opening that directly on this resistance layer, forms, the angle of inclination of the hole wall of this opening is unrestricted, and the angle of inclination is increased, and is highly lower to reduce, and effectively reaches the purpose of thinning.
In addition,, therefore need not to purchase Wet-type etching equipment and soup, effectively reduce production costs owing to need not to use wet etching patterning manufacturing approach.
The foregoing description is in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So rights protection scope of the present invention, should be listed like claim.
Claims (19)
1. semiconductor package part comprises:
Substrate;
The resistance layer is located on this substrate, and is had opening, to expose outside the surface of this substrate;
The first metal layer is located on this resistance laminar surface;
Semiconductor element is located on the substrate in this opening, and electrically connects this substrate, and this semiconductor element is a light-emitting diode chip for backlight unit; And
The encapsulation material is located in this opening, with this semiconductor element that is covered.
2. semiconductor package part according to claim 1 is characterized in that this first metal layer also is formed on the substrate surface in this opening, and has the fluting that exposes outside this substrate surface, and this semiconductor element is located on the substrate in this fluting.
3. semiconductor package part according to claim 1 is characterized in that, this substrate is a silicon substrate.
4. semiconductor package part according to claim 1 is characterized in that, the bore of this opening is towards this substrate surface convergent.
5. semiconductor package part according to claim 1 is characterized in that, the material that forms this first metal layer is silver, aluminium or nickel.
6. semiconductor package part according to claim 1 is characterized in that, this semiconductor element is with the routing mode or cover this substrate of crystal type electric connection.
7. semiconductor package part according to claim 1 is characterized in that, also comprises second metal level, is located on this substrate or the part resistance layer, and is connected with this semiconductor element electric.
8. semiconductor package part according to claim 7 is characterized in that, the material that forms this second metal level is gold or nickel.
9. semiconductor package part according to claim 1 is characterized in that, is dispersed with fluorescent material in this encapsulation material.
10. the method for making of a semiconductor package part comprises:
One substrate is provided;
On this substrate, form the resistance layer, and on this resistance layer, form at least one opening, to expose outside the surface of this substrate;
On this resistance laminar surface, form the first metal layer;
On the substrate in this opening semiconductor element is set, and makes this semiconductor element electric connect this substrate, this semiconductor element is a light-emitting diode chip for backlight unit; And
In this opening, form the encapsulation material, with this semiconductor element that is covered.
11. the method for making of semiconductor package part according to claim 10 is characterized in that, this first metal layer also is formed on the substrate surface in this opening, and has the fluting that exposes outside this substrate surface, and this semiconductor element is located on the substrate in this fluting.
12. the method for making of semiconductor package part according to claim 10 is characterized in that, this substrate is a silicon substrate.
13. the method for making of semiconductor package part according to claim 10 is characterized in that, the bore of this opening is towards this substrate surface convergent.
14. the method for making of semiconductor package part according to claim 10 is characterized in that, also be included in this semiconductor element is set before, form second metal level on this substrate or part resistance layer, and be connected with this semiconductor element electric.
15. the method for making according to claim 10 or 14 described semiconductor package parts is characterized in that, is dispersed with fluorescent material in this encapsulation material.
16. a bearing part comprises:
Substrate;
The resistance layer is located on this substrate, and is had opening, and to expose outside the surface of this substrate, the bore of this opening is towards this substrate surface convergent; And
The first metal layer is located on this resistance laminar surface.
17. bearing part according to claim 16 is characterized in that, this substrate is a silicon substrate.
18. bearing part according to claim 16 is characterized in that, the material that forms this first metal layer is silver, aluminium or nickel.
19. bearing part according to claim 16 is characterized in that, this first metal layer also is formed on the substrate surface in this opening, and has the fluting that exposes outside this substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106129427A CN102544304A (en) | 2010-12-21 | 2010-12-21 | Carrier, semiconductor package and manufacturing method for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106129427A CN102544304A (en) | 2010-12-21 | 2010-12-21 | Carrier, semiconductor package and manufacturing method for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102544304A true CN102544304A (en) | 2012-07-04 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010106129427A Pending CN102544304A (en) | 2010-12-21 | 2010-12-21 | Carrier, semiconductor package and manufacturing method for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102544304A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| CN2641835Y (en) * | 2003-06-17 | 2004-09-15 | 胜开科技股份有限公司 | Video image sensor |
| US20050156184A1 (en) * | 2004-01-16 | 2005-07-21 | Yu-Nung Shen | Light-emitting diode chip package body and packaging method thereof |
| CN1825640A (en) * | 2004-09-30 | 2006-08-30 | 晶元光电股份有限公司 | Semiconductor luminescent element composition |
-
2010
- 2010-12-21 CN CN2010106129427A patent/CN102544304A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| CN2641835Y (en) * | 2003-06-17 | 2004-09-15 | 胜开科技股份有限公司 | Video image sensor |
| US20050156184A1 (en) * | 2004-01-16 | 2005-07-21 | Yu-Nung Shen | Light-emitting diode chip package body and packaging method thereof |
| CN1825640A (en) * | 2004-09-30 | 2006-08-30 | 晶元光电股份有限公司 | Semiconductor luminescent element composition |
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| PB01 | Publication | ||
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120704 |