CN102542083A - Method for adjusting hierarchical unit ports based on connection relational tree - Google Patents
Method for adjusting hierarchical unit ports based on connection relational tree Download PDFInfo
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CN201010601518.2A CN102542083B (en) | 2010-12-23 | 2010-12-23 | Based on the Hierarchical Components port method of adjustment of annexation tree |
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CN201010601518.2A CN102542083B (en) | 2010-12-23 | 2010-12-23 | Based on the Hierarchical Components port method of adjustment of annexation tree |
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CN102542083A true CN102542083A (en) | 2012-07-04 |
CN102542083B CN102542083B (en) | 2015-12-02 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106777416A (en) * | 2015-11-20 | 2017-05-31 | 北京华大九天软件有限公司 | The other version comparison method present of the schematic diagram based on topological relation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6539525B1 (en) * | 1999-10-06 | 2003-03-25 | Samsung Electronics Co., Ltd. | Layout verifying method for integrated circuit device |
CN1760879A (en) * | 2005-11-10 | 2006-04-19 | 复旦大学 | Programmable method for automatic generating kernel domain |
CN1892661A (en) * | 2005-07-06 | 2007-01-10 | 北京中电华大电子设计有限责任公司 | Algorithm based on equivalence class to resolve short-circuit problem in IILVS |
US7464350B1 (en) * | 2006-08-11 | 2008-12-09 | Xilinx, Inc. | Method of and circuit for verifying a layout of an integrated circuit device |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6539525B1 (en) * | 1999-10-06 | 2003-03-25 | Samsung Electronics Co., Ltd. | Layout verifying method for integrated circuit device |
CN1892661A (en) * | 2005-07-06 | 2007-01-10 | 北京中电华大电子设计有限责任公司 | Algorithm based on equivalence class to resolve short-circuit problem in IILVS |
CN1760879A (en) * | 2005-11-10 | 2006-04-19 | 复旦大学 | Programmable method for automatic generating kernel domain |
US7464350B1 (en) * | 2006-08-11 | 2008-12-09 | Xilinx, Inc. | Method of and circuit for verifying a layout of an integrated circuit device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106777416A (en) * | 2015-11-20 | 2017-05-31 | 北京华大九天软件有限公司 | The other version comparison method present of the schematic diagram based on topological relation |
CN106777416B (en) * | 2015-11-20 | 2019-11-15 | 北京华大九天软件有限公司 | The other version comparison method present of schematic diagram based on topological relation |
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CN102542083B (en) | 2015-12-02 |
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Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Patentee after: Shenzhen Pango Microsystems Co., Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Patentee before: SHENZHEN PANGO MICROSYSTEMS CO., LTD. |