CN102541753B - A kind of read-write optimization method of in-line memory - Google Patents
A kind of read-write optimization method of in-line memory Download PDFInfo
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Abstract
A read-write optimization method for in-line memory, is applicable to eflash storer; A logical page (LPAGE) is corresponding with several sectors onesize on a Physical Page, set up the mapping relations of valid data and Physical Page sector on logical page (LPAGE).The data of actual storage are found to read according to mapping relations.When write operation, first read the data of actual storage, if full FF then writes direct; And if not full FF and a not in the end sector, current sector, then data are write in next sector, otherwise, all valid data of current logical page all should be read in SRAM, wipe corresponding Physical Page, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page; After more than having operated, upgrade mapping table.Optimization method of the present invention simplifies the read-write operation of eflash storer, effectively can improve the performance of file system, reduce the complexity of system simultaneously.
Description
Technical field
The present invention relates to a kind of method optimizing embedded Norflash memory read/write (hereinafter referred to as eflash), be particularly useful for the embedded software system setting up file system on eflash.
Background technology
Semiconductor memory can be divided into volatile storage and non-volatility memorizer two class, the data that can lose the memory of after volatile storage power down, even if non-volatility memorizer also can protected data when cutting off the electricity supply.ROM is non-volatility memorizer, and whether ROM can write data according to user and be divided into two classes in type, and a class is the ROM that user can write, and what another kind of Shi Shi manufacturer write in process is called as Mask ROM.In the ROM that user can write, relatively more conventional has EEPROM(Electrically Erasable Programmable ROM, EEPROM (Electrically Erasable Programmable Read Only Memo)) and eflash(Embedded Flash Memory, embedded flash memory).
Eflash is that EEPROM moves to maturity, and semiconductor technology evolves is to submicron technology, and the product of Large Copacity electrically-erasable storage requirement.The principle that it stores data is stored on floating gate electrode in the form of a charge.Compared with EEPROM, Flash has unrivaled superiority in integrated level; Its cellar area is only 1/4th of conventional EEPROM.EEPROM, because cost is high, demand is little, integrated level is low, has gradually by trend that eflash replaces.
Shortcoming after but eflash has in the application: on the one hand, eflash can not read and write by word; On the other hand, eflash can only perform erase operation with page unit, and one page is usually very large, has from 256 bytes according to different eflash models to 4K byte.In addition, before write operation is carried out to eflash, first must perform erase operation, and time required for erase operation is very long, generally can reach Microsecond grade.This can bring very large inconvenience in the application, adds the complicacy that file system realizes, and reduces system performance.
Summary of the invention
The object of the invention is to solve in application at present to the technological difficulties run into during eflash memory read/write, the read-write optimization method of a kind of more high-performance and eflash storer is more easily provided, making can as operation SRAM(static RAM to the read-write of eflash storer) simple, improve the performance of file system, reduce the complexity of system simultaneously.
Technical scheme of the present invention is to provide a kind of read-write optimization method of in-line memory, and described in-line memory is eflash; Described optimization method, comprises:
Several Physical Page are set in the primary memory space of eflash, each Physical Page are divided into several onesize sectors; Also several logical page (LPAGE)s are set in Virtual Space, make the size of a logical page (LPAGE) equal the size of a sector;
And, define a logical page (LPAGE) corresponding with a Physical Page, and the mapping relations valid data on this logical page (LPAGE) are mapped in the Physical Page corresponding to it on several sectors, that is: make logical page address equal physical page address, and on logical page (LPAGE), the offset address of valid data equal the offset address of each sector on this Physical Page;
Therefore according to described mapping relations, the concrete sector number of valid data on corresponding Physical Page on logical page (LPAGE) can be determined, and then according to this sector number, the operation that logic is read or logic is write is carried out to eflash.
Described optimization method, that carries out when being specifically included in initialization builds table handling, that is, in a SRAM, set up mapping relations table, determines and the sector number corresponding to valid data on logical page (LPAGE);
Build in table handling described, according to the offset address of valid data on a logical page (LPAGE), scan successively to first sector from last sector of corresponding Physical Page, obtain the data on the same offset address of each sector:
If the data obtained from one of them sector are not full FF, then this sector number is the mapping sector number of valid data on logical page (LPAGE), is the sector on logical page (LPAGE) corresponding to valid data in mapping relations table by this sector record;
If data are all full FF on this offset address of all sectors, then the mapping sector number setting these valid data on described logical page (LPAGE) is 0, is the sector on logical page (LPAGE) corresponding to valid data by first of this Physical Page sector record.
Described mapping relations table is a two-dimensional array Lut [m] [n] of setting up in described SRAM, and wherein m represents the logical page number (LPN) of each logical page (LPAGE) in eflash; N represents the logical number of valid data in a logical page (LPAGE); Described logical number is corresponding with the side-play amount of data in logical page (LPAGE) and respective sectors, and the minimum read-write unit of described side-play amount and described eflash matches;
The value of described two-dimensional array represents with s, represents the sector number corresponding to valid data.
Described optimization method is when carrying out logic read operation, according to the logical address that application program provides, calculate the logic number of pages at valid data place, and the side-play amount in this logical page (LPAGE), obtain the concrete sector number mapped on respective physical page by inquiring about described mapping relations table; Again according to described side-play amount, physical address corresponding with this logical address on the sector that calculating maps; Afterwards, the data on described physical address are read.
Described optimization method, when carrying out logical write operation, first reads the value of data in the logical address that provides of application program:
If the value read is full FF, then will newly be worth this physical address directly writing current mapping sector;
If the value read is not full FF, and current mapping sector is not last sector of described eflash, then new data write in the next sector of current sector, and upgrades mapping relations table;
If the value read is not full FF, and current mapping sector is last sector of described eflash, then valid data all on current logical page are all read in SRAM, the Physical Page that erasing is corresponding, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page, and upgrade mapping relations table.
In addition, described optimization method is when carrying out logical write operation, if the new value writing logical page (LPAGE) is full FF, which sector what then no matter map is, all valid data all in current logical page to be read in SRAM, the Physical Page that erasing is corresponding, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page, and upgrade mapping relations table.
The read-write optimization method of in-line memory of the present invention, its advantage is, by setting up the mapping relations between logical page data and number of physical pages certificate, make the read-write operation of eflash storer simply efficient, especially situation process can be divided when writing data, all need not carry out the erase operation of whole page in all cases, solve the technical matters in tradition application.Therefore, the present invention can improve the performance of file system, reduces the complexity of system simultaneously.
Accompanying drawing explanation
Fig. 1 is the process flow diagram building table handling in the read-write optimization method of in-line memory of the present invention;
Fig. 2 is the process flow diagram of logical write operation in the read-write optimization method of in-line memory of the present invention.
Embodiment
The present invention is the read-write optimization method that one is applicable to embedded Norflash storer (hereinafter referred to as eflash), first each Physical Page of eflash is divided into several onesize physical sectors, is usually convenient to counting and can be divided into 4 or 8 physical sectors.Make the corresponding logical page (LPAGE) of a Physical Page, meanwhile, a logical page (LPAGE) several onesize physical sectors corresponding are made, namely, data on same logical page (LPAGE) can be distributed in above the different sectors of same Physical Page, and the size of a logical page (LPAGE) equals the size of a physical sector.
The data that what application program was specifically accessed is on logical page (LPAGE), and the data on logical page (LPAGE) need the data that just can be corresponded to by specific mapping relations on real Physical Page.For this reason, define a kind of mapping relations efficiently in the present invention, that is, make logical page address equal physical page address, and on the logical page (LPAGE) that need access, the offset address of data equals the offset address of physical sector on this Physical Page; Therefore, in order to be mapped to number of physical pages certificate from logical page data, only need to find corresponding sector number, such as, certain sector number in 4 or 8 physical sectors.
Generally in use, during initialization, mapping relations table can be established in advance in a SRAM, determine the sector number of data on corresponding Physical Page on logical page (LPAGE).Each sector normally scanning corresponding Physical Page is from high to low in the data on same offset address: if find that data are not full FF, then this sector number is the mapping sector number of these data on logical page (LPAGE); If data are all full FF on this offset address finding all sectors, then the mapping sector number setting these data on logical page (LPAGE) is that 0(i.e. these data are corresponding with first sector).
When read operation, physically actual data only need be found to carry out reading by above-mentioned mapping relations.
Full FF when write operation, first finds physically actual data by above-mentioned mapping relations, if then can write direct; And if not full FF and a not in the end sector, current sector, then data are write and currently find in the next sector of sector, otherwise, all valid data of current logical page all should be read in SRAM in this case, wipe corresponding Physical Page, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page; After more than having operated, upgrade mapping table.
Conveniently explain content of the present invention, for a concrete eflash, set forth the read-write optimization method of eflash storer, in the present embodiment, last 32 pages of eflash, the physical space of totally 128 byte-sized are modeled to the EEPROM of 32K byte-sized, namely, each sector-size of described eflash is 1K byte, and the least unit of read-write is 16 bits.The function interface of application program by specifying, only needs to provide logical address, just as operation SRAM, can carry out read-write operation to eflash, without the need to being concerned about the problems such as erasing, page size.
Concrete grammar is, is designated as logical page number (LPN) page0 to page31 successively from small to large by last 32 pages of eflash, then eflash Physical Page is divided into 4 sectors, and label is from 0 to 3.Further, the valid data deposited in a logical page (LPAGE) are made to be the size (i.e. 1K byte) of a sector.Because eflash is 16, manage so storage inside management logic take half-word as least unit, the valid data namely in each logical page (LPAGE) have 512 half-words, and logical number is from 0 to 511.
The logical number of valid data on logical page (LPAGE), corresponding with corresponding half-word side-play amount in a sector, but it is uncertain that these data specifically leave which sector corresponding with logical page (LPAGE) in, this just needs to set up a mapping table in sram, records this half-word and is in which sector.Set up a two-dimensional array Lut [m] [n] in sram, in array, m represents logical page number (LPN), and size represents the logical number of valid data in one page from 0 to 31, n, and size is from 0 to 511; The value of array represents with s, corresponding sector number 0 ~ 3.The process setting up described two-dimensional array Lut [m] [n] is called and builds table handling by the present invention.
Process flow diagram when setting up mapping table shown in Figure 1, builds table from logical number n=0 of logical page (LPAGE) m=0, valid data.Be positioned at which sector to search valid data, should from the highest sector to minimum sector successively search, namely namely search successively from last sector (this example sector 3) to first sector (i.e. sector 0).If the value finding wherein respective offsets amount place, some sectors is not equal to 0xffff, then this sector is the sector at valid data place.If find sector 0 always, the value at respective offsets amount place is still 0xffff, then make Lut [m] [n]=0, and the mapping sector number namely setting these data on logical page (LPAGE) is 0.
Such as when setting up Lut [1] [0], search from 0 skew place (n=0) of last sector (i.e. s=3) of logical page (LPAGE) m=1, if the value finding 0 skew place of this sector 3 equals 0xffff, then 0 skew place forwarding sector 2 to starts to search, the like.And such as when the 0 skew place duration finding sector 1 is not equal to 0xffff, then the logical number of logical page (LPAGE) m=1 is 0 skew place that the data of n=0 are located in sector 1.And if until the value that 0 skew place of sector 0 checks in is still 0xffff, then made Lut [1] [0]=0.
The present invention, when reading eflash, needs the logical address provided to be transformed into the concrete physical address storing data.In the present invention, this operation is called that logic is read.Wherein, logical address refers to the virtual address of the EEPRM simulated, and address realm is from 0 to 32K; The value of logic number of pages m is calculated according to the logical address provided, with the value of data side-play amount n in this logical page (LPAGE), obtained the number value s of sector, valid data place by query mappings table, then physical address corresponding with described side-play amount in this sector carries out digital independent.
Process flow diagram shown in Figure 2, the present invention, when writing eflash, according to the logical address provided, first reads the data in this logical address, then divides four kinds of situation operations.In the present invention, this operation is called that logic is write.
The first situation, the value (being labeled as Dirty-Data in Fig. 2) read is 0xffff, directly newly will be worth (in Fig. 2, being labeled as NewData) and write origin-location in current mapping sector, namely, be written to the physical address calculated by this logical address in mapping sector, do not need the value changing mapping table.
The second situation, the value of reading is not 0xffff, and current mapping sector is not last sector of Physical Page, then new value write in the next sector of current sector, and in the mapping table mapping relations are updated to next sector.
The third situation, the value of reading is not 0xffff, and current mapping sector is last sector of Physical Page.Valid data all in current logical page all should be read in SRAM in this case, wipe the Physical Page corresponding to this logical page (LPAGE), the old value in SRAM on respective offsets position is replaced again by new value, finally all valid data after renewal in SRAM are write in first sector (i.e. sector 0) of corresponding Physical Page, and upgrade mapping table.
4th kind of situation, if the new value write is 0xffff, which sector regardless of current valid data mapping is, all valid data all in current logical page to be read in SRAM, wipe the Physical Page corresponding to this logical page (LPAGE), replace the old value in SRAM on respective offsets position by new value simultaneously, the more all valid data after upgrading in SRAM are write in first sector of corresponding Physical Page, and upgrade mapping table.
In sum, the read-write optimization method of in-line memory of the present invention, by setting up the mapping relations between logical page data and number of physical pages certificate, make the read-write operation of eflash storer simply efficient, especially situation process can be divided when writing data, all need not carry out the erase operation of whole page in all cases, solve the technical matters in tradition application.Therefore, the present invention can improve the performance of file system, reduces the complexity of system simultaneously.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a read-write optimization method for in-line memory, described in-line memory is eflash, it is characterized in that, described eflash be a kind of erase operation based on page and the Norflash storer of read-write operation based on word, described optimization method, comprises:
Several Physical Page are set in the primary memory space of eflash, each Physical Page are divided into several onesize sectors; Also several logical page (LPAGE)s are set in Virtual Space, make the size of a logical page (LPAGE) equal the size of a sector;
And, define a logical page (LPAGE) corresponding with a Physical Page, and the mapping relations valid data on this logical page (LPAGE) are mapped in the Physical Page corresponding to it on several sectors, that is: make logical page address equal physical page address, and on logical page (LPAGE), the offset address of valid data equal the offset address of each sector on this Physical Page;
Therefore according to described mapping relations, the concrete sector number of valid data on corresponding Physical Page on logical page (LPAGE) can be determined, and then according to this sector number, the operation that logic is read or logic is write is carried out to eflash;
Wherein, that carries out when described optimization method is specifically included in initialization builds table handling, that is, in a SRAM, set up mapping relations table, determines and the sector number corresponding to valid data on logical page (LPAGE);
Described optimization method, when carrying out logical write operation, first reads the value of data in the logical address that provides of application program:
If the value read is full FF, then will newly be worth the physical address directly writing current mapping sector;
If the value read is not full FF, and current mapping sector is not last sector of described eflash, then new data write in the next sector of current sector, and upgrades mapping relations table;
If the value read is not full FF, and current mapping sector is last sector of described eflash, then valid data all on current logical page are all read in SRAM, the Physical Page that erasing is corresponding, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page, and upgrade mapping relations table.
2. the read-write optimization method of in-line memory as claimed in claim 1, is characterized in that,
Build in table handling described, according to the offset address of valid data on a logical page (LPAGE), scan successively to first sector from last sector of corresponding Physical Page, obtain the data on the same offset address of each sector:
If the data obtained from one of them sector are not full FF, then this sector number is the mapping sector number of valid data on logical page (LPAGE), is the sector on logical page (LPAGE) corresponding to valid data in mapping relations table by this sector record;
If data are all full FF on this offset address of all sectors, then the mapping sector number setting these valid data on described logical page (LPAGE) is 0, is the sector on logical page (LPAGE) corresponding to valid data by first of this Physical Page sector record.
3. the read-write optimization method of in-line memory as claimed in claim 2, is characterized in that,
Described mapping relations table is a two-dimensional array Lut [m] [n] of setting up in described SRAM, and wherein m represents the logical page number (LPN) of each logical page (LPAGE) in eflash; N represents the logical number of valid data in a logical page (LPAGE); Described logical number is corresponding with the side-play amount of data in logical page (LPAGE) and respective sectors, and the minimum read-write unit of described side-play amount and described eflash matches;
The value of described two-dimensional array represents with s, represents the sector number corresponding to valid data.
4. the read-write optimization method of in-line memory as claimed in claim 3, is characterized in that,
Described optimization method is when carrying out logic read operation, according to the logical address that application program provides, calculate the logic number of pages at valid data place, and the side-play amount in this logical page (LPAGE), obtain the concrete sector number mapped on respective physical page by inquiring about described mapping relations table; Again according to described side-play amount, physical address corresponding with this logical address on the sector that calculating maps; Afterwards, the data on described physical address are read.
5. the read-write optimization method of in-line memory as claimed in claim 4, is characterized in that,
Described optimization method is when carrying out logical write operation, if the new value writing logical page (LPAGE) is full FF, which sector what then no matter map is, all valid data all in current logical page to be read in SRAM, the Physical Page that erasing is corresponding, and write after the value in SRAM is updated to up-to-date value and wipe in first sector of Physical Page, and upgrade mapping relations table.
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| CN103034456B (en) * | 2012-12-14 | 2015-09-02 | 南京南瑞继保电气有限公司 | Based on the implementation method of the virtual terminal that non-volatile SRAM stores |
| CN108319433B (en) * | 2018-03-19 | 2021-02-02 | 艾体威尔电子技术(北京)有限公司 | Storage management method for NOR Flash of small-memory single chip microcomputer |
| CN112181898B (en) * | 2020-09-23 | 2023-12-29 | 北京百汇安科技有限公司 | Embedded security file management system |
| CN113568579B (en) * | 2021-07-28 | 2022-05-03 | 深圳市高川自动化技术有限公司 | Memory, data storage method and data reading method |
| CN114265562B (en) * | 2021-12-27 | 2022-09-20 | 北京国腾创新科技有限公司 | File storage method and system based on flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637721A (en) * | 2003-12-30 | 2005-07-13 | 三星电子株式会社 | Address mapping method and mapping information managing method for flash memory, and flash memory using the same |
| CN101645043A (en) * | 2009-09-08 | 2010-02-10 | 成都市华为赛门铁克科技有限公司 | Methods for reading and writing data and memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1637721A (en) * | 2003-12-30 | 2005-07-13 | 三星电子株式会社 | Address mapping method and mapping information managing method for flash memory, and flash memory using the same |
| CN101645043A (en) * | 2009-09-08 | 2010-02-10 | 成都市华为赛门铁克科技有限公司 | Methods for reading and writing data and memory device |
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