CN102540535B - MVA liquid crystal display device - Google Patents
MVA liquid crystal display device Download PDFInfo
- Publication number
- CN102540535B CN102540535B CN201010615688.6A CN201010615688A CN102540535B CN 102540535 B CN102540535 B CN 102540535B CN 201010615688 A CN201010615688 A CN 201010615688A CN 102540535 B CN102540535 B CN 102540535B
- Authority
- CN
- China
- Prior art keywords
- liquid crystal
- mva
- tft
- via hole
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 43
- 239000004020 conductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims description 39
- 238000002161 passivation Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000003825 pressing Methods 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a MVA pixel structure and a liquid crystal display device comprising the same, wherein the MVA pixel structure is arranged on a substrate and comprises: the transparent conductive blocks are electrically connected with each other through a conductive material for the first via hole. The MVA pixel structure provided by the invention has the advantages that the electric potential is conducted to each transparent conductive (ITO) block between the domains through the conductive material for the via hole, the metastable-state domain is eliminated, the display unevenness caused by pressing and an electric field is eliminated, and the domain stability is finally realized. In addition, the conductive material is used for forming the storage capacitor, so that the pixel aperture ratio can be improved.
Description
Invention field
The present invention relates to a kind of MVA liquid crystal indicator.
Background technology
Liquid crystal indicator (LCD) is because it is lightweight, volume is little, thickness is thin, and oneself is used in various big-and-middle undersized terminal presentation facility widely.At present, market is developed towards the characteristic such as high-contrast, high brightness, low colour cast, fast response, wide angle of visibility for the performance requirement of liquid crystal indicator.The technology that can realize wide angle of visibility requirement at present mainly contains three kinds of modes: Twisted Nematic liquid crystal (TN) mixes wide viewing-angle film (WVF) liquid crystal indicator, copline switch mode (IPS) liquid crystal indicator, multi-domain vertical alignment (MVA, multi-domainvertical) liquid crystal indicator.Wherein MVA mode LCD is due to the superiority in production and display characteristic etc., becomes the liquid crystal indicator of main flow on market.
The liquid crystal indicator of MVA mode, when voltage close, namely pixel rope electrode and be 0 to the potential difference (PD) between straight electrode (also referred to as public electrode) time, liquid crystal molecule relative to base plan vertically orientation, when voltage is maximum, relative to base plan orientation abreast.In addition, in the liquid crystal indicator of MVA mode, being black display when voltage is closed, is white display when voltage is maximum.
In addition, in the liquid crystal indicator of MVA mode, in order to improve viewing angle characteristic, be mostly combined with the orientation cutting techniques (multidomain) of liquid crystal molecule.This orientation cutting techniques, refers to and liquid crystal layer is divided into zonule, changes the technology of vergence direction when liquid crystal molecule is orientated according to voltage in each zonule.Namely by control, liquid crystal molecule is in an area tilted to the right, is tilted to the left in other regions.The light quantity of picture entirety can be made thus average, can significantly suppress the color based on visual angle to change.The principle of aforementioned orientation cutting techniques, be such as when voltage is closed, the liquid crystal molecular orientation on border, each zonule is not orthogonal to base plan, but is in the state tilted to certain direction.
Homeotropic alignment (VA) liquid crystal molecule relies on the surperficial riveting of orientation rete effect to be surely vertically arranged in liquid crystal layer in liquid crystal cell.After apply electric field on the ITO pole plate of its both sides, liquid crystal molecule can deflect under electric field action, coordinates the setting of polaroid and backlight and creates optical path difference, and can realize display thus.The major advantage of MVA pattern is that contrast is high, and visual angle is wide.
In current MVA display mode, the farmland distribution dislocation after pressing is a problem anxious to be resolved.This farmland distribution inconsistent phenomenon is because metastable state farmland produces from black state to the change of white state.And metastable state farmland distributes due to the entanglement of fringing field, be mainly present in the coupling part of electrically conducting transparent block (ITO).Pressing display uneven (push mura) can be regarded as the farmland distribution dislocation after external force applying.This image retention (image stick) that not common electrode DC to a certain extent also can be caused to remain cause.At present, common MVA dot structure is that the electrically conducting transparent block on each farmland is connected to each other.So just cause farmland distribution problem of misalignment.Common solution adopts rotatory polarization sheet, and metastable like this farmland would not be seen by human eye.Fig. 1 is the MVA pattern pixel structural representation of prior art.101 is electrically conducting transparent block (ITO), and it is made up of the connection electrically conducting transparent block 104 between three electrically conducting transparent block (ITO) 101a, 101b, 101c and three conducting blocks; 102 is projections (rib) of colored filter side; 103 is via hole and memory capacitance region.Three electrically conducting transparent block (ITO) 101a, 101b, 101c correspondences form three farmlands, there is the electrically conducting transparent block (ITO) 104 of connection, material is thus formed metastable state farmland between each farmland.Farmland distribution dislocation will be formed when pushed, finally can cause pressing display uneven (push mura) and image retention (imagestick).
Summary of the invention
The technical problem to be solved in the present invention is, the MVA dot structure of prior art has metastable state farmland.
Invention thinking of the present invention is, removes in prior art in pixel between multiple ITO block, be positioned at same layer with the plurality of ITO block link; Can be independent of one another at same layer between multiple ITO block, but carry out connecting with conductive material by the via hole in the insulation course below it; So just, eliminate the metastable state farmland problem of the MVA dot structure of prior art.
In order to solve the problems of the technologies described above, the invention provides a kind of MVA liquid crystal indicator, comprising infrabasal plate, the upper substrate just described infrabasal plate arranged and the liquid crystal layer clamped between described infrabasal plate and described upper substrate;
Described MVA liquid crystal indicator also comprises the MVA dot structure be arranged on described infrabasal plate, described MVA pixel comprises: at least two electrically conducting transparent blocks, insulation course is provided with between described electrically conducting transparent block and described substrate, described insulation course has the first via hole, is electrically connected between described each electrically conducting transparent block by described first via hole conductive material; Described upper substrate is provided with colored filter in the face of the side of described liquid crystal layer and is arranged at the projection on described colored filter; Described projection is perpendicular to described upper substrate direction is projected as circle.
As one preferred embodiment, described insulation course comprises gate insulator and passivation layer.Described MVA dot structure also comprises the thin film transistor (TFT) as pixel switch, the through described passivation layer of described first via hole, and described conductive material is source metal, and described source metal is identical with the material of described thin film transistor (TFT) source electrode and be in same layer.
For this preferred implementation, the source/drain of described thin film transistor (TFT) can be connected with described electrically conducting transparent block by described first via hole; Also can be connected with described electrically conducting transparent block by via hole independent in addition; Can also directly be connected with described conductive material.
Further, described MVA dot structure also comprises the public electrode of the overlapping generation memory capacitance with described conductive material; Utilize conductive material to form memory capacitance like this, as long as it is just passable just can to prepare separately or prepare less memory capacitance, improve aperture opening ratio.Gap area between adjacent described electrically conducting transparent block also can be used for generating memory capacitance, provides aperture opening ratio further.
As another preferred embodiment, described insulation course comprises gate insulator and passivation layer.Described MVA dot structure also comprises the thin film transistor (TFT) as pixel switch, the through described passivation layer of described first via hole and described gate insulator, described conductive material is gate metal, and described gate metal is identical with the material of described thin-film transistor gate and be in same layer.
For this preferred implementation, the source/drain of described thin film transistor (TFT) can be connected with described electrically conducting transparent block by described first via hole; Also can be connected with described electrically conducting transparent block by via hole independent in addition; Or the source/drain of described thin film transistor (TFT) can also be connected with described conductive material by the second independent in addition via hole.
Compared with prior art, advantage and the beneficial effect of MVA liquid crystal indicator of the present invention are: by via hole conductive material (source metal or gate metal as thin film transistor (TFT)), current potential is led each ITO block between farmland and farmland, eliminate metastable state farmland, and then eliminate pressing and the display that causes of electric field is uneven, finally achieve farmland stable.In addition, utilize this conductive material to form memory capacitance and can improve pixel aperture ratio.
Accompanying drawing explanation
Accompanying drawing shows embodiments of the invention, and together with instructions, is used for explaining principle of the present invention.By the detailed description done below in conjunction with accompanying drawing, can more clearly understand object of the present invention, advantage and feature, wherein:
Fig. 1 is a kind of MVA dot structure schematic diagram of prior art;
Fig. 2 is the MVA dot structure schematic diagram of the embodiment of the present invention 1;
Fig. 3 is the AA ' diagrammatic cross-section of Fig. 2;
Fig. 4 is the BB ' diagrammatic cross-section of Fig. 2;
Fig. 5 is the MVA dot structure schematic diagram of the embodiment of the present invention 2;
Fig. 6 is the AA ' diagrammatic cross-section of Fig. 5;
Fig. 7 is the BB ' diagrammatic cross-section of Fig. 5;
Fig. 8 is the MVA dot structure schematic diagram of the embodiment of the present invention 3;
Fig. 9 is the AA ' diagrammatic cross-section of Fig. 8;
Figure 10 is the BB ' diagrammatic cross-section of Fig. 8;
Figure 11 is the MVA dot structure schematic diagram of the embodiment of the present invention 4;
Figure 12 is the AA ' diagrammatic cross-section of Figure 11;
Figure 13 is the BB ' diagrammatic cross-section of Figure 11;
Figure 14 is the embodiment MVA dot structure schematic diagram with 2 electrically conducting transparent blocks provided by the invention.
Embodiment
For describing technology contents of the present invention and structural attitude in detail, accompanying drawing is coordinated to be described in detail below in conjunction with embodiment.
Embodiment 1
Consult Fig. 2 and 3, in embodiment 1, MVA dot structure of the present invention, is arranged on an infrabasal plate (not shown in FIG.), just this infrabasal plate is provided with upper substrate 210; Liquid crystal layer 213 is clamped with between infrabasal plate and upper substrate 210.The projection 202 that upper substrate 210 is provided with colored filter (not shown in FIG.) in the face of the side of liquid crystal layer 213 and is arranged on this colored filter.
The pixel electrode of each MVA pixel comprises three electrically conducting transparent blocks 201 (can adopt ITO), and in colored filter side, corresponding each electrically conducting transparent block 201 arranges a projection 202.The molecule of the liquid crystal layer 213 between each like this electrically conducting transparent block 201 from its corresponding projection 202 presents different tendencies, forms farmland.
Be provided with insulation course 212 between electrically conducting transparent block 201 and infrabasal plate, insulation course 212 has via hole 204, is electrically connected between each electrically conducting transparent block 201 by the via hole 204 in insulation course 212 with conductive material 203.Obviously can find out in composition graphs 2 and Fig. 4, between three electrically conducting transparent blocks 201, with electrically conducting transparent block 201 same layer in there is no link, be independently each other in same layer; Just by being electrically connected with the conductive material 203 that electrically conducting transparent block 201 is positioned at different layers.Thus, the metastable state between farmland and farmland can just be eliminated.
As one preferred embodiment, the projection 202 that the via hole 204 of each electrically conducting transparent block 201 correspondence is corresponding with this electrically conducting transparent block 201 is just to setting.As shown in Figures 2 and 3, look up from perpendicular to pixel planes side, together with via hole 204 overlaps on completely with projection 202.Do like this and can save aperture opening ratio.In fact, via hole 204 and projection 202 also can not just to settings, but make all can loss aperture opening ratio perpendicular to via hole on pixel planes direction and printing opacity direction 204 and projection 202 like this.
As one preferred embodiment, conductive material 203 can adopt metal material.
Embodiment 2
As shown in Figure 5, the pixel region of each MVA pixel is defined by sweep trace 206 and data line 207; Each MVA pixel has the thin film transistor (TFT) (TFT) as pixel switch.This thin film transistor (TFT) (TFT) is arranged on infrabasal plate 211, comprises the grid be positioned on infrabasal plate, the gate insulator 208 be positioned on grid, the polysilicon layer be positioned on gate insulator 208, the source-drain electrode be positioned on polysilicon layer, the passivation layer 209 be positioned on source-drain electrode.The grid of this thin film transistor (TFT) (TFT) is connected with sweep trace 206, and its drain/source is connected with data line 207, and its source/drain is electrically connected with electrically conducting transparent block 201.Generally, the grid of this thin film transistor (TFT) (TFT) is identical with the material of sweep trace 206 and be in same layer; The source electrode of this thin film transistor (TFT) (TFT), drain electrode is identical with data line 207 material and be in same layer.
As one preferred embodiment, embodiment 2 is on the basis of embodiment 1, and insulation course 212 comprises gate insulator 208 and passivation layer 209; Via hole 204 runs through gate insulator 208 and passivation layer 209 (as shown in Figure 6, Figure 7).Conductive material 203 is positioned at the intersection of gate insulator 208 and infrabasal plate 211.Conductive material 203 can select gate metal, and namely conductive material 203 can be identical with the grid material of thin film transistor (TFT) (TFT) and be in same layer; Grid and the sweep trace 206 of such conductive material 203 and thin film transistor (TFT) (TFT) just can complete in same procedure, have saved cost.
In embodiment 2, source/drain and the electrically conducting transparent block 201 of thin film transistor (TFT) (TFT) are electrically connected can in the following way: the source/drain of thin film transistor (TFT) (TFT) is connected with electrically conducting transparent block 201 by the via hole in passivation layer 209, this via hole can be same with via hole 204, also can open via hole again in the region in passivation layer 209 outside via hole 204; Or the source/drain of thin film transistor (TFT) (TFT) is connected with conductive material 203 by via hole in gate insulator 208, and this via hole can be same with via hole 204, also can open via hole again in the region in gate insulator 208 outside via hole 204.
Embodiment 3
As shown in Figure 8, the pixel region of each MVA pixel is defined by sweep trace 206 and data line 207; Each MVA pixel has the thin film transistor (TFT) (TFT) as pixel switch.This thin film transistor (TFT) (TFT) is arranged on infrabasal plate 211, comprises the grid be positioned on infrabasal plate, the gate insulator 208 be positioned on grid, the polysilicon layer be positioned on gate insulator 208, the source-drain electrode be positioned on polysilicon layer, the passivation layer 209 be positioned on source-drain electrode.The grid of this thin film transistor (TFT) (TFT) is connected with sweep trace 206, and its drain/source is connected with data line 207, and its source/drain is electrically connected with electrically conducting transparent block 201.Generally, the grid of this thin film transistor (TFT) (TFT) is identical with the material of sweep trace 206 and be in same layer; The source electrode of this thin film transistor (TFT) (TFT), drain electrode is identical with data line 207 material and be in same layer.
As one preferred embodiment, embodiment 3 is on the basis of embodiment 1, and insulation course 212 comprises gate insulator 208 and passivation layer 209; Via hole 204 runs through passivation layer 209, is positioned at the intersection (as shown in Figure 9, Figure 10) of gate insulator 208 and passivation layer 209.Conductive material 203 can select source/drain metal, and namely conductive material 203 can be identical with the source-drain electrode material of thin film transistor (TFT) (TFT) and be in same layer; Source-drain electrode and the data line 207 of such conductive material 203 and thin film transistor (TFT) (TFT) just can complete in same procedure, have saved cost.
In embodiment 3, source/drain and the electrically conducting transparent block 201 of thin film transistor (TFT) (TFT) are electrically connected can in the following way: the source/drain of thin film transistor (TFT) (TFT) is connected with electrically conducting transparent block 201 by the via hole in passivation layer 209, this via hole can be same with via hole 204, also can open via hole again in the region in passivation layer 209 outside via hole 204; Or the source/drain of thin film transistor (TFT) (TFT) is directly connected with conductive material 203, because the source-drain electrode of conductive material 203 and thin film transistor (TFT) (TFT) and data line 207 are in same layer, the source/drain of thin film transistor (TFT) (TFT) is directly connected with conductive material 203 and is more prone to realize.
Embodiment 4
As shown in Figure 11, Figure 12 and Figure 13, embodiment 4 is on the basis of embodiment 3, increases one deck public electrode 205 at gate insulator 208 and the intersection of infrabasal plate 211.This public electrode 205 is overlapping on printing opacity direction with conductive material 203, forms memory capacitance.Utilize public electrode 205 and the overlapping formation memory capacitance of conductive material 203 like this, as long as memory capacitance need not be prepared in addition or prepare less memory capacitance in addition, save aperture opening ratio.
Public electrode 205 and conductive material 203 can part overlapping, also can be completely overlapping, the size according to the memory capacitance that will be formed sets.
Public electrode 205 and conductive material 203 can also gap area between each electrically conducting transparent block 201 overlapping, form memory capacitance.
Public electrode 205 can with the grid of thin film transistor (TFT) (TFT) and sweep trace 206 material phase, such three is all in same layer, can complete, saved cost in same procedure.
The number of the electrically conducting transparent block 201 that the pixel electrode of each pixel in embodiment 1,2,3 and 4 has is 3.Electrically conducting transparent block in MVA dot structure provided by the invention can also adopt 2 (as shown in figure 14), also can be the integers such as 4,5 or 6.MVA dot structure shown in Figure 14 is the preferred embodiments of the present invention, adopts 2 electrically conducting transparent blocks, namely forms two liquid crystal farmlands.Such design can reduce memory capacitance to greatest extent, and then improves aperture opening ratio.If when in concrete product design, memory capacitance is large not, the gap area 214 between 2 electrically conducting transparent blocks can be utilized to do memory capacitance, by conductive material 203 and public electrode 205 all overlay areas 214, the two is overlapping formation memory capacitance in region 214.
These are only the preferred embodiments of the present invention, be not limited to the present invention.In the above-described embodiments, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a MVA liquid crystal indicator, comprises infrabasal plate, the upper substrate just arranged described infrabasal plate and the liquid crystal layer clamped between described infrabasal plate and described upper substrate;
Described MVA liquid crystal indicator also comprises the MVA dot structure be arranged on described infrabasal plate, described MVA dot structure comprises: at least two electrically conducting transparent blocks, insulation course is provided with between described electrically conducting transparent block and described substrate, described insulation course has the first via hole, is electrically connected between described each electrically conducting transparent block by described first via hole conductive material;
Described upper substrate is provided with colored filter in the face of the side of described liquid crystal layer and is arranged at the projection on described colored filter; Described projection is perpendicular to described upper substrate direction is projected as circle.
2. MVA liquid crystal indicator according to claim 1, is characterized in that, described insulation course comprises gate insulator and passivation layer.
3. MVA liquid crystal indicator according to claim 2, it is characterized in that, described MVA dot structure also comprises the thin film transistor (TFT) as pixel switch, the through described passivation layer of described first via hole, described conductive material is source/drain metal, and described source/drain metal is identical with the material of described thin film transistor (TFT) source-drain electrode and be in same layer.
4. MVA liquid crystal indicator according to claim 3, is characterized in that, the source/drain of described thin film transistor (TFT) is connected with described electrically conducting transparent block by described first via hole; Or the source/drain of described thin film transistor (TFT) is directly connected with described conductive material.
5. MVA liquid crystal indicator according to claim 3, is characterized in that, described MVA dot structure also comprises the public electrode of the overlapping generation memory capacitance with described conductive material.
6. MVA liquid crystal indicator according to claim 5, is characterized in that, the gap area between adjacent described electrically conducting transparent block generates memory capacitance.
7. MVA liquid crystal indicator according to claim 2, it is characterized in that, described MVA dot structure also comprises the thin film transistor (TFT) as pixel switch, the through described passivation layer of described first via hole and described gate insulator, described conductive material is gate metal, and described gate metal is identical with the material of described thin-film transistor gate and be in same layer.
8. MVA liquid crystal indicator according to claim 7, is characterized in that, the source/drain of described thin film transistor (TFT) is connected with described electrically conducting transparent block by described first via hole; Or the source/drain of described thin film transistor (TFT) is connected with described conductive material by the second via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010615688.6A CN102540535B (en) | 2010-12-27 | 2010-12-27 | MVA liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010615688.6A CN102540535B (en) | 2010-12-27 | 2010-12-27 | MVA liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102540535A CN102540535A (en) | 2012-07-04 |
| CN102540535B true CN102540535B (en) | 2015-03-04 |
Family
ID=46347777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010615688.6A Active CN102540535B (en) | 2010-12-27 | 2010-12-27 | MVA liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102540535B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105372881B (en) * | 2015-12-01 | 2018-04-20 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1544987A (en) * | 2003-11-24 | 2004-11-10 | 友达光电股份有限公司 | Transistor liquid crystal display with multi-domain perpendicular direction matching mode |
| CN1677179A (en) * | 2004-03-31 | 2005-10-05 | 富士通显示技术株式会社 | Liquid crystal display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100460964C (en) * | 2004-05-18 | 2009-02-11 | 夏普株式会社 | Liquid crystal display and electronic device having same |
| JP4649916B2 (en) * | 2004-09-03 | 2011-03-16 | セイコーエプソン株式会社 | Liquid crystal display device, electronic equipment |
| US7995170B2 (en) * | 2005-03-23 | 2011-08-09 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| TWI333110B (en) * | 2006-10-16 | 2010-11-11 | Au Optronics Corp | Multi-domain vertically alignment liquid crystal display panel |
| WO2008096638A1 (en) * | 2007-02-08 | 2008-08-14 | Sharp Kabushiki Kaisha | Liquid crystal display |
-
2010
- 2010-12-27 CN CN201010615688.6A patent/CN102540535B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1544987A (en) * | 2003-11-24 | 2004-11-10 | 友达光电股份有限公司 | Transistor liquid crystal display with multi-domain perpendicular direction matching mode |
| CN1677179A (en) * | 2004-03-31 | 2005-10-05 | 富士通显示技术株式会社 | Liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102540535A (en) | 2012-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10088720B2 (en) | TFT array substrate and display device with tilt angle between strip-like pixel electrodes and direction of initial alignment of liquid crystals | |
| CN102566157B (en) | Array substrate and liquid crystal display | |
| JP3885122B2 (en) | High aperture ratio and high transmittance liquid crystal display device from which color shift is removed | |
| CN103529607B (en) | A kind of liquid crystal display panel, display device and its driving method | |
| JP5301605B2 (en) | Liquid crystal display | |
| US9019454B2 (en) | Liquid crystal display | |
| EP2778776A1 (en) | Liquid crystal display | |
| CN105549236A (en) | Switchable peep-proof device, preparation method thereof and display device | |
| KR20140042716A (en) | Display device and electronic equipment | |
| CN111208676B (en) | Liquid crystal display panel and liquid crystal display device | |
| CN103488002A (en) | Pixel electrode, array substrate and display device | |
| CN104865766A (en) | Pixel structure of multi-domain vertical alignment type liquid crystal | |
| CN204166255U (en) | A kind of display panel and display device | |
| US20180067345A1 (en) | Liquid crystal display panel with adjustable viewing angle and method for adjusting the viewing angle thereof | |
| CN215813614U (en) | Display panel with switchable wide and narrow viewing angles and display device | |
| CN103412447A (en) | Liquid crystal display (LCD) panel and display device | |
| CN102629042A (en) | Thin film transistor-liquid crystal display (TFT-LCD) array substrate and display device | |
| US20120001840A1 (en) | Liquid crystal display device | |
| CN103529606B (en) | A kind of liquid crystal display panel and display device | |
| CN101634767B (en) | Active driven liquid crystal display | |
| CN105487304B (en) | Liquid crystal display device with a light guide plate | |
| CN104423106A (en) | Liquid crystal display | |
| US20110317118A1 (en) | Liquid crystal display device | |
| CN102540535B (en) | MVA liquid crystal display device | |
| CN102998857B (en) | Slit electrode, array substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |