CN102523455A - Multi-thread arithmetic coding circuit and method based on standard JPEG 2000 - Google Patents

Multi-thread arithmetic coding circuit and method based on standard JPEG 2000 Download PDF

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CN102523455A
CN102523455A CN2012100005059A CN201210000505A CN102523455A CN 102523455 A CN102523455 A CN 102523455A CN 2012100005059 A CN2012100005059 A CN 2012100005059A CN 201210000505 A CN201210000505 A CN 201210000505A CN 102523455 A CN102523455 A CN 102523455A
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index
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CN102523455B (en
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郝跃
邸志雄
逄杰
史江义
马佩军
田映辉
龚章芯
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Xidian University
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Abstract

The invention discloses a multi-thread arithmetic coding circuit and method based on the standard JPEG 2000 and mainly aims to solve the problem of large area, low encoding efficiency and low throughput of a conventional multi-context arithmetic coder. The coding circuit is characterized in that under the premise of ensuring that the compression result is identical with that of the standard JPEG 2000, a command generating subunit, a command register and a comparator are introduced to a command generating and index forecasting unit' in the arithmetic coder, and the comparator is used for generating a 'command for controlling the thread coding mode; and simultaneously, an interval adjustment selector, a probability estimate selector and an index selector are controlled according to the command value to allocate the last coding result to the current to-be-coded thread, so that the logic complexity is reduced. Besides, according to the invention, LUTs (lookup tables) are split and expanded, wherein the primary LUT stores all possible index values, and the secondary LUT only stores probability estimate value. The simulation result shows that the invention has the characteristics of small area and high throughput and can be applied to high-performance image processing chips.

Description

Multithreading arithmetic coding circuit and method based on the JPEG2000 standard
Technical field
The invention belongs to microelectronics technology, relate to chip design, particularly a kind of coding method and circuit structure that meets the arithmetic encoder of JPEG2000 standard is mainly used in digital image coding chip design field.
Background technology
JPEG2000 has been widely applied to a plurality of fields such as the Internet, image transmission as Static Compression coding standard of new generation.Compare with traditional JPEG, JPEG2000 has compression effectiveness and good anti-error code capacity efficiently, and it supports quality scalability, resolution flexible property, encoding region of interest, and in same framework, supports harmless and lossy compression method simultaneously.
The embedded block encoding algorithm EBCOT that the JPEG2000 algorithm is mainly blocked by wavelet transform DWT, optimization, quantification, Bit-Plane Encoding, arithmetic encoder MQ and these several modules of code stream control are formed.Wherein wavelet transformation and block encoding technique have improved the anti-error code capacity of the code stream of image encoding generation; And interior embedding technique provides possibility for code stream control flexibly, promptly can realize can't harm, diminishing the compatibility of image compression.Bit-Plane Encoding and arithmetic encoder MQ are 2 higher modules of complexity among the JPEG2000, and the time of these 2 resume module has spent the over half of whole scramble time.Current Bit-Plane Encoding processing speed has far surpassed the speed of arithmetic encoder MQ; Bit-Plane Encoding can walk abreast produce many to context data; And arithmetic encoder MQ algorithm is because it is to the dependence between the context coding result; Can only each context data of serial process, so the code rate of arithmetic encoder MQ has become the key point of restriction JPEG2000 processing speed.
In JPEG2000, the MQ encoder is used for reading in code block context CX and the binary decision D that the Bit-Plane Encoding module produces, and obtains the data compression code stream CD of each independent code block coefficient then through coding.Its encryption algorithm mainly by search index and probability Estimation value table, heavily these three steps of normalization and code stream output are formed.
Index and probability Estimation value table are the look-up table of a two-stage: the first order is a concordance list, and the second level is probability Estimation value table.In JPEG2000,0-18 totally 19 possible context CX are arranged.The concordance list of the first order is the whole look-up table of a dynamic adjustable, deposits 19 context CX present clock periods corresponding index value separately.Wherein, each CX is to there being 47 different index values.And partial probability Estimation value table is fixing immutable look-up table, deposits totally 29 of the pairing next one of index value big probability index value NMPS (6bit) and next small probability index value NLPS (6bit), an exchange SWITCH (1bit) and probability Estimation value Qe (16bit).The context CX of the current reception of MQ encoder is searching of process two-stage successively, obtains correct probability Estimation value Qe.
In the MQ arithmetic encoder, adjust the width that register A representes current subinterval with the interval, code registers C representes the original position in subinterval.Wherein interval adjustment register A is 16bit, and code registers C is 28bit.After obtaining correct probability Estimation value Qe,, interval adjustment register A and code registers C are carried out normalization based on the difference between the code area.Wherein, interval adjustment register A is updated to A-Qe or Qe, and code registers C is updated to C+Qe or keeps.For the span that makes interval adjustment register A remains on [0.75,0.5], it is constantly moved to left.Each interval adjustment register A moves to left one the time, and built-in counter CT is subtracted 1 operation, when A >=0x8000, stops interval adjustment register A is moved to left.When register A moved to left, the code registers C identical figure place that also moves to left when CT=0, stopped displacement, and the high position of code registers C is exported as packed data CD.
In traditional M Q coding method; Realize according to the JPEG2000 standard fully; Not making full use of hardware circuit can parallel computing characteristics, can only realize serial code, and a clock cycle is handled a context CX; As number being 03129690.4 patent application, number for the patent application of 200410026019.X be exactly this.In recent years, in more existing papers, circuit structure and method that some can parallel processing a plurality of context CX have been proposed.Like Dyer a kind of circuit structure is proposed in paper " Concurrency techniques for arithmetic Coding in JPEG2000 ", can be at two context CX of a clock cycle parallel processing.Though code efficiency and aspect of performance at circuit have had certain improvement; But the problem that still has two aspects: first; This technology is in order to handle a plurality of context CX; Increase a large amount of MUXs and memory cell, increased circuit area and logical complexity to a certain extent; The second, if interval adjustment register A carries out that carry digit is not zero in the normalization operation, then the calculating of context CX will pause, and makes the treatment effeciency of circuit receive certain restriction in this technology.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art; A kind of coding method of multithreading arithmetic encoder and coding circuit based on the JPEG2000 standard proposed; With under the prerequisite that does not change coding result, make full use of the relation between the context CX, reduced index value and probability Estimation value search procedure; Reduce the quantity of MUX and memory cell, reduce circuit area and logical complexity; Adjust heavily normalization computational process, make that circuit can not pause, and promotes code efficiency and throughput when interval adjustment register A carry digit was not zero yet.
For realizing above-mentioned purpose, the present invention is based on the multithreading arithmetic coding circuit of JPEG2000 standard, comprising:
Instruction generates and the index predicting unit; It comprises instruction and generates subelement, command register instr and index predictor unit; This instruction generates subelement according to the judged result that whether equates in twos between the context CX of all threads; Write command register instr, the wherein corresponding context CX of each thread; This command register instr is used for controlling searching and the interval normalization of adjusting register A of index and normalization unit concordance list; This index predictor unit is used to predict the index transient state value of each context CX;
Index is selected and the normalization unit, and it comprises data allocations subelement and thread-data stream subelement; This data allocations subelement is used for distributing the coding result of its required preceding context CX_dff to each thread, and coding result comprises index value index_dff, probability Estimation value Qe_dff and interval adjustment register A_dff; This thread-data stream subelement is used for according to the value of data allocations subelement distribution and the value of command register instr; Select index value and the probability Estimation value Qe of the context CX of current each thread; The heavily normalization of computation interval adjustment register A a, wherein corresponding context CX of each thread as a result then;
Code registers normalization unit, it comprises code registers C and returns a beggar unit; This is returned a beggar unit and is used for the heavily normalization to code registers C;
The code stream output unit is used for the heavily normalization result according to code registers C, and output meets the code stream of JPEG2000 standard.
Described instruction generates in the subelement and contains comparator and command register instr; Whether comparator is used to judge between current each context CX and equates, and whether current each context CX equates with preceding once all context CX_dff respectively in twos in twos; If total number of threads is n, then comparator sum T does Individual; Command register instr bit wide value W satisfies relation by Thread Count n decision
Figure BDA0000128452860000032
Wherein low
Figure BDA0000128452860000033
Whether bit representes between current each context CX in twos equal relation, high n 2Bit representes whether each context CX equates with preceding once all context CX_dff respectively in twos in current each thread.
Described data allocations subelement comprises 3 class selectors, interval adjustment selector a_mux, probability Estimation selector q_mux and index selector i_mux; Wherein selector, 1 probability Estimation selector and 1 index selector are adjusted in corresponding 1 interval of each thread; The heavily normalization of the interval adjustment register A that the interval input signal of adjusting selector is preceding once all context CX_dff is A_dff as a result, and the output signal is the thread control signal a_pre that distributes to this thread; Probability Estimation selector input signal is the probability Estimation value Qe_dff of preceding once all context CX_dff, and the output signal is the possible probable value qe_pre that distributes to this thread; Index selector input signal is the index value i_dff of preceding once all context CX_dff, and the output signal is the possible index value i_pre that distributes to this thread; The control signal of interval adjustment selector, probability Estimation selector and index selector is the output signal of command register instr.
The look-up table that contains a two-stage in the described index predictor unit, all threads are all shared this look-up table; The address of data is current context CX in the first order look-up table; The content of data be index value, next time big probability environment, next time small probability environment and big next time probability environment and next time the next stage of small probability environment arrive the probability environment of next (n-1) level successively, wherein n is a total number of threads; The bit wide DW=6 of data * (2 N+1-1), wherein n is a total number of threads; The address of data is the lookup result of first order look-up table in the look-up table of the second level, and the content of data is probability Estimation value Qe, and data bit width is 16.
To achieve these goals, the present invention is based on the multithreading arithmetic coding method of JPEG2000 standard, comprising:
1) instruction generates step:
1a) comparator in the use instruction generation subelement carries out in twos all context CX of a current n thread; Corresponding context of each thread wherein; Corresponding context of each thread wherein; In in the corresponding command register of the 2nd thread the 0th, corresponding the 1st and the 2nd of the 3rd thread, the 3rd, 4 and 5 of the 4th thread correspondence; If comparative result equates, then with command register instr [C n 2-1:0] in the position corresponding bit position 1, otherwise put 0;
1b) current context CX and preceding once all context CX_dff are compared in twos corresponding context of each thread wherein, i the high n of thread correspondence command register 2[C in the bit n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position, n 2Be the number of times that current context and a preceding context are compared in twos, n is a total number of threads, i ∈ [1, n], and i is an integer; If comparative result equates, then with the high n of command register instr 2Corresponding bit position 1 in the position, otherwise put 0;
2) index prediction steps:
At first search first order look-up table according to current context, for i thread, lookup result is index transient state value, arrives down i time big probability coding environment and small probability coding environment, 2i+1 value altogether successively next time; Whether equate with coding environment MPS [j] according to data to be encoded D [j] then, from the result of first order look-up table, confirm j time probability encoding sign down; If equate, then descend j time probability encoding sign to confirm as big probability coding environment; If do not wait, then descend j time probability encoding sign to confirm as the small probability coding environment; Index prediction steps final result is index transient state value, arrives down i time probability encoding sign next time, is total to i+1 value; Wherein, j gets all integers from 1 to i, i ∈ [1, n], and i is an integer, n is a total number of threads;
3) index is confirmed and the normalization step:
3a) use data allocations subelement is given each current thread according to the value of command register with preceding once contextual index value, probability Estimation value and interval adjustment its registers, and allocation result is possible index value, possibility probable value and thread controlling value;
3b) according to possibility index value, possibility probable value and thread controlling value, confirm the index value of each thread: for i thread, at first whether equal zero the position of decision instruction register [2i (i-1)+i, 2i (i-1)]; If equal zero, then this thread index value is an index transient state value; Otherwise, confirm index value according to the thread controlling value and the magnitude relationship of possibility probable value: if a_pre>=i * qe_pre+2 15, then this thread index value is a possible index value; Otherwise, judge a_pre>=l * qr_pre+2 15Whether set up, if set up, then index value is (i-l) inferior probability encoding sign down, if be false, then carries out circulation: l from subtracting 1, judges a_pre>=l * qe_pre+2 15Whether set up, as if setting up, then jump out circulation, if be false, then circulation, wherein the l initial value is (i-1) if continuing, span is [i-1,0], and a_pre is the thread controlling value, and qe_pre is a possible probable value, i ∈ [1, n], and i is an integer, n is a total number of threads;
The index value that 3c) obtained according to a last step is searched second level look-up table, obtains the probability Estimation value Qe of current context CX;
4) the adjustment register normalization step of first thread:
At first computation interval is adjusted the register A first intermediate variable A1=A-Qe; According to the highest two value of the A first intermediate variable A1, the A first intermediate variable A1 is moved to left then, obtain the A second intermediate variable A2: as if the highest two value of A intermediate variable A1 is 3 or 2, then the A second intermediate variable A2=A1; As if the highest two value of the A first intermediate variable A1 is 1, then A second intermediate variable A2=A1＜＜1; As if the highest two value of the A first intermediate variable A1 is 0, then A intermediate variable A2=A1＜＜2; Use formula selection marker sel to confirm the heavy normalized value of interval adjustment register at last: when the value of formula selection marker sel was 1, heavily normalization result was A2; Otherwise heavily normalization result is Qe;
5) the code registers normalization step of first thread:
At first, the calculation code register C first intermediate variable C1=C+Qe;
Then, the highest two value of the first intermediate variable A1 of interval adjustment register A moves to left to C1, and obtain the code registers C second intermediate variable C2: as if the highest two value of A intermediate variable A1 is 3 or 2, then C2=C1; As if the highest two value of the A first intermediate variable A1 is 1, then C2=C1＜＜1; As if the highest two value of the A first intermediate variable A1 is 0, then C2=C1＜＜2;
At last, use formula selection marker sel to confirm the heavy normalized value of interval adjustment register: when the value of formula selection marker sel was 1, heavily normalization result of adjustment register was C2; Otherwise heavily normalization result of adjustment register is C;
6) repeating step: promptly repeating step 4) and step 5) accomplish the interval adjustment register of other threads and the normalization of code registers;
7) value of code stream output step: code registers C after with normalization is input to the code stream output unit, obtains final coded data.
Described use data allocations subelement; Preceding once contextual index value, probability Estimation value and interval adjustment register value are distributed to each current thread; Be whether value according to the corresponding position of command register equals zero to confirm: for i thread, as if command register [C n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position equal zero, then the index value of a last order n thread, probability Estimation value and the interval register value of adjusting are distributed to current thread i; Otherwise, if C in the command register n 2+ i (n-1)-1+k position is 1, then with a last order k thread index value, probability Estimation value and interval adjustment register value distribute to current thread i; C wherein n 2Represent the number of times that all context CX of a current n thread compare in twos, n is a total number of threads, i ∈ [1, n], and i is an integer, k ∈ [1, n], k is an integer.
Described formula is selected signal sel; Be by a expression formula through concluding: D==MPS (CX) ⊙ (M＞2Qe) produce, wherein D is data to be encoded, CX is the context of data to be encoded; ⊙ is an xor operator; M is the value of adjustment register A, and MPS () is a coding environment symbol M PS look-up-table function, and Qe is the probability Estimation value.
The present invention has following advantage:
The present invention is owing to generate subelement and command register through " instruction generates and the index predicting unit " in the arithmetic encoder encryption algorithm introduced instruction; Whether made full use of between each thread context CX equal relation; Thereby reduced the quantity of MUX and memory cell, reduced circuit area; Simultaneously because coding method of the present invention adopts data distributing method and index to confirm method; Different threads is adopted different distribution and determination methods; Thereby adjusted heavily normalization computational process, reduced the decision logic complexity, promoted code efficiency and throughput.Simulation result shows that the present invention significantly reduces the area of circuit, and has significantly improved the operating frequency of arithmetic encoder.
Description of drawings
Fig. 1 is a multithreading arithmetic encoder structured flowchart of the present invention;
Fig. 2 generates and index predicting unit circuit diagram for instruction in the arithmetic encoder of the present invention;
Fig. 3 selects and normalization element circuit figure for index in the arithmetic encoder of the present invention;
Fig. 4 is data allocations subelement circuit diagram in the arithmetic encoder of the present invention;
Fig. 5 is the general flow chart of multithreading arithmetic encoder of the present invention coding method;
Fig. 6 confirms and normalization sub-process figure for the index among the present invention.
Embodiment
With reference to Fig. 1, arithmetic encoder coder structure of the present invention comprises that instruction generates and index predicting unit, index selection and normalization unit, code registers normalization unit and code stream output unit.Wherein:
Instruction generates and the index predicting unit, and its structure is as shown in Figure 2, and it comprises instruction and generates subelement, command register instr and index predictor unit; This instruction generates subelement according to the judged result that whether equates in twos between the context CX of all threads; Write command register instr, corresponding context CX of each thread wherein, it comprises comparator; Whether comparator is used to judge between current each context CX and equates in twos; And whether current each context CX equates in twos with preceding once all context CX_dff that respectively if total number of threads is n, then comparator sum T is T=C n 2+ n 2Individual; This command register instr bit wide value W is determined by Thread Count n, the satisfied W=C that concerns n 2+ n 2, wherein low Whether bit representes between current each context CX in twos equal relation, high n 2Bit representes whether each context CX equates with preceding once all context CX_dff respectively in twos in current each thread; This index predictor unit contains the look-up table of a two-stage; All threads are all shared this look-up table; The address of data is current context CX in the first order look-up table; The content of data be index value, next time big probability environment, next time small probability environment and big next time probability environment and next time the next stage of small probability environment arrive the probability environment of next (n-1) level successively, wherein n is a total number of threads, the bit wide DW=6 of data * (2 N+1-1), wherein n is a total number of threads; The address of data is the lookup result of first order look-up table in the look-up table of the second level, and the content of data is probability Estimation value Qe, and data bit width is 16;
Index is selected and the normalization unit, and its structure is as shown in Figure 3, and it comprises data allocations subelement and thread-data stream subelement; This data allocations subelement; Its result is as shown in Figure 4; Be used for distributing the coding result of its required preceding context CX_dff to each thread; Coding result comprises index value index_dff, probability Estimation value Qe_dff and interval adjustment register A_dff, and it comprises 3 class selectors, is respectively interval adjustment selector a_mux; Probability Estimation selector q_mux and index selector i_mux; Wherein selector is adjusted in corresponding 1 interval of each thread, 1 probability Estimation selector and 1 index selector, and the heavily normalization of the interval adjustment register A that the interval input signal of adjusting selector is preceding once all context CX_dff is A_dff as a result; The output signal is the thread control signal a_pre that distributes to this thread; Probability Estimation selector input signal is the probability Estimation value Qe_dff of preceding once all context CX_dff, and the output signal is the possible probable value qe_pre that distributes to this thread, and index selector input signal is the index value i_dff of preceding once all context CX_dff; The output signal is the possible index value i_pre that distributes to this thread, and the control signal of interval adjustment selector, probability Estimation selector and index selector is the output signal of command register instr;
Code registers normalization unit, it comprises code registers C and returns a beggar unit, and this is returned a beggar unit and is used for the heavily normalization to code registers C;
The code stream output unit is used for the heavily normalization result according to code registers C, and output meets the code stream of JPEG2000 standard.
With reference to Fig. 5, the arithmetic coding method that the present invention is based on JPEG2000 comprises the steps:
Step 1, instruction generates step.
1a) comparator in the use instruction generation subelement carries out in twos all context CX of a current n thread; Corresponding context of each thread wherein; In in the corresponding command register of the 2nd thread the 0th, corresponding the 1st and the 2nd of the 3rd thread, the 3rd, 4 and 5 of the 4th thread correspondence; If comparative result equates, then with command register instr [C n 2-1:0] in the position corresponding bit position 1, otherwise put 0;
1b) current context CX and preceding once all context CX_dff are compared in twos corresponding context of each thread wherein, i the high n of thread correspondence command register 2[C in the bit n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position, n 2Be the number of times that current context and a preceding context are compared in twos, n is a total number of threads, i ∈ [1, n], and i is an integer; If comparative result equates, then with the high n of command register instr 2Corresponding bit position 1 in the position, otherwise put 0.
Step 2, the index prediction.
At first, search first order look-up table according to current context, for i thread, lookup result is index transient state value, arrives down i time big probability coding environment and small probability coding environment, 2i+1 value altogether successively next time;
Then, whether equate with coding environment MPS [j], from the result of first order look-up table, confirm j time probability encoding sign down according to data to be encoded D [j]; If equate, then descend j time probability encoding sign to confirm as big probability coding environment; If do not wait, then descend j time probability encoding sign to confirm as the small probability coding environment; Index prediction steps final result is index transient state value, arrives down i time probability encoding sign next time, common i+1 value, and wherein, j gets all integers from 1 to i, i ∈ [1, n], i is an integer, n is a total number of threads.
Step 3, index is confirmed and the normalization step.
3a) preceding once contextual index value, probability Estimation value and interval adjustment register value are distributed to each current thread, promptly whether the value according to the corresponding position of command register equals zero to confirm: for i thread, if command register [C n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position equal zero, then the index value of a last order n thread, probability Estimation value and the interval register value of adjusting are distributed to current thread i; Otherwise, if C in the command register n 2+ i (n-1)-1+k position is 1, then with a last order k thread index value, probability Estimation value and interval adjustment register value distribute to current thread i, wherein C n 2Represent the number of times that all context CX of a current n thread compare in twos, n is a total number of threads, i ∈ [1, n], and i is an integer, k ∈ [1, n], k is an integer.
3b) according to possibility index value, possibility probable value and thread controlling value, confirm the index value of each thread:
With reference to Fig. 6, the concrete realization of this step is: for i thread, at first whether equal zero the position of decision instruction register [2i (i-1)+i, 2i (i-1)]; If equal zero, then this thread index value is an index transient state value; Otherwise, confirm index value according to the thread controlling value and the magnitude relationship of possibility probable value: if a_pre>=i * qe_pre+2 15, then this thread index value is a possible index value; Otherwise, judge a_pre>=l * qe_pre+2 15Whether set up, if set up, then index value is (i-l) inferior probability encoding sign down, if be false, then carries out circulation: l from subtracting 1, judges a_pre>=l * qe_pre+2 15Whether set up, if set up, then jump out circulation, if be false, then circulation continues; Wherein l is an integer, and its initial value is (i-1), and span is [i-1,0], and a_pre is the thread controlling value; Qe_pre is a possible probable value, i ∈ [1, n], and i is an integer, n is a total number of threads;
The index value that 3c) obtained according to a last step is searched second level look-up table, obtains the probability Estimation value Qe of current context CX;
Step 4 is to the adjustment register normalization of first thread.
At first, computing formula is selected signal sel, and it is by an expression formula through concluding: D==MPS (CX) ⊙ (M＞2Qe) produce; Wherein D is data to be encoded; CX is the context of data to be encoded, and ⊙ is an xor operator, and M is the value of adjustment register A; MPS () is a coding environment symbol M PS look-up-table function, and Qe is the probability Estimation value.
Then, the computation interval adjustment register A first intermediate variable A1=A-Qe;
Then, according to the highest two value of the A first intermediate variable A1, the A first intermediate variable A1 is moved to left, obtain the A second intermediate variable A2: as if the highest two value of A intermediate variable A1 is 3 or 2, then the A second intermediate variable A2=A1; As if the highest two value of the A first intermediate variable A1 is 1, then A second intermediate variable A2=A1＜＜1; As if the highest two value of the A first intermediate variable A1 is 0, then A intermediate variable A2=A1＜＜2;
At last, use formula selection marker sel to confirm the heavy normalized value of interval adjustment register: when the value of formula selection marker sel was 1, heavily normalization result was A2; Otherwise heavily normalization result is Qe.
Step 5 is to the code registers normalization of first thread.
At first, the calculation code register C first intermediate variable C1=C+Qe;
Then, the highest two value of the first intermediate variable A1 with interval adjustment register A moves to left to C1, and obtain the code registers C second intermediate variable C2: the highest two value of intermediate variable A1 as if A is 3 or 2, then C2=C1; If the highest two value of the first intermediate variable A1 of A is 1, then C2=C1＜＜1; If the highest two value of the first intermediate variable A1 of A is 0, then C2=C1＜＜2;
At last, use formula selection marker sel to confirm the heavy normalized value of interval adjustment register: when the value of formula selection marker sel was 1, heavily normalization result of adjustment register was C2; Otherwise heavily normalization result of adjustment register is C;
Step 6, repeating step 4) and step 5) accomplish the interval adjustment register of other threads and the normalization of code registers;
Step 7 is input to the code stream output unit with the value of the code registers C in the step 6 after with normalization, obtains final coded data.
Effect of the present invention can further specify through following emulation:
Emulation 1; The present invention uses the VerilogHDL language that entire circuit is carried out the register transfer rtl code and describes; Making the preceding data of arithmetic encoder encodes with C language program prepares; Accomplish functional simulation on the NC-verilog instrument of use Candence company, the picture of a 400*400 pixel is encoded, the simulation result coding is correct.
Emulation 2; The present invention uses the Design-Compile instrument of Synopsys company, adopts 0.18 μ mCMOS standard cell technology library of SMIC company to carry out comprehensively, and comprehensive back area is 307100.27 square microns; Maximum clock frequency is 287MHz, and throughput is 574Msymbols/sec.And the area of the arithmetic encoder in the document " Concurrency techniques for arithmetic Coding in JPEG2000 " is 384817.91 square microns, and operating frequency is 211.86MHz, and disposal ability is merely 388.34Msymbols/sec.

Claims (8)

1. multithreading arithmetic coding circuit based on the JPEG2000 standard comprises:
Instruction generates and the index predicting unit; It comprises instruction and generates subelement and index predictor unit; This instruction generates subelement according to the judged result that whether equates in twos between the context CX of all threads, write command register instr, the wherein corresponding context CX of each thread; This command register instr is used for controlling searching and the interval normalization of adjusting register A of index and normalization unit concordance list; This index predictor unit is used to predict index transient state value index_pos and the probability encoding sign of each context CX;
Index is selected and the normalization unit, and it comprises data allocations subelement and thread-data stream subelement; This data allocations subelement is used for distributing the coding result of its required preceding context CX_dff to each thread, and coding result comprises index value index_dff, probability Estimation value Qe_dff and interval adjustment register A_dff; This thread-data stream subelement is used for according to the value of data allocations subelement distribution and the value of command register instr; Select index value and the probability Estimation value Qe of the context CX of current each thread; The heavily normalization of computation interval adjustment register A a, wherein corresponding context CX of each thread as a result then;
Code registers normalization unit, it comprises code registers C and returns a beggar unit; This is returned a beggar unit and is used for the heavily normalization to code registers C;
The code stream output unit is used for the heavily normalization result according to code registers C, and output meets the code stream of JPEG2000 standard.
2. coding circuit according to claim 1 is characterized in that: described instruction generates in the subelement and contains comparator and command register instr; Whether comparator is used to judge between current each context CX and equates, and whether current each context CX equates with preceding once all context CX_dff respectively in twos in twos; If total number of threads is n, then comparator sum T is T=C n 2+ n 2Individual; Command register instr bit wide value W is determined by Thread Count n, the satisfied W=C that concerns n 2+ n 2, wherein low
Figure FDA0000128452850000011
Whether bit representes between current each context CX in twos equal relation, high n 2Bit representes whether each context CX equates with preceding once all context CX_dff respectively in twos in current each thread.
3. coding circuit according to claim 1 is characterized in that: said data allocations subelement comprises 3 class selectors, is respectively interval adjustment selector a_mux, probability Estimation selector q_mux and index selector i_mux; Wherein selector, 1 probability Estimation selector and 1 index selector are adjusted in corresponding 1 interval of each thread.
4. coding circuit according to claim 3; It is characterized in that: the heavily normalization of the interval adjustment register A that the interval input signal of adjusting selector is preceding once all context CX_dff is A_dff as a result, and the output signal is the thread control signal a_pre that distributes to this thread; Probability Estimation selector input signal is the probability Estimation value Qe_dff of preceding once all context CX_dff, and the output signal is the possible probable value qe_pre that distributes to this thread; Index selector input signal is the index value i_dff of preceding once all context CX_dff, and the output signal is the possible index value i_pre that distributes to this thread; The control signal of interval adjustment selector, probability Estimation selector and index selector is the output signal of command register instr.
5. coding circuit according to claim 1 is characterized in that: contain the look-up table of a two-stage in the described index predictor unit, all threads are all shared this look-up table;
The address of data is current context CX in the first order look-up table; The content of data be index value, next time big probability environment, next time small probability environment and big next time probability environment and next time the next stage of small probability environment arrive the probability environment of next (n-1) level successively, wherein n is a total number of threads; The bit wide DW=6 of data * (2 N+1-1), wherein n is a total number of threads;
The address of data is the lookup result of first order look-up table in the look-up table of the second level, and the content of data is probability Estimation value Qe, and data bit width is 16.
6. arithmetic coding method based on the JPEG2000 standard comprises:
1) instruction generates step:
1a) comparator in the use instruction generation subelement carries out in twos all context CX of a current n thread; Corresponding context of each thread wherein; In in the corresponding command register of the 2nd thread the 0th, corresponding the 1st and the 2nd of the 3rd thread, the 3rd, 4 and 5 of the 4th thread correspondence; If comparative result equates, then with command register instr [C n 2-1:0] in the position corresponding bit position 1, otherwise put 0;
1b) current context CX and preceding once all context CX_dff are compared in twos corresponding context of each thread wherein, i the high n of thread correspondence command register 2[C in the bit n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position, n 2Be the number of times that current context and a preceding context are compared in twos, n is a total number of threads, i ∈ [1, n], and i is an integer; If comparative result equates, then with the high n of command register instr 2Corresponding bit position 1 in the position, otherwise put 0;
2) index prediction steps:
At first search first order look-up table according to current context, for i thread, lookup result is index transient state value, arrives down i time big probability coding environment and small probability coding environment, 2i+1 value altogether successively next time; Whether equate with coding environment MPS [j] according to data to be encoded D [j] then, from the result of first order look-up table, confirm j time probability encoding sign down; If equate, then descend j time probability encoding sign to confirm as big probability coding environment; If do not wait, then descend j time probability encoding sign to confirm as the small probability coding environment; Index prediction steps final result is index transient state value, arrives down i time probability encoding sign next time, is total to i+1 value; Wherein, j gets all integers from 1 to i, i ∈ [1, n], and i is an integer, n is a total number of threads;
3) index is confirmed and the normalization step:
3a) use data allocations subelement is given each current thread according to the value of command register with preceding once contextual index value, probability Estimation value and interval adjustment its registers, and allocation result is possible index value, possibility probable value and thread controlling value;
3b) according to possibility index value, possibility probable value and thread controlling value, confirm the index value of each thread: for i thread, at first whether equal zero the position of decision instruction register [2i (i-1)+i, 2i (i-1)]; If equal zero, then this thread index value is an index transient state value; Otherwise, confirm index value according to the thread controlling value and the magnitude relationship of possibility probable value: if a_pre>=i * qe_pre+2 15, then this thread index value is a possible index value; Otherwise, judge a_pre>=l * qe_pre+2 15Whether set up, if set up, then index value is (i-l) inferior probability encoding sign down, if be false, then carries out circulation: l from subtracting 1, judges a_pre>=l * qe_pre+2 15Whether set up, as if setting up, then jump out circulation, if be false, then circulation, wherein the l initial value is (i-1) if continuing, span is [i-1,0], and a_pre is the thread controlling value, and qe_pre is a possible probable value, i ∈ [1, n], and i is an integer, n is a total number of threads;
The index value that 3c) obtained according to a last step is searched second level look-up table, obtains the probability Estimation value Qe of current context CX;
4) the adjustment register normalization step of first thread:
At first computation interval is adjusted the register A first intermediate variable A1=A-Qe; According to the highest two value of the A first intermediate variable A1, the A first intermediate variable A1 is moved to left then, obtain the A second intermediate variable A2: as if the highest two value of A intermediate variable A1 is 3 or 2, then the A second intermediate variable A2=A1; As if the highest two value of the A first intermediate variable A1 is 1, then A second intermediate variable A2=A1＜＜1; As if the highest two value of the A first intermediate variable A1 is 0, then A intermediate variable A2=A1＜＜2; Use formula selection marker sel to confirm the heavy normalized value of interval adjustment register at last: when the value of formula selection marker sel was 1, heavily normalization result was A2; Otherwise heavily normalization result is Qe;
5) the code registers normalization step of first thread:
At first, the calculation code register C first intermediate variable Ci=C+Qe;
Then, the highest two value of the first intermediate variable A1 of interval adjustment register A moves to left to C1, and obtain the code registers C second intermediate variable C2: as if the highest two value of A intermediate variable A1 is 3 or 2, then C2=C1; As if the highest two value of the A first intermediate variable A1 is 1, then C2=C1＜＜1; As if the highest two value of the A first intermediate variable A1 is 0, then C2=C1＜＜2;
At last, use formula selection marker sel to confirm the heavy normalized value of interval adjustment register: when the value of formula selection marker sel was 1, heavily normalization result of adjustment register was C2; Otherwise heavily normalization result of adjustment register is C;
6) repeating step 4) and step 5) accomplish the interval adjustment register of other threads and the normalization of code registers;
7) value of code stream output step: code registers C after with normalization is input to the code stream output unit, obtains final coded data.
7. arithmetic coding method according to claim 6; Step 3a wherein) described use data allocations subelement; Preceding once contextual index value, probability Estimation value and interval adjustment register value are distributed to each current thread; Be whether value according to the corresponding position of command register equals zero to confirm: for i thread, as if command register [C n 2+ i (n-1)+n-2, C n 2+ i (n-1)-1] the position equal zero, then the index value of a last order n thread, probability Estimation value and the interval register value of adjusting are distributed to current thread i; Otherwise, if C in the command register n 2+ i (n-1)-1+k position is 1, then with a last order k thread index value, probability Estimation value and interval adjustment register value distribute to current thread i; C wherein n 2Represent the number of times that all context CX of a current n thread compare in twos, n is a total number of threads, i ∈ [1, n], and i is an integer, k ∈ [1, n], k is an integer.
8. arithmetic coding method according to claim 6, wherein the described formula of step 4) is selected signal sel, is by an expression formula through concluding: D==MPS (CX) ⊙ (M＞2Qe) produce; Wherein D is data to be encoded; CX is the context of data to be encoded, and ⊙ is an xor operator, and M is the value of adjustment register A; MPS () is a coding environment symbol M PS look-up-table function, and Qe is the probability Estimation value.
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