CN102522110A - Method and device for realizing data preloading in transmission circuit of digital audio interface - Google Patents
Method and device for realizing data preloading in transmission circuit of digital audio interface Download PDFInfo
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- CN102522110A CN102522110A CN2011103895823A CN201110389582A CN102522110A CN 102522110 A CN102522110 A CN 102522110A CN 2011103895823 A CN2011103895823 A CN 2011103895823A CN 201110389582 A CN201110389582 A CN 201110389582A CN 102522110 A CN102522110 A CN 102522110A
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Abstract
The invention discloses a method and device for realizing data preloading in a transmission circuit of a digital audio interface. According to the method and the device for realizing data preloading in the transmission circuit of the digital audio interface, a data preloading control module is in charge of the advance preparation of data by arranging a detecting counter, an auxiliary counter and the data preloading control module in a transmission circuit of a digital audio interface through referring to the counting value of the detecting counter or the auxiliary counter, the counting value of a moment transmitting first data is also judged according to a digital audio interface protocol, and a period before the data are transmitted is determined according to the counting value and is just a moment for preparing the data; and when a synchronous clock (LRCK) arrives, the first data are shifted out on the edge of a bit clock (BCLK), and then other data are also shifted out on the edge of the bit clock bit by bit. According to such a data preloading method, the time delay brought because of logical judgment is decreased, the data transmission rate is enhanced, and the time-sequence characteristic of a circuit is structurally improved.
Description
Technical field
The present invention relates to digital audio interface transtation mission circuit field, especially relate to through in the digital audio interface transtation mission circuit, improving the method and apparatus of data rate through data prestrain.
Background technology
Digital audio interface is through analog to digital conversion by sound pick-up outfit; Become analog audio data the data stream of numeral; Send to system through certain protocol; Perhaps send to tone playing equipment to the data stream of numeral through certain protocol, come out voice playing originally through digital-to-analog conversion by tone playing equipment again by system.
Digital audio interface has different transfer rates according to the sampling rate and the quantified precision of voice data.Modal sampling rate has 8KHz, 44.1KHz, and 48KHz, 96KHz etc., the precision of data also has 16,18,20,24,32 etc.Quality of audio data is high more, and the sampling rate of requirement is high more, and the quantified precision of requirement is also high more, and high more tonequality requires just to require the high more transfer rate of audio interface circuit.When system environments was very poor, the line between the digital audio interface may produce a lot of uncertain time-delays, also can operate as normal under such environment with regard to needing the good interface circuit of the characteristic system that makes.
Common digital audio interface is that serial is received and dispatched synchronously, i.e. the data transmission of clock or reception one by one on the clock edge, and the sampled data of different sound channels is alignd according to the synchronous clock tissue.Common interface protocol has IIS (Integrate Interface of Sound, integrated audio interface), left-justify, Right Aligns, DSP pattern etc.Data change along being sign with synchronous clock (LRCK), when synchronous clock changes, begin to send data or when arriving, begin to send first data at next bit clock (BCLK).Under the situation of data demand horse back output data when synchronous clock (LRCK) changes; Common design meeting divides two parts data; A part is to send first data through one group of decision logic switch data output port after detecting synchronizing signal (LRCK), when arriving in next bit clock (BCLK) edge, switches to by bit clock more then and exports data by turn at once.
In the digital audio interface transtation mission circuit; Some interface protocol is that the data transmission does not have the enough reaction time; When data sync clock (LRCK) occurs, must send first bit data simultaneously, send the next bit data at next bit clock (BCLK) rising edge, by that analogy.Switching different circuits through one group of decision logic control selector switch sends first respectively and can realize with other bit data; But the complex judging logic brings very big delay can for the data of first transmission; Influence the temporal characteristics of integrated circuit greatly, can't reach certain message transmission rate.For improving the temporal characteristics of circuit, need to adopt the way of prediction loading data, prepare data in advance through prediction, shift out total data by turn by bit clock (BCLK) then.
As above chat; The sequence problem of first bit data is the main bottleneck of design in the design of digital audio interface transtation mission circuit; And other bit data can both be alignd with bit clock (BCLK) edge; But because the complexity of decision logic and agreement and design all have relation, possibly bring a lot of uncertain time-delays, so that whole design circuit characteristic is very poor.In the bad application of system environments, may cause the interface circuit data transmission fault especially.
Summary of the invention
The purpose of this invention is to provide a kind of method and apparatus of in the digital audio interface circuit, realizing data prestrain; It introduces data prestrain circuit in the digital audio interface circuit; Shift to an earlier date preliminary date; Let total data all on bit clock (BCLK) edge, send by turn, solve the unbalanced problem of sequential, thereby improve the transmission speed of data.
For realizing above-mentioned purpose, the present invention proposes one of technical scheme and is: a kind of method that in the digital audio interface transtation mission circuit, realizes data prestrain comprises:
A. detect synchronous clock and bit clock in the COBBAIF transtation mission circuit by detection counter, and determine the bit clock rate and the count value that detects clock of digital audio interface;
B. data prestrain control module is according to said detection counter bit clock rate that obtains and the count value that detects clock; Requirement according to the digital audio interface agreement; Judge the count value when sending data, and confirm to send the data preparatory period that the preceding one-period of data is the preparation data;
C. data prestrain control module is sent data prestrain control signal in the data preparatory period and is given digital sending module, by data transmission blocks with data load to be sent in shift register.
D. on the bit clock edge, send out first bit data when synchronous clock arrives by shift register.
Wherein, there are parallel L channel data and parallel right data in the said data transmission blocks.
Another technical scheme that the present invention proposes is: a kind of method that in the digital audio interface transtation mission circuit, realizes data prestrain comprises:
A. detect synchronous clock and bit clock in the COBBAIF transtation mission circuit by detection counter, and determine the bit clock rate and the count value that detects clock of digital audio interface;
B. produce synchronizing signal by detection counter to auxiliary counter, by auxiliary counter according to this synchronizing signal counting that carries out being associated with said detection counter;
C. data prestrain control module, is judged and is sent the moment of data according to the requirement of digital audio interface agreement according to the count value of said auxiliary counter, and confirms to send the data preparatory period that the preceding one-period of data is the preparation data;
D. data prestrain control module is sent the Loading Control signal in the data preparatory period, and data load to be sent is ready for sending in shift register.
E. on the bit clock edge, send out first bit data when synchronous clock arrives by shift register.
Wherein, said auxiliary counter is hinted obliquely at by said detection counter and is got.
There are parallel L channel data and parallel right data in the said data transmission blocks.
The third technical scheme that the present invention proposes is: a kind of device of in the digital audio interface transtation mission circuit, realizing data prestrain, comprise clock module, data transmission blocks and register, and detection counter, data prestrain control module; Wherein:
Said detection counter is used for detecting the synchronous clock and the bit clock of said clock module, with the bit clock rate of specified data;
Said data prestrain control module is controlled the one-period of said data transmission blocks before said register sends data and is ready to data to be sent with reference to the count value of said detection counter.
The device of said data prestrain also comprises auxiliary counter, and the counting of said auxiliary counter is hinted obliquely at by said detection counter and got.
Said data prestrain control module is controlled the one-period of said data transmission blocks before said register sends data and is ready to data to be sent with reference to the count value of said auxiliary counter.
Said auxiliary counter is for being selected from up counter, a kind of in down counter and other type counter.
The present invention adopts the technical scheme of auxiliary counter to reduce the area of data prediction loading decision logic; Auxiliary counter is through specific synchronization mechanism; Produce the required counting of transtation mission circuit, make transtation mission circuit need not to call a plurality of totalizers and carry out complex calculation and can simply judge digital audio-frequency data Loading Control signal.
The data of sending when digital audio interface are sent the responseless time of data with the synchronous clock alignment time, and promptly synchronous clock moment of arriving will be sent first data by the bit clock driving.This just needs prediction to prepare data in advance.For realizing that prediction loads, at first need detecting position clock ratio (BCLKRATIO), this is accomplished by detection counter, and each synchronous clock (LRCK) is when sending synchronizing signal, and the output valve of detection counter is bit clock rate (BCLKRATIO).
According to the agreement of interface, refer again to the count value of counter, bit clock rate (BCLKRATIO) can be confirmed preliminary date through calculating the moment.The counter of reference can be a detection counter, also can be auxiliary counter.For example this Counter Design is for adding 1 counter, and counting is N when synchronizing signal is sent, when the moment of data preparation is counter arrival N-1 so.When N is 0 or 1, when prediction need be got back to counting for BCLKRATIO-1 or BCLKRATIO constantly.For reducing decision logic, design a suitable auxiliary counter, can avoid a lot of plus and minus calculations.
With Right Aligns, data length is the data instance of WLEN, if detection counter CNTD is for adding 1 counter; This counter be one from 1 be added to BCLKRATIO counter; Each synchronizing signal all can count down to BCLKRATIO when arriving, and becomes 1 clearly then, so circulation.Adopt data prediction to load, need subtracter " BCLKRATIO-1 " and corresponding comparer, be used for the data load under the BCLKRATIO=WLEN situation; Subtracter " BCLKRATIO-WLEN " and " BCLKRATIO-WLEN-1 " and corresponding comparer are used to judge the difference of BCLKRATIO and WLEN, confirm the position BCLKRATIO-WLEN-1 of loading data control signal.If adopt the method for auxiliary counter, design one and subtract 1 counter, counter becomes BCLKRATIO clearly in BCLKRATIO-2, so only need in the value CNTA=WLEN of auxiliary counter, get final product by loading data.Used an auxiliary counter (and comparer of a subtracter) like this,, reduced area generally though many 1 counters have been saved 2 subtracters and 1 comparer.
The present invention is because all data all are the output on the clock edge of same register, and the data time-delay nearly all is the same, i.e. the constant time lag of this fixed route from the clock to the pin.First bit data of sending has not had because the time-delay that the complex combination logic is brought, and the integrated circuit characteristic is greatly improved, and promptly transfer rate is improved, and chip conforms stronger.Simultaneously; Utilize auxiliary counter prediction loading data, make the digital audio interface transtation mission circuit can prepare data in advance, shift out by turn by bit clock (BCLK) again; Reduced the time-delay that brings because of logic determines; Well improved message transmission rate, improved the temporal characteristics of circuit from framework, good temporal characteristics makes that also more digital audio interface agreement is better supported.
Design the synchronization mechanism and the counting of auxiliary counter dexterously, can reduce the use of totalizer, reduced the area of circuit on the whole.
Description of drawings
Fig. 1 is for realizing the module map of data prestrain principle in the digital audio interface transtation mission circuit of the present invention.
Fig. 2 realizes the module map of data prestrain for the present invention.
Fig. 3 realizes the sequential chart of data prestrain for Right Aligns DAB transmission interface in the embodiment of the invention utilizes auxiliary counter.
Embodiment
To combine accompanying drawing of the present invention below, the technical scheme in the preferred embodiment of the present invention will be carried out clear, complete description.
As shown in Figure 1, in the digital audio interface transtation mission circuit, comprise clock module; Data transmission blocks; Shift register and data prestrain unit, clock module produce or handle synchronous clock and bit clock, and data transmission blocks comprises parallel data L channel and parallel data R channel.With the synchronous clock is reference; Data prestrain control module produces the prestrain control signal and when data are about to send, is loaded into shift register to parallel L channel data in the data transmission blocks or parallel right data; Shift register is shifted all the time; When synchronous clock (LRCK) arrives, just in time on bit clock (BCLK) edge, shift out first bit data, then also on the bit clock edge, shift out other bit data by turn.
As shown in Figure 2; Said data prestrain unit comprises detection counter, auxiliary counter and data prestrain control module; When adopting auxiliary counter; The reference system of data prestrain control module is an auxiliary counter, and the reference system of auxiliary counter is by the synchronous detection counter of synchronous clock.Auxiliary counter designs according to digital audio interface agreement etc., produces a unified reference frame, data prestrain control module can directly be judged produce data prestrain control signal, and the parallel left and right acoustic channels of control is written into shift register.
Detection counter is a up counter, and purpose is to detect the synchronous clock (LRCK) and the bit clock (BCLK) of digital audio interface, confirms the bit clock rate (BCLKRATIO) of digital audio interface data.Sending synchronous signal at synchronous clock (LRCK) (can be rising edge; Also can be negative edge) time to this counter O reset or become particular value clearly; When this synchronous signal arrived once more, the current count value of detection counter was exactly the bit clock rate (BCLKRATIO) that we need.According to the count value of detected bit clock rate (BCLKRATIO) and detection clock, just can judge the moment that draws preloading data.
Auxiliary counter can be a up counter, also can be down counter or other types counter, and this need decide according to the digital audio interface agreement.This designs because of the hardware consumption that complicated plus and minus calculation brings in order to reduce decision logic.It can be hinted obliquely at according to certain logic and got by detection counter; Can be reference also by detection counter; Producing a specific synchronizing signal, is a series of countings of initial generation with this particular sync signal, also can combine above method according to design demand; Both some counting was to be hinted obliquely at and got by detection counter, and also some counting is by the own nature counting and get.
The data load prediction module is that predicted data loads constantly, prepares data in advance, and when upset took place digital audio interface synchronous clock (LRCK), the interface transtation mission circuit sent data under the driving on bit clock (BCLK) edge simultaneously.The data load prediction module can only judge that detection counter obtains the Loading Control signal through certain logic, but this decision logic can take many circuit areas.The introducing of auxiliary counter can be simplified decision logic, and this has also reduced the area of circuit on the whole.
Be illustrated in figure 3 as one of preferred embodiment of the present invention, this embodiment is to be the sequential chart of example with the Right Aligns digital audio interface.M is the position bit rate of data, detection counter be one from 1 to M 1 counter that adds, all count M when each synchronous clock (LRCK) arrives.
Auxiliary counter is the down counter of a M to 1, in M-2, makes auxiliary counter when bit clock arrives, be synchronized to M at detection counter.The generation of prestrain control signal need be with reference to auxiliary counter, the value of auxiliary counter be position bit rate subtrahend according to length in, promptly produce a data prestrain control signal.
The present invention includes all digital audio interface agreements, under different agreement, adopt different auxiliary counters, auxiliary counter can be selected from and add 1 counter, subtracts the counter or the counter combination of 1 counter and other types.
Technology contents of the present invention and technical characterictic have disclosed as above; Yet those of ordinary skill in the art still maybe be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; Therefore; Protection domain of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (10)
1. method that in the digital audio interface transtation mission circuit, realizes data prestrain, it is characterized in that: this method comprises:
A. detect synchronous clock and bit clock in the COBBAIF transtation mission circuit by detection counter, and determine the bit clock rate and the count value that detects clock of digital audio interface;
B. data prestrain control module is according to said detection counter bit clock rate that obtains and the count value that detects clock; Requirement according to the digital audio interface agreement; Judge the count value when sending data, and confirm to send the data preparatory period that the preceding one-period of data is the preparation data;
C. data prestrain control module is sent data prestrain control signal in the data preparatory period and is given digital sending module, by data transmission blocks with data load to be sent in shift register.
D. on the bit clock edge, send out first bit data when synchronous clock arrives by shift register.
2. method according to claim 1 is characterized in that: have parallel L channel data and parallel right data in the said data transmission blocks.
3. method that in the digital audio interface transtation mission circuit, realizes data prestrain, it is characterized in that: this method comprises:
A. detect synchronous clock and bit clock in the COBBAIF transtation mission circuit by detection counter, and determine the bit clock rate and the count value that detects clock of digital audio interface;
B. produce synchronizing signal by detection counter to auxiliary counter, carry out the counting that is associated with said detection counter by auxiliary counter according to this synchronizing signal;
C. data prestrain control module, is judged and is sent the moment of data according to the requirement of digital audio interface agreement according to the count value of said auxiliary counter, and confirms to send the data preparatory period that the preceding one-period of data is the preparation data;
D. data prestrain control module is sent the Loading Control signal in the data preparatory period, and data load to be sent is ready for sending in shift register.
E. on the bit clock edge, send out first bit data when synchronous clock arrives by shift register.
4. method according to claim 3 is characterized in that: said auxiliary counter is hinted obliquely at by certain logic by said detection counter and is got.
5. method according to claim 3 is characterized in that: have parallel L channel data and parallel right data in the said data transmission blocks.
6. device of in the digital audio interface transtation mission circuit, realizing data prestrain is characterized in that: comprise clock module, data transmission blocks and register, and detection counter, data prestrain control module; Wherein:
Said detection counter is used for detecting the synchronous clock and the bit clock of said clock module, with the bit clock rate of specified data;
Said data prestrain control module is controlled the one-period of said data transmission blocks before said register sends data and is ready to data to be sent with reference to the count value of said detection counter.
7. device according to claim 6 is characterized in that: said device also comprises auxiliary counter, and the counting of said auxiliary counter is hinted obliquely at by certain logic by said detection counter and got.
8. device according to claim 7 is characterized in that: said auxiliary counter is to be reference with the detection counter, produce a synchronizing signal, and is initial counting with this synchronizing signal.
9. according to claim 7 or 8 described devices; It is characterized in that: said data prestrain control module is controlled the one-period of said data transmission blocks before said register sends data and is ready to data to be sent with reference to the count value of said auxiliary counter.
10. according to claim 7 or 8 described devices, it is characterized in that: said auxiliary counter is for being selected from up counter, a kind of in down counter and other type counter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103731411A (en) * | 2012-10-16 | 2014-04-16 | 马维尔国际贸易有限公司 | High bandwidth configurable serial link |
| CN106936847A (en) * | 2017-04-11 | 2017-07-07 | 深圳市米尔声学科技发展有限公司 | The processing method and processor of voice data |
| CN115174305A (en) * | 2022-06-28 | 2022-10-11 | 珠海一微半导体股份有限公司 | IIS interface-based data conversion control system and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103731411A (en) * | 2012-10-16 | 2014-04-16 | 马维尔国际贸易有限公司 | High bandwidth configurable serial link |
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| CN115174305A (en) * | 2022-06-28 | 2022-10-11 | 珠海一微半导体股份有限公司 | IIS interface-based data conversion control system and chip |
| CN115174305B (en) * | 2022-06-28 | 2023-11-03 | 珠海一微半导体股份有限公司 | IIS interface-based data conversion control system and chip |
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