CN102508798A

CN102508798A - CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) interface method based on BURST and flow line

Info

Publication number: CN102508798A
Application number: CN2011103154686A
Authority: CN
Inventors: 陈庆旭; 叶品勇; 魏建功; 余华武
Original assignee: Guodian Nanjing Automation Co Ltd
Current assignee: Guodian Nanjing Automation Co Ltd
Priority date: 2011-10-18
Filing date: 2011-10-18
Publication date: 2012-06-20
Anticipated expiration: 2031-10-18
Also published as: CN102508798B

Abstract

The invention discloses a CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) interface method based on BURST and a flow line. The method is applied to various occasions in the need of interacting mass data between the CPU and the FPGA. The method is mainly characterized by comprising the following steps: the CPU is used for reading and writing the FPGA in a BUSRT manner; the FPGA is in a form of an internal address register; and an actual read-write address is in a form of the internal address register of the FPGA. According to the method disclosed by the invention, the problems of lower exchange efficiency between the CPU and the FPGA and incapability of satisfying the actual use requirement when mass data between the CPU and the FPGA needs to be interacted in the prior art are solved; a method for reading and writing the FPGA by the CPU by adopting the BURST manner with the help of a flow line technology is provided; and, by means of the manner, the time required for reading and writing the FPGA by the CPU can be greatly reduced, and the efficiency for reading and writing the FPGA by the CPU can be increased.

Description

CPU and FPGA interface method based on BURST and streamline

Technical field

The present invention relates to a kind of CPU and FPGA interface method, can be used in CPU and FPGA and need mass data and carry out mutual various occasions based on BURST and streamline.

Background technology

Along with the application of FPGA (Field Programmable Gate Array) is day by day extensive, a lot of systems have adopted the framework mode of CPU+FPGA.Have lot of data need carry out alternately between CPU and the FPGA, the efficient that how to improve CPU read-write FPGA has become a bottleneck problem in the plurality of applications.

At present, FPGA generally carries out alternately through dual port RAM and CPU, and the buffering through dual port RAM is with problems such as the speed that solves FPGA and CPU and concurrencys.The dual port RAM that dual port RAM can adopt special-purpose dual port RAM chip or utilize the logic simulation of FPGA to come out, the former is because cost is high, and capacity is little, so general more be the mode that adopts the latter.

For the ease of explanation, sequential discussion below is an example with certain MPC8247 application system, the read-write frequency 100MHz of CPU, but concrete principle goes for the CPU of other various frequencies.Compiling information according to FPGA can know, the output time-delay that the logical resource of FPGA simulates out dual port RAM generally at 12ns between the 17ns.Consider the Time Created of address, the factors such as retention time of data, CPU reads the FPGA dual port RAM at every turn should need at least 4 clock period, and just 40ns can carry out normal read-write to the dual port RAM of FPGA.Fig. 1 is the synoptic diagram of FPGA being read and write with traditional approach CPU, and each read-write of CPU all need be waited for the time of about 40ns.The output procedure of whole FPGA does not have overlapping, reads 8 needed times continuously to be at least 320ns.

Even CPU has read FPGA The data dma mode; Because when CPU reads and writes FPGA; Address data bus is taken by DMA; CPU can't operate peripheral hardwares such as SDRAM and FLASH, so this moment, CPU was equivalent to be in waiting status, so the efficient of CPU is still lower at this moment.

Summary of the invention

Have lot of data need carry out alternately in order solving in the prior art between the CPU and FPGA, but exchange efficiency between the two to be lower, can not to satisfy the problem of actual use needs.The present invention proposes the method that a kind of CPU adopts BURST mode incorporating pipeline technology that FPGA is read and write; There is mass data to carry out mutual occasion at CPU and FPGA; Adopt this mode can reduce the CPU read-write needed time of FPGA greatly, improve the efficient of CPU read-write FPGA.

In order to address the above problem, the technical scheme that the present invention taked is:

A kind of CPU and FPGA interface method based on BURST and streamline is characterized in that: may further comprise the steps:

(1), CPU adopts the mode of BURST to read and write to FPGA, adopt this mode after, CPU can carry out the continuous several times read-write to FPGA;

(2), adopted the mode of home address register in FPGA inside, when CPU began to read and write, FPGA was latched into current read/write address in the inner address register of FPGA;

(3), for read operation, FPGA adds 1 to the value of address register before accomplishing in current read cycle automatically, exports next data; For write operation, then after current write cycle time is accomplished, add 1 to the value of address register;

(4), the back process in, each clock period, FPGA adds 1 to address register automatically.

Aforesaid a kind of CPU and FPGA interface method based on BURST and streamline is characterized in that: for read operation, CPU has adopted the BURST mode to carry out repeatedly read operation to FPGA continuously; In the time of the CPU read data first time; The whole cycle needs 40ns, and FPGA begins output data in 20ns, because the data of FPGA output time-delay is 20ns; So in the time of 40ns, CPU can read first data; In the inside of FPGA, design logic adds 1 to the current address automatically in 30ns, begins to export the content of next address; Because the data of FPGA output time-delay is 20ns; In 50ns, CPU can read second data, in the time afterwards; The rest may be inferred, and FPGA can export data in each clock period.

Aforesaid a kind of CPU and FPGA interface method based on BURST and streamline is characterized in that: need not consider the data output delay time of FPGA for write operation, the value of the address register that FPGA is inner only need add 1 again after this write cycle time is accomplished.

Aforesaid a kind of CPU and FPGA interface method based on BURST and streamline is characterized in that: for continuous 8 read operations, it is 110ns that CPU reads the needed time of FPGA data.

The invention has the beneficial effects as follows: the BURST mode is a kind of continuous read-write mode that CPU adopts in order to improve read-write efficiency, and generally according to the difference of CPU, the length of BURST can be configured to 4 or 8.Present this technology generally only be applied to CPU and SDRAM between read-write, CPU adopts the BURST mode to read and write a plurality of addresses of SDRAM, has improved the read-write efficiency of CPU to SDRAM.The present invention has been incorporated into the read-write process of CPU to FPGA to the BURST mode, in FPGA, has adopted pipelining, has improved the speed of CPU read-write FPGA greatly.

Description of drawings

Fig. 1 is the synoptic diagram that adopts traditional approach CPU that FPGA is read and write.

Fig. 2 is the synoptic diagram that FPGA adopts the pipeline system read procedure.

Fig. 3 is that FPGA adopts pipeline system to write the synoptic diagram of process.

Embodiment

Below in conjunction with accompanying drawing the present invention is done further description.

Enforcement of the present invention comprises the design of two aspects, and first is that CPU reads and writes FPGA according to the BUSRT mode; Second portion is the realization of the employing pipeline system reading and writing operation of FPGA.

CPU reads and writes according to the mode of similar BURST FPGA.After adopting this mode, CPU can carry out the continuous several times read-write to FPGA.

Adopted the mode of home address register in FPGA inside, when CPU began to read and write, FPGA was latched into current read/write address in the inner address register of FPGA.

For read operation, FPGA adds 1 to the value of address register before accomplishing in the current read cycle, exports next data; For write operation, then after current write cycle time is accomplished, add 1 to the value of address register.

In the process of back, each clock period, FPGA adds 1 to address register automatically.

According to such process, need experience the long stand-by period when first data are got in the CPU reading and writing, but in the process of back, CPU can improve efficient greatly in data of each clock period reading and writing.

Fig. 2 adopts BURST and pipelining to realize that CPU reads sequential to FPGA.Read procedure with FPGA is an example below, and the course of work of FPGA is described.

Because CPU has adopted the BURST mode, so CPU can carry out repeatedly read operation to FPGA continuously.In the time of the CPU read data first time; The whole cycle approximately needs 40ns, and FPGA begins output data about time about 20ns greatly, because the data of FPGA output time-delay is generally between 10ns and 16ns; So in the time of 40ns, CPU can read first data.In the inside of FPGA, design logic adds 1 to the current address automatically in 30ns, begins to export the content of next address; Because the data of FPGA output time-delay is 20ns; In 50ns, CPU can read second data, in the time afterwards like this; The rest may be inferred, and FPGA can export data in each clock period.In whole process, the time-delay of FPGA output data is overlapped, and the mode of similar streamline is carried out continuous data output, can improve the read-write efficiency of FPGA greatly.

After adopting this mode, for continuous 8 read operations, the needed time is about 110ns.Improved greatly the CPU read-write efficient and and FPGA between the data interaction bandwidth.

Fig. 3 adopts BURST and pipelining to realize that CPU writes sequential to FPGA.Compare with read procedure, main difference is because ablation process need not considered the data output time-delay of FPGA, so the inner address of FPGA only need add 1 again after this read-write is accomplished.In conjunction with the BURST mode, improved the writing speed of data greatly.

More than show and described ultimate principle of the present invention, principal character and advantage.The technician of the industry should understand; The present invention is not restricted to the described embodiments; That describes in the foregoing description and the instructions just explains principle of the present invention; Under the prerequisite that does not break away from spirit and scope of the invention, the present invention also has various changes and modifications, and these variations and improvement all fall in the scope of the invention that requires protection.The present invention requires protection domain by appending claims and equivalent circle thereof.

Claims

1. CPU and FPGA interface method based on a BURST and a streamline is characterized in that: may further comprise the steps:

2. a kind of CPU and FPGA interface method based on BURST and streamline according to claim 1 is characterized in that: for read operation, CPU has adopted the BURST mode to carry out repeatedly read operation to FPGA continuously; In the time of the CPU read data first time; Suppose that the whole cycle needs 40ns, FPGA begins output data in 20ns, because the data of FPGA output time-delay is 20ns; So in the time of 40ns, CPU can read first data; In the inside of FPGA, design logic adds 1 to the current address automatically in 30ns, begins to export the content of next address; Because the data of FPGA output time-delay is 20ns; In 50ns, CPU can read second data, in the time afterwards; The rest may be inferred, and FPGA can export data in each clock period.

3. a kind of CPU and FPGA interface method according to claim 2 based on BURST and streamline; It is characterized in that: need not consider the data output delay time of FPGA for write operation, the value of the address register that FPGA is inner only need add 1 again after this write cycle time is accomplished.

4. according to claim 2 or 3 described a kind of CPU and FPGA interface methods based on BURST and streamline, it is characterized in that: for continuous 8 read operations, it is 110ns that CPU reads the needed time of FPGA data.