CN102495792A - Interface device for multi-event control and real-time monitoring during online debugging - Google Patents
Interface device for multi-event control and real-time monitoring during online debugging Download PDFInfo
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Abstract
The invention relates to an interface device for multi-event control and real-time monitoring during online debugging. The interface device comprises a hardware event unit, a JTAG (Joint Test Action Group) interface unit, a command register unit, a control register unit and a state register unit. The JTAG interface unit is used for receiving a control command transmitted from an upper computer to a processing unit and inputting state information of the processing unit to the upper computer during the online debugging; the command register unit is used for receiving commands, transmitted by the upper computer, for selecting the control register unit and executing writing operation on the control register unit; the control register unit is used for judging that a first hardware breakpoint event, a second hardware breakpoint event, a tracking event and a combined event consisting of the first hardware breakpoint event, the second hardware breakpoint event and the tracking event are valid or not; and the state register unit is used for saving state information of a built-in processing unit after events generate. The interface device for multi-event control and real-time monitoring during the online debugging, disclosed by the invention, controls the hardware breakpoint events and the tracking event to generate according to a specific combined sequence and monitors in real time so as to effectively reduce the difficulty of the online debugging.
Description
Technical field
The present invention relates to flush bonding processor on-line debugging field, it specifically is the interface arrangement of eventful control of a kind of on-line debugging and real time monitoring.
Background technology
On-line debugging is that a kind of flush bonding processor carries out software debugging and uses mode widely, and on-line debugging is realized the real-time, interactive of software debugging personnel and flush bonding processor through an in-circuit emulator.
Hardware Breakpoint incident and track of events are dual modes commonly used in the on-line debugging, can the accurate in locating debugged program through Hardware Breakpoint incident and track of events software debugging personnel, and then carry out real-time, interactive with flush bonding processor.Along with the continuous lifting of flush bonding processor performance, the program of carrying on flush bonding processor is also increasing, becomes increasingly complex, and this has proposed challenge to software debugging, need carry out complicated on-line debugging.The software debugging personnel carry out frequent use Hardware Breakpoint incident and the track of events of meeting in the complicated on-line debugging process, even can require Hardware Breakpoint incident and track of events to take place according to the different combinations order.
Traditional flush bonding processor hardware assistant adjustment module, the generation of Hardware Breakpoint incident and track of events is separate in design.In the software debugging operation of complicacy; The software debugging personnel use Hardware Breakpoint incident and track of events to carry out on-line debugging simultaneously; Might occur just might causing when a plurality of Hardware Breakpoint incidents and track of events take place simultaneously flush bonding processor the chaotic state of response to occur like this; Thereby cause the uncertainty of software debugging to be kept watch on being difficult for, this has increased difficulty to on-line debugging.
Summary of the invention
Cause flush bonding processor the chaotic defective of response to occur simultaneously in order to overcome Hardware Breakpoint incident and track of events; The invention provides the interface arrangement of eventful control of a kind of on-line debugging and real time monitoring; Control hardware breakpoint event and track of events take place smoothly according to specific combined and carry out real time monitoring, effectively reduce the difficulty of on-line debugging.
The technical solution adopted for the present invention to solve the technical problems is:
The interface arrangement of eventful control of a kind of on-line debugging and real time monitoring, described interface arrangement comprises:
The hardware event unit comprises Hardware Breakpoint event generator and track of events generator, and the Hardware Breakpoint incident is produced by the Hardware Breakpoint event generator; Track of events is produced by the track of events generator;
The jtag interface unit based on the standard communication interface of IEEE Std 1149.1 agreements, is used to receive host computer and sends to the control command of flush bonding processor and the status information of flush bonding processor is exported to host computer in the on-line debugging;
The command register unit is used for carrying out through the selection control register unit of jtag interface unit reception host computer transmission and to the control register unit order of write operation; Carry out the order of read operation through the selection mode register cell of jtag interface unit reception host computer transmission and to the status register unit;
The control register unit; Be used for choosing the control register unit and the control register unit being carried out the order of write operation through what the jtag interface unit sent when the command register unit receives host computer, the control register unit begin to receive the order that host computer sends through the jtag interface unit so that control combination event that the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident and track of events constitute effectively with invalid;
The status register unit is used to preserve the status information that the back flush bonding processor takes place for the said first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events and combination event.
Further, said track of events generator has one, and said Hardware Breakpoint event generator has more than two at least.
Further again, said track of events generator has one, and said Hardware Breakpoint event generator has two, is respectively the first Hardware Breakpoint event generator and the second Hardware Breakpoint event generator.
A read-write control bit W/R then can write data to the register cell of choosing, if W/R=1 then can be from the register cell sense data of choosing in the said command register unit when W/R=0; Select control bit RS [4:0] for five in the command register unit; RS [4:0] can select to control 32 register cells; Control register unit and status register unit are two in these 32 register cells, W/R position after flush bonding processor resets, and RS [4:0] is all by zero clearing.
Two bit pattern incident control bit SQC [1:0] in the control register unit; The generation of the corresponding respectively control different combinations of SQC=2 ' b00, SQC=2 ' b01, SQC=2 ' b10, SQC=2 ' b11 incident, flush bonding processor resets back SQC [1:0] by zero clearing.
Hardware Breakpoint incident generation flag MBO in the status register unit; When the Hardware Breakpoint incident takes place and the formula processor of being embedded into responds then that MBO is put the track of events generation flag TO in the 1 status register unit, when track of events takes place and the formula processor of being embedded into responds then the TO position and put 1; Two one combination event generation flag SQA and SQB in the status register unit, the combination event that constitutes when Hardware Breakpoint incident and track of events takes place and the formula processor of being embedded into responds then that SQA and SQB can be put 1 accordingly; MBO in the status register, TO, SQA, SQB after flush bonding processor resets all by zero clearing.
Preferably, formerly debug eventful control procedure and be: as SQC [1:0]=2 ' b00, and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled.When the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all can take place alone when satisfying occurrence condition separately, unaffected each other.
As SQC [1:0]=2 ' b01, and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled.In such cases, one time second Hardware Breakpoint incident must at first take place in the generation of track of events, and wherein the second Hardware Breakpoint incident is not processed the device response, and the track of events that takes place subsequently is processed the device response.
As SQC [1:0]=2 ' b10, and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled.In such cases, the second Hardware Breakpoint incident takes place one time first Hardware Breakpoint incident must at first take place, and wherein the first Hardware Breakpoint incident is not processed the device response, and the second Hardware Breakpoint incident that takes place subsequently is processed the device response.
As SQC [1:0]=2 ' b11, and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled.This kind information summary above two kinds of combination events; One time first Hardware Breakpoint incident must formerly take place and take place just possibly take place under the exciting of one time second Hardware Breakpoint incident again in track of events; Wherein the response of formula processor takes place all not to be embedded in the first Hardware Breakpoint incident and the second Hardware Breakpoint incident, and the track of events that takes place subsequently is processed the device response.
Preferably, on-line debugging real time monitoring process is: when SQC [1:0]=2 ' b00, SQA in the status register unit and SQB position all remain unchanged; The first Hardware Breakpoint incident and second at least one generation of Hardware Breakpoint incident are also responded then by CPU that Hardware Breakpoint incident generation flag MBO is put 1; Track of events takes place and is responded then by CPU that track of events generation flag TO is put 1.
When SQC [1:0]=2 ' b01, track of events takes place and is embedded into the formula processor to respond in the combination event, and the SQA in the status register unit remains unchanged, and SQB is put 1; Hardware Breakpoint incident generation flag MBO remains unchanged; Track of events generation flag TO is put 1.
When SQC [1:0]=2 ' b10, the second Hardware Breakpoint incident takes place and is embedded into the formula processor to respond in the combination event, and the SQA in the status register unit is put 1, and SQB remains unchanged; Hardware Breakpoint incident generation flag MBO is put 1; Track of events generation flag TO remains unchanged.
When SQC [1:0]=2 ' b11, track of events takes place and is embedded into the formula processor to respond in the combination event, and SQA in the status register unit and SQB are all put 1; Hardware Breakpoint incident generation flag MBO remains unchanged; Track of events generation flag TO is put 1.
Among the present invention, Hardware Breakpoint incident and track of events add up to n, n is a natural number; And n >=2, the combination event quantity that a situation arises is m, the quantity a of combination event control bit; Satisfy 2a >=m, make that the combination event control bit can the corresponding generation of controlling the various combination incident.
Beneficial effect of the present invention is: control hardware breakpoint event and track of events take place according to the specific combined order and carry out real time monitoring, effectively reduce the difficulty of on-line debugging.
Description of drawings
Fig. 1 is the TAP state machine interface synoptic diagram of JTAG.
Fig. 2 controls the schematic flow sheet of three kinds of hardware events for the software debugging personnel.
Fig. 3 is a register cell steering logic synoptic diagram.
Fig. 4 is three kinds of overall logic synoptic diagram that the hardware event combination takes place.
The logical schematic that hardware event independently took place when Fig. 5 was SQC [1:0]=2 ' b00.
The logical schematic that the combination event that the second Hardware Breakpoint incident and track of events constituted when Fig. 6 was SQC [1:0]=2 ' b01 takes place.
The logical schematic that the combination event that the first Hardware Breakpoint incident and the second Hardware Breakpoint incident constituted when Fig. 7 was SQC [1:0]=2 ' b10 takes place.
The logical schematic that the combination event that the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events constituted when Fig. 8 was SQC [1:0]=2 ' b11 takes place.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described:
With reference to Fig. 1～Fig. 8, the interface arrangement of eventful control of a kind of on-line debugging and real time monitoring.
Described three kinds of hardware events, like Fig. 2, three kinds of hardware events are by the inner separate logical block Hardware Breakpoint event generator A (Fig. 2-7) of flush bonding processor, Hardware Breakpoint event generator B (Fig. 2-8), track of events generator (Fig. 2-9) produces.
Described jtag interface unit; As shown in Figure 1; The jtag interface unit comprises that mainly a TAP state machine that contains 16 states controls the input and output of flush bonding processor data, and the jtag interface unit has five signal wire TCLK, TMS, TRST, TDI, TDO to be connected to external pin.Wherein, TCLK provides the external drive clock for the jtag interface unit; TMS drives the TAP state machine; The TRST jtag interface unit that is used for resetting; TDI serial ground is to flush bonding processor input data; TDO serial ground is from the flush bonding processor output data.These five pins are connected with in-circuit debugger ICE (Fig. 2-2), and the commissioning staff carries out interactive communication through top connection and flush bonding processor.
Described command register unit (Fig. 2-4) and read-write control bit W/R wherein; Register is selected control bit RS [4:0]; As shown in Figure 1; The inside, jtag interface unit writes data to the control path that IR operates to command register unit (Fig. 2-4) the inside through the TAP state machine, and (Fig. 2-4) makes it effective to the command register unit with Data Update at Update IR state; As shown in Figure 3, register selects control bit RS [4:0] to select a purpose operation note, mainly is used for selecting control register unit and status register unit as the purpose operation note in the present invention; As shown in Figure 3, read-write control bit W/R carries out write operation to the purpose operation note of choosing when W/R=0, when W/R=1, the purpose operation note of choosing is carried out read operation.
Described control register unit (Fig. 2-5), as shown in Figure 3, the control register unit is selected during as the purpose operation note, decides according to the read-write control bit W/R of the inside, command register unit the control register unit is read or write operation; As shown in Figure 1; The jtag interface unit receives the data (perhaps sending data to host computer) that host computer sends through the interface with IDE; Receive data that host computer sends through the write control register of TAP state machine to the operation serial of DR; To the reading from the control register the inside of the operation serial of DR, read at Update DR state write command register cell or from the order register cell by data through the TAP state machine for the data of sending to host computer.
Described status register unit (Fig. 2-6), as shown in Figure 3, the status register unit is selected during as the purpose operation note, and status register is a read-only register, and this moment, no matter the W/R position was 1 or 0, all can only carry out read operation to status register; As shown in Figure 1, the inside, jtag interface unit is through from the status register the inside sense data of TAP state machine to the operation serial of DR, and data are read from the status register unit at Update DR state.Shown in Fig. 2-1, Fig. 2-2, Fig. 2-3, the data of reading from the status register unit send to host computer through being connected of jtag interface unit and ICE.
Combination event flag, hardware event flag inside the combination event control bit SQC [1:0] of described control register unit (Fig. 2-5) the inside and the status register (Fig. 2-6) are like Fig. 4～shown in Figure 8.
When SQC [1:0]=2 ' b00, as shown in Figure 5, the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, the relatively independent separately generation of track of events.SQA and SQB remain unchanged; Can be embedded into the response of formula processor after the first Hardware Breakpoint incident takes place, MBO is put 1; Can be embedded into the response of formula processor after the second Hardware Breakpoint incident takes place, MBO is put 1; Can be embedded into the response of formula processor after track of events takes place, TO is put 1.
When SQC [1:0]=2 ' b01; As shown in Figure 6; The second Hardware Breakpoint incident and track of events constitute a combination, and only track of events just possibly take place after one second Hardware Breakpoint incident takes place, when track of events takes place and be embedded into the formula processor to respond; The combination event flag SQA of the inside, status register unit remains unchanged, and SQB is put 1; The first Hardware Breakpoint incident generation can be embedded into the response of formula processor, and MBO is put 1; Can not be embedded into the response of formula processor after the second Hardware Breakpoint incident takes place, MBO remains unchanged; Can be embedded into the response of formula processor after track of events takes place, TO is put 1.
When SQC [1:0]=2 ' b10; As shown in Figure 7, the first Hardware Breakpoint incident and the second Hardware Breakpoint incident constitute a combination, and only the second Hardware Breakpoint incident just possibly take place after one first Hardware Breakpoint incident takes place;, the second Hardware Breakpoint incident can be embedded into the response of formula processor after taking place; The combination event flag SQA of the inside, status register unit is put 1, and SQB remains unchanged, and MBO is put 1; Can not be processed the device response after the first Hardware Breakpoint incident takes place, MBO remains unchanged; Can be embedded into the response of formula processor after track of events takes place, TO is put 1.
When SQC [1:0]=2 ' b11, as shown in Figure 8, this kind information summary above two kinds of combination events; The first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events constitute a combination; Only take place under the exciting of one second Hardware Breakpoint incident in one first Hardware Breakpoint incident of generation, track of events just might take place again, and can be embedded into the response of formula processor after track of events takes place; Combination event flag SQA in the status register unit, SQB are all put 1, and the TO position is put 1; The generation of the first Hardware Breakpoint incident and the second Hardware Breakpoint incident all can not be embedded into the response of formula processor, and MBO remains unchanged.
Through embodiment the present invention has been described; Command register unit that relates among the present invention who describes in the accompanying drawing and control bit W/R wherein, RS [4:0]; Control register unit and control bit SQC [1] wherein, SQC [0]; Status register unit and flag SQA wherein, SQB, MBO, TO, the figure place of these register cells can freely be adjusted according to the needs of programming model, and control bit and flag also can freely exist in the position of corresponding registers the inside; SQC [1] and SQC [0] can control the combination of three kinds of hardware events according to any mode freely, and these all distortion and variation all should be included in claim of the present invention the inside.
Claims (8)
1. the interface arrangement of eventful control of an on-line debugging and real time monitoring, it is characterized in that: described interface arrangement comprises:
The hardware event unit comprises Hardware Breakpoint event generator and track of events generator, and the Hardware Breakpoint incident is produced by the Hardware Breakpoint event generator; Track of events is produced by the track of events generator;
The jtag interface unit based on the standard communication interface of IEEE Std 1149.1 agreements, is used to receive host computer and sends to the control command of flush bonding processor and the flush bonding processor status information is exported to host computer in the on-line debugging;
The command register unit is used for carrying out through the selection control register unit of jtag interface unit reception host computer transmission and to the control register unit order of write operation; Carry out the order of read operation through the selection mode register cell of jtag interface unit reception host computer transmission and to the status register unit;
The control register unit; Be used for choosing the control register unit and the control register unit being carried out the order of write operation through what the jtag interface unit sent when the command register unit receives host computer, the control register unit begin to receive the order that host computer sends through the jtag interface unit so that control combination event that the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events and the first Hardware Breakpoint incident, the second Hardware Breakpoint incident and track of events constitute effectively with invalid;
The status register unit is used to preserve the status information that the back flush bonding processor takes place for the said first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events and combination event.
2. the interface arrangement of eventful control of on-line debugging as claimed in claim 1 and real time monitoring is characterized in that: said track of events generator has one, and said Hardware Breakpoint event generator has more than two at least.
3. the interface arrangement of eventful control of on-line debugging as claimed in claim 2 and real time monitoring; It is characterized in that: said track of events generator has one; Said Hardware Breakpoint event generator has two, is respectively the first Hardware Breakpoint event generator and the second Hardware Breakpoint event generator.
4. like the interface arrangement of eventful control of the described on-line debugging of one of claim 1～3 and real time monitoring; It is characterized in that: a read-write control bit W/R in the said command register unit; When W/R=0, then write data, if W/R=1 register cell sense data then from choosing to the register cell of choosing; Select control bit RS [4:0] for five in the command register unit, RS [4:0] selects 32 register cells of control, and control register unit and status register unit are two in these 32 register cells.
5. like the interface arrangement of eventful control of the described on-line debugging of one of claim 1～3 and real time monitoring; It is characterized in that: two bit pattern incident control bit SQC [1:0] in the said control register unit, the generation of the corresponding respectively control different combinations of SQC=2 ' b00, SQC=2 ' b01, SQC=2 ' b10, SQC=2 ' b11 incident.
6. like the interface arrangement of eventful control of the described on-line debugging of one of claim 1～3 and real time monitoring; It is characterized in that: the Hardware Breakpoint incident generation flag MBO in the said status register unit, when the Hardware Breakpoint incident takes place and the formula processor of being embedded into responds then that MBO is put 1; Track of events generation flag TO in the status register unit is when track of events takes place and the formula processor of being embedded into responds then the TO position and put 1; Two one combination event generation flag SQA and SQB in the status register unit, the combination event that constitutes when Hardware Breakpoint incident and track of events takes place and the formula processor of being embedded into responds then that SQA and SQB can be put 1 accordingly.
7. the interface arrangement of eventful control of on-line debugging as claimed in claim 5 and real time monitoring; It is characterized in that: as SQC [1:0]=2 ' b00; And the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled; The separate generation of the said first Hardware Breakpoint incident, the second Hardware Breakpoint incident and track of events, and all can be embedded into the response of formula processor;
As SQC [1:0]=2 ' b01; And the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled; One time second Hardware Breakpoint incident must at first take place in the generation of track of events; Wherein the second Hardware Breakpoint incident is not processed the device response, and the track of events that takes place subsequently is processed the device response;
As SQC [1:0]=2 ' b10; And the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled; The second Hardware Breakpoint incident takes place one time first Hardware Breakpoint incident must at first take place; Wherein the first Hardware Breakpoint incident is not processed the device response, and the second Hardware Breakpoint incident that takes place subsequently is processed the device response;
As SQC [1:0]=2 ' b11; And the first Hardware Breakpoint incident, the second Hardware Breakpoint incident, track of events all are enabled; One time first Hardware Breakpoint incident must formerly take place and take place just possibly take place under the exciting of one time second Hardware Breakpoint incident again in track of events; Wherein the response of formula processor takes place all not to be embedded in the first Hardware Breakpoint incident and the second Hardware Breakpoint incident, and the track of events that takes place subsequently is processed the device response.
8. the interface arrangement of eventful control of on-line debugging as claimed in claim 5 and real time monitoring is characterized in that: when SQC [1:0]=2 ' b00, SQA in the status register unit and SQB position remain unchanged; The first Hardware Breakpoint incident and second at least one generation of Hardware Breakpoint incident are also responded then by CPU that Hardware Breakpoint incident generation flag MBO is put 1; Track of events takes place and is responded then by CPU that track of events generation flag TO is put 1;
When SQC [1:0]=2 ' b01, track of events takes place and is embedded into the formula processor to respond in the combination event, and the SQA in the status register unit remains unchanged, and SQB is put 1; Hardware Breakpoint incident generation flag MBO remains unchanged; Track of events generation flag TO is put 1;
When SQC [1:0]=2 ' b10, the second Hardware Breakpoint incident takes place and is embedded into the formula processor to respond in the combination event, and the SQA in the status register unit is put 1, and SQB remains unchanged; Hardware Breakpoint incident generation flag MBO is put 1; Track of events generation flag TO remains unchanged;
When SQC [1:0]=2 ' b11, track of events takes place and is embedded into the formula processor to respond in the combination event, and SQA in the status register unit and SQB are all put 1; Hardware Breakpoint incident generation flag MBO remains unchanged; Track of events generation flag TO is put 1.
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Application publication date: 20120613 |