CN102487013A - Method for forming grid - Google Patents
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- CN102487013A CN102487013A CN2010105714194A CN201010571419A CN102487013A CN 102487013 A CN102487013 A CN 102487013A CN 2010105714194 A CN2010105714194 A CN 2010105714194A CN 201010571419 A CN201010571419 A CN 201010571419A CN 102487013 A CN102487013 A CN 102487013A
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Abstract
The invention provides a method for forming a grid. The method comprises the following steps of: providing a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a forged grid structure in the dielectric layer, wherein the forged grid structure comprises a forged grid and a grid dielectric layer positioned between the semiconductor substrate and the forged grid, and side walls are arranged at the periphery of the forged grid structure; removing parts of the forged grid and the side walls by using first wet-process etching, forming a first groove in the forged grid and the side walls, wherein the width of the top part of the first groove is more than that of the bottom part of the first groove, and the etching selection ratio of the first wet-process etching for the forged grid and the side walls is less than 19; removing the remaining forged grid by second wet-process etching and forming a grid groove; and filling a grid material into the grid groove and forming the grid. The method contribute to the filling of the grid material, improving the filling performance of the filling material and avoiding or at least reducing the gap in the grid. In addition, the semiconductor substrate can not be damaged.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the method that forms grid.
Background technology
In the prior art, the technology that forms grid can be divided into preceding grid (gate first) technology and back grid (gate last) technology.Preceding grid technique is meant deposition gate dielectric layer earlier, on gate dielectric layer, forms gate electrode, carries out the source then and leaks injection, carries out annealing process afterwards with the ion in the activation of source leakage.Preceding its processing step of grid technique is simple, but when annealing, gate electrode will bear high temperature inevitably, causes the threshold voltage vt drift of metal-oxide-semiconductor, influences the pipe performance.Back grid technique is meant behind annealing process, promptly after high-temperature step, etches away the pseudo-grid of polysilicon; Form pseudo-gate groove, again with suitable metal filled pseudo-gate groove to form gate electrode, can make gate electrode avoid high temperature like this; Avoid the threshold voltage vt drift of metal-oxide-semiconductor, influence the pipe performance.
Back grid technique can be widened the material chosen scope of gate electrode greatly, and is complicated more but technology becomes.When forming metal gate electrode; Along with dimensions of semiconductor devices is more and more littler, particularly in 32nm and following technology, because pseudo-gate groove width diminishes; Make the charging efficiency of metal material be difficult to reach absolutely; Can exist certain clearance in the middle of the metal promptly in pseudo-gate groove, inserted, the gap not only can increase the dead resistance of gate electrode, but also can cause problem such as metal-oxide-semiconductor reliability reduction.
On February 24th, 2010, disclosed publication number disclosed a kind of method that forms metal gates for the one Chinese patent application disclosed " integrated circuit metal gate structure and manufacturing approach thereof " of " CN101656205A ", comprising: Semiconductor substrate is provided; On said Semiconductor substrate, form dummy gate structure, wherein, said dummy gate structure comprises polysilicon; Remove said dummy gate structure, so that the groove with top and bottom to be provided, wherein said top and said bottom have first width; Increase the top width of said groove, so that second width to be provided; And, in comprising the said groove of said second width, forming grid, the step of wherein said formation grid comprises first Metal Deposition in said groove.The method of disclosed formation metal gates in this patent documentation after removing dummy gate structure, increases the width at groove top, in groove, fills metal after being beneficial to, and improves the fillibility of metal.Yet, utilize argon (Ar) sputtering technology to increase the groove top width in this patent documentation, easy like this substrate is damaged.
Summary of the invention
The problem that the present invention solves is that the method for the formation metal gates of prior art is damaged substrate easily.
For addressing the above problem, the present invention provides a kind of method that forms grid, comprising:
Semiconductor substrate is provided; On said Semiconductor substrate, be formed with dielectric layer; In said dielectric layer, be formed with dummy gate structure, said dummy gate structure comprises dummy grid and the gate dielectric layer between said Semiconductor substrate and dummy grid, has side wall around the said dummy gate structure;
First wet etching is removed said dummy grid of part and side wall; On said dummy grid and said side wall, form first groove; The top width of said first groove is greater than bottom width, said first wet etching to the etching selection ratio of said dummy grid and said side wall less than 19;
Second wet etching is removed remaining dummy grid, forms gate trench;
In said gate trench, fill grid material, form grid.
Optional, said second wet etching is removed remaining dummy grid, forms gate trench and comprises:
Second wet etching is removed remaining dummy grid, forms the gate trench that exposes said gate dielectric layer.
Optional, said second wet etching is removed remaining dummy grid, forms gate trench and comprises:
Second wet etching is removed remaining dummy grid, removes gate dielectric layer afterwards, forms second groove that exposes said Semiconductor substrate;
In said second groove, form the high K medium layer, said k value covers the sidewall and the bottom of said second groove greater than 4.5, forms gate trench.
Optional, the height of said first groove is 1/4～4/5 of a said dummy grid height; The top width of said first groove is 21/20～3/2 of a said dummy grid width.
Optional, contain nitric acid and ammonium fluoride in the solution that said first wet etching uses.
Optional, contain nitric acid and hydrofluoric acid in the solution that said first wet etching uses.
Optional, the solution that said second wet etching uses is tetramethyl ammonium hydroxide solution.
Optional, the sidewall of the said side wall that said first groove exposes along the angle that counterclockwise departs from said semiconductor substrate surface greater than 93 °.
Optional, remove gate dielectric layer with the 3rd wet etching.
Optional, the material of said dummy grid is selected from a kind of in silicon, germanium, germanium silicon, silicon nitride, the silica or their combination in any.
Optional, said grid material is selected from metal silicide one of them or theys' the combination in any of metal carbides, the conduction of metal nitride, the conduction of hafnium, zirconium, titanium, aluminium, tantalum, palladium, platinum, cobalt, nickel, tungsten, silver, copper, gold, conduction.
Compared with prior art, the present invention has the following advantages:
The present invention forms the method for grid; After forming dummy gate structure on the Semiconductor substrate; At first use dummy grid and side wall are had low the selection than first wet etching removal part dummy grid of (less than 19) and the side wall around the dummy grid, formation first groove on dummy grid and side wall, the top width of first groove is greater than bottom width; And then use second wet etching that dummy grid and side wall are had a high selectivity to remove remaining dummy grid; Form gate trench, the top width of this gate trench is filled grid material afterwards and is formed grid naturally greater than bottom width in gate trench.Because the gate trench top width that forms helps the filling of grid material greater than bottom width, improves the filling capacity of grid material, avoids or reduce at least in grid, forming the space.And the present invention utilizes wet etching (first wet etching and second wet etching) to form the gate trench of top width greater than bottom width, thereby can not damage Semiconductor substrate.
In specific embodiment of the present invention; Also remove gate dielectric layer after removing remaining dummy grid; Form second groove, in second groove, form one deck high K medium layer afterwards earlier, the bottom and the sidewall that cover second groove form gate trench; The top width of this gate trench is filled grid material then and is formed grid naturally greater than bottom width.The specific embodiment of the invention has formed the high K medium layer around the grid like this, can further solve because along with the dwindling of semiconductor device, and the corresponding attenuation of thickness of corresponding gate dielectric layer causes the problem of leakage current easily.
Description of drawings
Fig. 1 is the flow chart of method of the formation grid of the specific embodiment of the invention;
Fig. 2 a～Fig. 2 f is the cross-sectional view of method of the formation grid of first embodiment of the invention;
Fig. 3 a～Fig. 3 e is the cross-sectional view of method of the formation grid of second embodiment of the invention.
Embodiment
The method of the formation grid of the specific embodiment of the invention; After forming dummy gate structure on the Semiconductor substrate; At first use dummy grid and side wall are had low the selection than first wet etching removal part dummy grid of (less than 19) and the side wall around the dummy grid, formation first groove on dummy grid and side wall, the top width of first groove is greater than bottom width; And then use second wet etching that dummy grid and side wall are had a high selectivity to remove remaining dummy grid; Form gate trench, the top width of this gate trench is filled grid material afterwards and is formed grid naturally greater than bottom width in gate trench.Because the gate trench top width that forms helps the filling of grid material greater than bottom width, improves the filling capacity of grid material, avoids or reduce at least in grid, forming the space.And the present invention utilizes wet etching to form the gate trench of top width greater than bottom width, can not damage Semiconductor substrate.
In order to make those skilled in the art can better understand the present invention, specify embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of method of the formation grid of the specific embodiment of the invention, and with reference to figure 1, the method for the formation grid of the specific embodiment of the invention comprises:
Step S11; Semiconductor substrate is provided; On said Semiconductor substrate, be formed with dielectric layer; In said dielectric layer, be formed with dummy gate structure, said dummy gate structure comprises dummy grid and the gate dielectric layer between said Semiconductor substrate and dummy grid, has side wall around the said dummy gate structure;
Step S12; First wet etching is removed said dummy grid of part and side wall; On said dummy grid and said side wall, form first groove, the top width of said first groove is greater than bottom width, said first wet etching to the etching selection ratio of said dummy grid and said side wall less than 19;
Step S13, second wet etching is removed remaining dummy grid, forms gate trench;
Step S14 fills grid material in said gate trench, form grid.
Fig. 2 a～Fig. 2 f is the cross-sectional view of method of the formation grid of first embodiment of the invention; In order to make those skilled in the art can better understand the method for the formation grid of the specific embodiment of the invention, also combine the method with the formation grid of Fig. 2 a～Fig. 2 f detailed description specific embodiment of the invention with reference to figure 1 below in conjunction with specific embodiment.
In conjunction with reference to figure 1 and Fig. 2 c; Execution in step S11; Semiconductor substrate 20 is provided, on said Semiconductor substrate 20, is formed with dielectric layer 23, in said dielectric layer 23, be formed with dummy gate structure; Said dummy gate structure comprises dummy grid 22 and the gate dielectric layer 21 between said Semiconductor substrate 20 and dummy grid 22, has side wall 24 around the said dummy gate structure.Be specially:
With reference to figure 2a, Semiconductor substrate 20 is provided, on said Semiconductor substrate, form successively gate dielectric layer 21 ' with thin layer 22 '.The material of Semiconductor substrate 20 can be the silicon or the SiGe of monocrystalline or non crystalline structure; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.In said Semiconductor substrate 20, be formed with the device architecture (not shown), for example isolation trench structure etc.Gate dielectric layer 21 ' material can well known to a person skilled in the art material for silica etc., select silica for use in this specific embodiment.Thin layer 22 ' material be selected from a kind of in silicon, germanium, germanium silicon, silicon nitride, the silica or their combination in any, select polysilicon in the specific embodiment of the invention for use.
With reference to figure 2b; Utilize photoetching, the graphical gate dielectric layer of etching technics and thin layer, form dummy gate structure, said dummy gate structure comprises dummy grid 22 and gate dielectric layer 21; The corresponding gate dielectric layer 21 of gate dielectric layer after graphical, the corresponding dummy grid 22 of thin layer after graphical.The material of corresponding dummy grid 22 is selected from a kind of in silicon, germanium, germanium silicon, silicon nitride, the silica or their combination in any.It in the specific embodiment of the invention polysilicon gate.
With reference to figure 2c, after the formation dummy gate structure, Semiconductor substrate 20 is carried out the source leak injection, in Semiconductor substrate 20, form source region and drain region (not shown), and around dummy grid 22, form side wall 24.Form dielectric layer 23 afterwards, cover the surface of said dummy gate structure and Semiconductor substrate 20, the material of dielectric layer 23 can well known to a person skilled in the art material for silica etc., selects silica in the specific embodiment of the invention for use.Form dielectric layer 23 backs to dielectric layer 23 planarizations, the surface that makes dielectric layer 23 is surperficial equal with dummy grid 22.
In conjunction with reference to figure 1 and Fig. 2 d; Execution in step 12; First wet etching is removed said dummy grid 22 of part and side wall 24; On said dummy grid 22 and said side wall 24, form first groove 25, the top width of said first groove 25 is greater than bottom width, said first wet etching to the etching selection ratio of said dummy grid 22 and said side wall 24 less than 19.Wherein, for said Semiconductor substrate 20, the bottom of first groove 25 is near Semiconductor substrate 20, and the top is away from Semiconductor substrate 20.The height H of first groove 25 is 1/4～4/5 of dummy grid height h, and the top width D of said first groove 25 is 21/20～3/2 of said dummy grid width d.In the specific embodiment of the invention; First groove 25 be shaped as taper, certainly in other embodiments, the shape of first groove 25 is not limited to taper; Also can be other shapes; As long as the top width that satisfies first groove 25 is greater than bottom width, and the height H of first groove 25 is 1/4～4/5 of dummy grid height h, and the top width D of said first groove 25 is that 21/20～3/2 of said dummy grid width d gets final product.And in the specific embodiment of the invention, the angle C that said Semiconductor substrate 20 surfaces are counterclockwise departed from sidewall 241 edges of the said side wall 24 that first groove 25 exposes is greater than 93 °.Like this after form gate trench after, when in gate trench, filling metal, can be easy to metal filled in gate trench, avoid forming the space.
Among the present invention, contain nitric acid and ammonium fluoride in the solution that said first wet etching uses.In the specific embodiment of the invention, nitric acid in the solution that first wet etching uses: water: ammonium fluoride equals 126: 60: 5 (126HNO
3: 60H
2O: 5NH
4F), with this solution wet etching side wall 24 during, it is 11: 1 to the etching selection ratio of dummy grid 22 and side wall 24 with dummy grid 22.In other embodiments of the invention; Can adjust the etching selection ratio of first wet etching through the ratio of adjustment nitric acid, water, ammonium fluoride to dummy grid 22 and side wall 24; Can obtain the etching selection ratio lower, help forming first groove of top greater than the bottom than 11: 1.About nitric acid: water: the ratio of ammonium fluoride and the detailed content of etch rate; The article " etch rates for micromach processing " that can on " Journal of MEMS; Vol.5No4, Dec, 1996 ", deliver referring to " K.Williams and R.Muller ".
In the present invention, said first wet etching also can use the solution that contains nitric acid and hydrofluoric acid.Can adjust the etching selection ratio of first wet etching through the ratio of adjustment nitric acid, water, hydrofluoric acid, can obtain low etching selection ratio, help forming first groove of top greater than the bottom to dummy grid 22 and side wall 24.
In the specific embodiment of the invention, need to prove, carry out first wet etching when forming first groove, in order not damage dielectric layer 23, need form mask layer on the surface of dielectric layer 23, for example, the silicon nitride mask layer is protected dielectric layer 23.
In conjunction with reference to figure 1 and Fig. 2 e, execution in step S13, second wet etching is removed remaining dummy grid, forms gate trench 26.In first embodiment, utilize second wet etching to remove remaining dummy grid, form the gate trench 26 that exposes said gate dielectric layer 21.The top of this gate trench 26 is the top of above-described first groove, so the top width of gate trench 26 is greater than bottom width, and top width is 21/20～3/2 of bottom width, is 21/20～3/2 of said dummy grid width.
In the specific embodiment of the invention; The solution that second wet etching uses is TMAH (TMAH) solution; Tetramethyl ammonium hydroxide solution is very high to the etching selection ratio of dummy grid 22 and side wall 24; Hardly side wall 24 is carried out etching, therefore can utilize tetramethyl ammonium hydroxide solution to remove remaining dummy grid 22, and can remove remaining side wall 24 hardly.Certainly; In the present invention; Second wet etching also can use other solution, and this solution need have high etching selection ratio to dummy grid 22 and side wall 24, removes remaining dummy grid 22 to reach; And considerably less to the removal amount of remaining side wall 24, can not influence the performance of the device of final formation.
In conjunction with reference to figure 1 and Fig. 2 f, execution in step S14 fills grid material said gate trench 26 in, formation grid 27.The material of said grid 27 is selected from the metal nitride of hafnium (Hf), zirconium (Zr), titanium (Ti), aluminium (Al), tantalum (Ta), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), tungsten (W), silver (Ag), copper (Cu), gold (Au), conduction, the metal carbides of conduction, one of them perhaps their combination of metal silicide of conduction.The concrete grammar that forms grid 27 is: utilize vapour deposition; For example physical vapor deposition (PVD), chemical vapor deposition (CVD) are filled grid material in said gate trench; And fill up gate trench, afterwards, utilize flatening process; For example cmp planarized gate material finally forms grid 27.In the specific embodiment of the invention, select for use metallic aluminium as grid material.Utilize physical gas-phase deposite method to fill metallic aluminium in said gate trench; And when plated metal aluminium; On the surface of dielectric layer 23, also deposit metallic aluminium; Utilize flatening process to remove dielectric layer 23 lip-deep metallic aluminiums afterwards, form grid 27, the surface of grid 27 and dielectric layer 23 surperficial equal.
The method of the formation grid of first embodiment of the invention; After forming dummy gate structure on the Semiconductor substrate; At first remove part dummy grid and dummy grid side wall on every side with first wet etching, on dummy grid and side wall, form first groove, the top width of first groove is greater than bottom width; And then remove remaining dummy grid with second wet etching; Formation exposes the gate trench of gate dielectric layer, and the top width of this gate trench is filled grid material afterwards and formed grid naturally greater than bottom width in gate trench.Because the gate trench top width that forms helps the filling of grid material greater than bottom width, improves the filling capacity of grid material, avoids or reduce at least in grid, forming the space.And the present invention utilizes wet etching (comprising first wet etching and second wet etching) to form the gate trench of top width greater than bottom width, therefore can not damage Semiconductor substrate.
Fig. 3 a～Fig. 3 e is the cross-sectional view of method of the formation grid of second embodiment of the invention, below in conjunction with second embodiment and combine to specify with reference to figure 1 and Fig. 3 a～Fig. 3 e the method for the formation grid of the specific embodiment of the invention.
In conjunction with reference to figure 1 and Fig. 3 a; Execution in step S11; Semiconductor substrate 40 is provided, on said Semiconductor substrate 40, is formed with dielectric layer 43, in said dielectric layer 43, be formed with dummy gate structure; Said dummy gate structure comprises dummy grid 42 and the gate dielectric layer 41 between said Semiconductor substrate 40 and dummy grid 42, has side wall 44 around the said dummy gate structure.
Wherein, step S11 is identical with step S11 among first embodiment among second embodiment, does not do detailed description at this, can be with reference to above detailed description to step S11.
In conjunction with reference to figure 1 and Fig. 3 b; Execution in step 12; First wet etching is removed said dummy grid 42 of part and side wall 44; On said dummy grid 42 and said side wall 44, form first groove, the top width of said first groove is greater than bottom width, said first wet etching to the etching selection ratio of said dummy grid 42 and said side wall 44 less than 19.Wherein, step S12 is identical with step S12 among first embodiment among second embodiment, does not do detailed description at this, can be with reference to above detailed description to step S12.
In conjunction with reference to figure 1 and Fig. 3 d, execution in step S13, second wet etching remove remaining dummy grid 42, form gate trench 47.In a second embodiment, second wet etching is removed remaining dummy grid, formation gate trench 47 comprises: with reference to figure 3c, second wet etching is removed remaining dummy grid 42, removes gate dielectric layer 41 afterwards, forms second groove 46 that exposes said substrate 40; With reference to figure 3d, in said second groove 46, form high K medium layer 48, said k value covers the sidewall and the bottom of said second groove 46 greater than 4.5, forms gate trench 47.The top width of gate trench 47 is greater than bottom width, and the width at top is 21/20～3/2 of bottom width, is 21/20～3/2 of said dummy grid width.
In the present invention's second specific embodiment; The solution that second wet etching uses is TMAH (TMAH) solution; Tetramethyl ammonium hydroxide solution is very high to the etching selection ratio of dummy grid 42 and side wall 44; Hardly side wall 44 is carried out etching, therefore can utilize tetramethyl ammonium hydroxide solution to remove remaining dummy grid 42, and can remove remaining side wall 44 hardly.Certainly; In the present invention; Second wet etching also can use other solution, and this solution need have high etching selection ratio to dummy grid 42 and side wall 44, removes remaining dummy grid 42 to reach; And considerably less to the removal amount of remaining side wall 44, can not influence the performance of the device of final formation.After removing remaining dummy grid, to utilize wet etching to remove gate dielectric layer and expose substrate, in the specific embodiment of the invention, the material of gate dielectric layer is a silicon dioxide, the solution that uses in the wet etching is hydrofluoric acid (HF) solution.
In embodiments of the present invention, utilize CVD method, for example physical vapor deposition (PVD), chemical vapor deposition (CVD) form high K medium layer 48, cover the surface of sidewall and the bottom and the dielectric layer 43 of said second groove; In instantiation, according to the material chosen corresponding sedimentary method of high K medium layer.In the present invention, the material of said high K medium layer is selected from hafnium oxide (HfO
2), silicon oxidation hafnium (HfSiO), nitrogen hafnium oxide (HfON), nitrogen hafnium silicon oxide (HfSiON), lanthana (La
2O
3), zirconia (ZrO
2), silicon oxidation zirconium (ZrSiO), titanium oxide (TiO
2), yittrium oxide (Y
2O
3).In the specific embodiment of the invention; Select the material of silicon oxidation hafnium for use as the high K medium layer; Form silicon oxidation hafnium high K medium layer with chemical gaseous phase depositing process; This high K medium layer covers sidewall and bottom and the dielectric layer 43 of said second groove, the surface of side wall 44, removes the high K medium layer on dielectric layer 43, side wall 44 surfaces afterwards with chemical-mechanical planarization technology.
In conjunction with reference to figure 1 and Fig. 3 e, execution in step S14 fills grid material in said gate trench, form grid 49.Among the present invention, behind the formation high K medium layer, utilize vapour deposition, for example physical vapor deposition (PVD), chemical vapor deposition (CVD) are filled grid material in said gate trench, and fill up gate trench, form grid 49.In the specific embodiment of the invention, in said gate trench, and when plated metal aluminium, also deposit metallic aluminium on 44 surfaces at surface, the side wall of dielectric layer 43 with physical vapour deposition (PVD) plated metal aluminium; Then, utilize flatening process to remove dielectric layer 43 surfaces, side wall 44 lip-deep metallic aluminiums, form grid 49, the surface of grid 49 and dielectric layer 43 surperficial equal.
In second specific embodiment of the present invention, be formed with high K medium layer 48 at the bottom and the sidewall of grid 49, can prevent that like this thickness of corresponding gate dielectric layer causes the problem of leakage current easily also in corresponding attenuation along with the dwindling of semiconductor device.
The method of the formation grid of the second embodiment of the present invention after forming dummy gate structure on the Semiconductor substrate, is at first removed part dummy grid and dummy grid side wall on every side with first wet etching; On dummy grid and side wall, form first groove, the top width of first groove is removed remaining dummy grid with second wet etching then greater than bottom width; Wet etching is removed gate dielectric layer afterwards; Form second groove, then in second groove, form the high K medium layer earlier, cover the bottom and the sidewall of second groove; The top width of this gate trench is filled grid material then and is formed grid naturally greater than bottom width.The present invention utilizes wet etching (first wet etching, second wet etching and the 3rd wet etching) to form gate trench, thereby can not damage Semiconductor substrate.And, because the gate trench top width that forms helps the filling of grid material greater than bottom width, improve the filling capacity of grid material, avoid or reduce at least in grid, forming the space.In addition, because along with the dwindling of semiconductor device, the thickness of corresponding gate dielectric layer is also in corresponding attenuation, the easy like this problem that causes leakage current, and the present invention has formed the high K medium layer around grid, can well solve the problem of leakage current.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. a method that forms grid is characterized in that, comprising:
Semiconductor substrate is provided; On said Semiconductor substrate, be formed with dielectric layer; In said dielectric layer, be formed with dummy gate structure, said dummy gate structure comprises dummy grid and the gate dielectric layer between said Semiconductor substrate and dummy grid, has side wall around the said dummy gate structure;
First wet etching is removed said dummy grid of part and side wall; On said dummy grid and said side wall, form first groove; The top width of said first groove is greater than bottom width, said first wet etching to the etching selection ratio of said dummy grid and said side wall less than 19;
Second wet etching is removed remaining dummy grid, forms gate trench;
In said gate trench, fill grid material, form grid.
2. the method for formation grid as claimed in claim 1 is characterized in that, said second wet etching is removed remaining dummy grid, forms gate trench and comprises:
Second wet etching is removed remaining dummy grid, forms the gate trench that exposes said gate dielectric layer.
3. the method for formation grid as claimed in claim 1 is characterized in that, said second wet etching is removed remaining dummy grid, forms gate trench and comprises:
Second wet etching is removed remaining dummy grid, removes gate dielectric layer afterwards, forms second groove that exposes said Semiconductor substrate;
In said second groove, form the high K medium layer, said k value covers the sidewall and the bottom of said second groove greater than 4.5, forms gate trench.
4. like the method for each described formation grid of claim 1～3, it is characterized in that the height of said first groove is 1/4～4/5 of a said dummy grid height; The top width of said first groove is 21/20～3/2 of a said dummy grid width.
5. like the method for each described formation grid of claim 1～3, it is characterized in that, contain nitric acid and ammonium fluoride in the solution that said first wet etching uses.
6. like the method for each described formation grid of claim 1～3, it is characterized in that, contain nitric acid and hydrofluoric acid in the solution that said first wet etching uses.
7. like the method for each described formation grid of claim 1～3, it is characterized in that the solution that said second wet etching uses is tetramethyl ammonium hydroxide solution.
8. like the method for each described formation grid of claim 1～3, it is characterized in that, the sidewall of the said side wall that said first groove exposes along the angle that counterclockwise departs from said semiconductor substrate surface greater than 93 °.
9. the method for formation grid as claimed in claim 3 is characterized in that, removes said gate dielectric layer with the 3rd wet etching.
10. the method for formation grid as claimed in claim 1 is characterized in that, the material of said dummy grid is selected from a kind of in silicon, germanium, germanium silicon, silicon nitride, the silica or their combination in any.
11. the method for formation grid as claimed in claim 1; It is characterized in that said grid material is selected from metal silicide one of them or theys' the combination in any of metal carbides, the conduction of metal nitride, the conduction of hafnium, zirconium, titanium, aluminium, tantalum, palladium, platinum, cobalt, nickel, tungsten, silver, copper, gold, conduction.
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| CN103681273A (en) * | 2012-09-06 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Metal gate manufacturing method |
| WO2015021670A1 (en) * | 2013-08-13 | 2015-02-19 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN104752180A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN104979174A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device formation method |
| CN105097696A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method therefor and electronic device |
| CN105185706A (en) * | 2014-05-30 | 2015-12-23 | 中芯国际集成电路制造(上海)有限公司 | Method for removing pseudo grids |
| CN115225057A (en) * | 2022-09-19 | 2022-10-21 | 苏州汉天下电子有限公司 | Carrier, manufacturing method and application thereof |
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