CN102479710A - Transistor and manufacturing method for same - Google Patents
Transistor and manufacturing method for same Download PDFInfo
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- CN102479710A CN102479710A CN2010105600812A CN201010560081A CN102479710A CN 102479710 A CN102479710 A CN 102479710A CN 2010105600812 A CN2010105600812 A CN 2010105600812A CN 201010560081 A CN201010560081 A CN 201010560081A CN 102479710 A CN102479710 A CN 102479710A
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- pillar
- separator
- epitaxial loayer
- semiconductor substrate
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Abstract
The invention provides a transistor and a manufacturing method for the same. The method includes the steps: providing a semiconductor substrate; forming a support column on the semiconductor substrate; forming an isolating layer on the side wall of the support column; forming an extended layer covering the semiconductor substrate and the support column, wherein the thickness of the extended layer is larger than the height of the support column; forming a gate structure on the surface of the extended layer, wherein the gate structure is positioned above the support column; and forming a source region and a drain region on two sides of the gate structure inside the extended layer, wherein the source region and the drain region are positioned on two sides of each of the support column and the isolating layer. By the aid of the method, the short-channel effect and the performance of the transistor are improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and preparation method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is made, and they are in various integrated circuits, and the doping type during according to main charge carrier and manufacturing is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of transistorized manufacture method.Please refer to Fig. 1 to Fig. 3, be the transistorized manufacture method cross-sectional view of prior art.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, form gate dielectric layer 101 and grid 102 on the said Semiconductor substrate 100, said gate dielectric layer 101 constitutes grid structure with grid 102.
Continuation is carried out oxidation technology with reference to figure 1, forms the oxide layer 103 that covers said grid structure.
Then, please refer to Fig. 2, in the Semiconductor substrate of grid structure both sides, form light doping section 104, said light doping section 104 injects through ion and forms.
Then, please refer to Fig. 3, on the Semiconductor substrate of grid structure both sides, form the side wall 105 of grid structure.Carry out source/drain region heavy doping and inject (S/D), in the Semiconductor substrate 100 of grid structure both sides, form source region 106 and drain region 107.
, publication number can find more information in being the one Chinese patent application of CN101789447A about prior art.
Find that in reality the transistor short-channel effect that existing method is made is obvious, the performance of device is undesirable.
Summary of the invention
The problem that the present invention solves has provided a kind of transistor and preparation method thereof, has suppressed transistorized short-channel effect, has improved transistorized performance.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided;
On said Semiconductor substrate, form pillar;
Sidewall at said pillar forms separator;
Form the epitaxial loayer that covers said Semiconductor substrate and pillar, the thickness of said epitaxial loayer is greater than the height of said pillar;
Form grid structure in epi-layer surface, said grid structure is positioned at said pillar top;
In the epitaxial loayer of said grid structure both sides, form source region and drain region, said source region and drain region are positioned at the both sides of said pillar and separator.
Alternatively, the material of said pillar is semiconductor material or insulation material.
Alternatively, the material of said pillar is a polysilicon, and the manufacture method of pillar comprises:
On said Semiconductor substrate, form polysilicon layer;
The said polysilicon layer of etching forms said pillar.
Alternatively, the material of said separator is silica, silicon nitride, carborundum or silicon nitride.
Alternatively, the thickness range of said separator is 3～30 nanometers.
Alternatively, the width range of said pillar is 5 nanometers～1 micron.
Alternatively, the thickness of said epitaxial loayer is than high 20～100 nanometers of height of said pillar.
Correspondingly, the present invention also provides a kind of transistor, comprising:
Semiconductor substrate;
Epitaxial loayer is positioned on the said Semiconductor substrate;
Grid structure is positioned on the said epitaxial loayer;
Pillar is positioned at the epitaxial loayer of said grid structure below, and the height of said pillar is less than the thickness of said epitaxial loayer;
Separator is positioned at the sidewall of said pillar;
The source region is positioned at the epitaxial loayer of said pillar and separator one side;
The drain region is positioned at the epitaxial loayer of said pillar and separator opposite side.
Alternatively, the material of said pillar is semiconductor material, insulation material.
Alternatively, the material of said separator is silica, silicon nitride, carborundum or silicon nitride.
Alternatively, the thickness range of said separator is 3～30 nanometers.
Alternatively, the width range of said pillar is 5 nanometers～1 micron.
Alternatively, the thickness of said epitaxial loayer is than high 20～100 nanometers of height of said pillar.
Compared with prior art, the present invention has the following advantages:
Through on Semiconductor substrate, forming pillar and the separator that is positioned at the pillar both sides, then, form the epitaxial loayer that covers said pillar, in said epitaxial loayer, form source region and the drain region that is positioned at said pillar and separator both sides.Because said source region and drain region are positioned at the both sides of separator; Thereby said separator can prevent the dopant ion generation horizontal proliferation in said source region and drain region; Improved transistorized short-channel effect; And reduce the junction capacitance between source region or drain region and the Semiconductor substrate, reduced junction leakage, improved the performance of device.
Description of drawings
Fig. 1～Fig. 3 is the transistor fabrication method cross-sectional view of prior art;
Fig. 4 is a transistor fabrication method flow sketch map of the present invention;
Fig. 5～Figure 10 is the transistor fabrication method cross-sectional view of one embodiment of the invention.
Embodiment
The transistorized short-channel effect that existing method is made is obvious, and the performance of device is undesirable.Development along with semiconductor technology; Ultra shallow junction technology is applied to make source region and drain region; Dopant ion horizontal proliferation between source region and the drain region is more serious, thereby makes that described short-channel effect is more obvious, and source region and drain region and bigger junction capacitance and the junction leakage of Semiconductor substrate existence; Thereby reduced the response speed of device, influenced the performance of device.
In order to address the above problem, the inventor proposes a kind of transistorized manufacture method, please refer to transistor fabrication method flow sketch map of the present invention shown in Figure 4, and said method comprises:
Step S1 provides Semiconductor substrate;
Step S2 forms pillar on said Semiconductor substrate;
Step S3 is at the sidewall formation separator of said pillar;
Step S4 forms the epitaxial loayer that covers said Semiconductor substrate and pillar, and the thickness of said epitaxial loayer is greater than the height of said pillar;
Step S5 forms grid structure in epi-layer surface, and said grid structure is positioned at said pillar top;
Step S6 forms source region and drain region in the epitaxial loayer of said grid structure both sides, said source region and drain region are positioned at the both sides of said pillar and separator.
To combine specific embodiment that technical scheme of the present invention is at length explained below.
At first, please refer to Fig. 5, Semiconductor substrate 200 is provided.Said Semiconductor substrate 200 materials can be silicon or germanium silicon.On said Semiconductor substrate 200, form polysilicon layer 211.Said polysilicon layer 211 utilizes chemical vapor deposition method to make.Said polysilicon layer 211 is used to make pillar.Said pillar will be made separator at its sidewall in follow-up processing step, said separator will be used to isolate the source region and the drain region of follow-up formation.
Then, please refer to Fig. 6, the said polysilicon layer 211 of partial etching forms pillar 201 on said Semiconductor substrate 200.Said etching is a wet etching.
In the present embodiment, the material of said pillar 201 is a polysilicon.In other embodiment, the material of said pillar 201 can also be monocrystalline silicon, germanium, silica, silicon nitride, carborundum, silicon oxynitride etc.
In a preferred embodiment of the invention; The width of the transistorized channel region that the width considered of said pillar 201 will form and designing; Preferably, the width of said pillar 201 is equal to or slightly less than the width of said channel region, after forming separator on the said pillar 201; The thickness sum of said pillar 201 and separator and the width of said channel region are comparatively approaching, thereby make said separator can effectively isolate the diffusion of the dopant ion in source region and drain region.
As an embodiment, the width range of said pillar 201 is 5 nanometers～1 micron, and the width of for example said pillar 201 can be 5 nanometers, 500 nanometers or 1 micron.
Then, please continue, form the separator 202 of the sidewall that covers said pillar 201 with reference to figure 6.Said separator 202 is between the source region and drain region of follow-up formation, and said separator 202 tops also will form the epitaxial loayer that covers said pillar 201 and separator 202.
Said separator 202 is between the source region and drain region of follow-up formation; Thereby said separator 202 can prevent the dopant ion horizontal proliferation between said source region and the drain region; Thereby can prevent the appearance of short-channel effect, and said pillar can also reduce the junction capacitance between source region and drain region and the Semiconductor substrate 200.Because said post top portion will form epitaxial loayer, said epitaxial loayer will be as the channel region between said source region and the drain region, thereby said separator can not influence the conducting channel between source region and the drain region.
As one embodiment of the present of invention, the material of said separator 202 is the insulation material.Said insulation material can be silica, silicon nitride, carborundum or silicon nitride etc.Said separator 202 can be single layer structure, also can be sandwich construction.Said sandwich construction can be three-decker, for example is the ONO structure of silica-silicon-nitride and silicon oxide groove.
In the present embodiment; The thickness range of said separator 202 is 3～30 nanometers; Be preferably 5～30 nanometers, the thickness of for example said separator 202 can be 5 nanometers, 10 nanometers, 20 nanometers or 30 nanometers, and those skilled in the art can carry out concrete setting according to actual needs.
Then, please refer to Fig. 7, at said Semiconductor substrate 200 growing epitaxial layers 203, said epitaxial loayer 203 covers said pillar 201 and separator 202.Said epitaxial loayer 203 utilizes epitaxial growth technology to make.
The thickness of said epitaxial loayer 203 should be greater than the height of said pillar 201, thereby can be used as the source region of follow-up formation and the channel region between the drain region at the part epitaxial loayer 203 above the pillar 203.As an embodiment, the thickness of said epitaxial loayer 203 is than big 10～100 nanometers of height of said pillar 201.
Then, please refer to Fig. 8, on said epitaxial loayer 203, form grid structure, said grid structure is positioned at said pillar top.
As an embodiment, the manufacture method of said grid structure comprises:
On said epitaxial loayer 203, form gate dielectric layer 204, said gate dielectric layer 204 is positioned at said pillar 201 and separator 202 tops, and the material of said gate dielectric layer 204 is preferably silica, and the thickness range of said gate dielectric layer 204 is 10～300 dusts;
As the preferred embodiments of the present invention, after said grid structure forms, also need form oxide layer 206 in the said grid structure outside, said oxide layer 206 is used to protect said grid structure, prevents that said grid structure from receiving the damage of etching technics.In the present embodiment, the thickness range of said oxide layer 206 is 10～200 dusts.
Then, please refer to Fig. 9, in the epitaxial loayer 203 of said grid structure both sides, form light doping section 207.Said light doping section 207 injects through the light dope ion and forms.The light dope ion injects the known technology as those skilled in the art, does not do detailed explanation at this.
Then, please refer to Figure 10, form side wall 208 on epitaxial loayer 208 surfaces of said grid structure both sides.As an embodiment, said side wall 208 is the ONO structure that silica-silicon-nitride and silicon oxide constitutes.
Then, be mask with said grid structure and side wall 208, carry out source/leakage ion and inject, in the epitaxial loayer 203 of said grid structure both sides, form source region 209 and drain region 210.Said source region 209 lays respectively in the epitaxial loayer 203 of said pillar 201 and separator 202 both sides with drain region 210.Said source/leakage ion injects the known technology of the method in formation source region 209 and drain region 210 as those skilled in the art, does not do detailed explanation at this.
Through said method, the transistor arrangement of formation please refer to Figure 10.Said transistor comprises:
Source region 209 is positioned at the epitaxial loayer 203 of a side of said pillar 201 and separator 202;
Drain region 210 is positioned at the epitaxial loayer 203 of the opposite side of said pillar 201 and separator 202;
In the present embodiment, the material of said pillar 201 is a polysilicon.In other embodiment, said pillar 201 can also be silica, silicon nitride, carborundum, silicon oxynitride, germanium silicon etc.
Said separator 202 materials are the insulation material, and the material of for example said separator 202 is silica, silicon nitride, carborundum or silicon nitride.The thickness range of said separator is 3～30 nanometers.
As other embodiment, said pillar can also be the column structure of insulation material formation.
As one embodiment of the present of invention, the width range of said pillar 201 is 5 nanometers～1 micron.
The thickness of said epitaxial loayer 203 is higher than the height of said pillar 201, thereby can be used as the conducting channel between said source region 209 and the drain region 210 at the epitaxial loayer 203 of said pillar 201.As an embodiment, the thickness of said epitaxial loayer 203 is than big 10～100 nanometers of height of said pillar.
To sum up; Transistor provided by the invention and preparation method thereof forms separator between source region and drain region, said separator can prevent the dopant ion diffusion between source region and the drain region; Reduced transistorized short-channel effect; Prevent to form junction capacitance between source region and drain region and the Semiconductor substrate, reduced junction leakage, improved transistorized performance.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (13)
1. a transistorized manufacture method is characterized in that, comprising:
Semiconductor substrate is provided;
On said Semiconductor substrate, form pillar;
Sidewall at said pillar forms separator;
Form the epitaxial loayer that covers said Semiconductor substrate and pillar, the thickness of said epitaxial loayer is greater than the height of said pillar;
Form grid structure in epi-layer surface, said grid structure is positioned at said pillar top;
In the epitaxial loayer of said grid structure both sides, form source region and drain region, said source region and drain region are positioned at the both sides of said pillar and separator.
2. transistorized manufacture method as claimed in claim 1 is characterized in that, the material of said pillar is semiconductor material or insulation material.
3. transistorized manufacture method as claimed in claim 3 is characterized in that, the material of said pillar is a polysilicon, and the manufacture method of pillar comprises:
On said Semiconductor substrate, form polysilicon layer;
The said polysilicon layer of etching forms said pillar.
4. transistorized manufacture method as claimed in claim 1 is characterized in that, the material of said separator
Be silica, silicon nitride, carborundum or silicon nitride.
5. transistorized according to claim 1 manufacture method is characterized in that the thickness range of said separator is 3～30 nanometers.
6. transistorized manufacture method as claimed in claim 1 is characterized in that, the width range of said pillar is 5 nanometers～1 micron.
7. transistorized manufacture method as claimed in claim 1 is characterized in that, the thickness of said epitaxial loayer is than high 20～100 nanometers of height of said pillar.
8. a transistor is characterized in that, comprising:
Semiconductor substrate;
Epitaxial loayer is positioned on the said Semiconductor substrate;
Grid structure is positioned on the said epitaxial loayer;
Pillar is positioned at the epitaxial loayer of said grid structure below, and the height of said pillar is less than the thickness of said epitaxial loayer;
Separator is positioned at the sidewall of said pillar;
The source region is positioned at the epitaxial loayer of said pillar and separator one side;
The drain region is positioned at the epitaxial loayer of said pillar and separator opposite side.
9. transistor as claimed in claim 8 is characterized in that, the material of said pillar is semiconductor material, insulation material.
10. transistor as claimed in claim 8 is characterized in that, the material of said separator is silica, silicon nitride, carborundum or silicon nitride.
11., it is characterized in that the thickness range of said separator is 3～30 nanometers like the said transistor of claim 8.
12. transistor as claimed in claim 8 is characterized in that, the width range of said pillar is 5 nanometers～1 micron.
13. transistor as claimed in claim 8 is characterized in that, the thickness of said epitaxial loayer is than high 20～100 nanometers of height of said pillar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105600812A CN102479710A (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105600812A CN102479710A (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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| Publication Number | Publication Date |
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| CN102479710A true CN102479710A (en) | 2012-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010105600812A Pending CN102479710A (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083796A (en) * | 1998-02-04 | 2000-07-04 | Lg Semicon Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
-
2010
- 2010-11-24 CN CN2010105600812A patent/CN102479710A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083796A (en) * | 1998-02-04 | 2000-07-04 | Lg Semicon Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
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Application publication date: 20120530 |