CN102468435A - Manufacturing method of phase change memory - Google Patents
Manufacturing method of phase change memory Download PDFInfo
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- CN102468435A CN102468435A CN2010105501376A CN201010550137A CN102468435A CN 102468435 A CN102468435 A CN 102468435A CN 2010105501376 A CN2010105501376 A CN 2010105501376A CN 201010550137 A CN201010550137 A CN 201010550137A CN 102468435 A CN102468435 A CN 102468435A
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Abstract
The invention provides a manufacturing method of a phase change memory. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a bottom electrode is formed in the interlayer dielectric layer; forming a guide layer on the surface of the interlayer dielectric layer, and forming a guide layer opening corresponding to the bottom electrode in the guide layer; forming mask layers on the surface of the guide layer and in a part of the guide layer opening, wherein a gap with a width of 10-50 nanometers is reserved between the mask layers in the guide layer opening, and the lower interlayer dielectric layer is exposed from the gap; etching the interlayer dielectric layer along the gap by using the mask layers as masks so as to form a contact hole in the interlayer dielectric layer, wherein the lower bottom electrode is exposed by the contact hole; removing the mask layers and the guide layer; and forming a phase change layer on the surface of the interlayer dielectric layer and taking the phase change layer outside the contact hole as a top electrode. The contact area of the top electrode and the bottom electrode, which are formed in the manufacture method provided by the invention, is reduced so as to reduce the phase change current of the phase change memory.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of phase transition storage.
Background technology
(Phase Change Random Access Memory, PCRAM) technology is based on S.R.Ovshinsky and proposes in late 1960s that conception that phase-change thin film can be applied to the phase change memory medium sets up phase transition storage.As a kind of emerging nonvolatile storage technologies; Phase transition storage all has bigger superiority to flash memory in read or write speed, read-write number of times, data hold time, cellar area, many-valued realization etc. aspect many, has become the focus of present non-volatile memory technologies research.
In phase transition storage, can change the value of memory through the phase change layer that has write down data is heat-treated.The phase-change material that constitutes phase change layer can get into crystalline state or noncrystalline state owing to the heats of applying electric current.When phase change layer was in crystalline state, the resistance of PCRAM was lower, and this moment, the memory assignment was " 0 ".When phase change layer was in noncrystalline state, the resistance of PCRAM was higher, and this moment, the memory assignment was " 1 ".Therefore, PCRAM utilizes resistance difference when phase change layer is in crystalline state or noncrystalline state to write/nonvolatile memory of reading of data.
The manufacture method of existing phase transition storage please refer to Fig. 1～Fig. 6.At first,, Semiconductor substrate 100 is provided, is formed with transistor in the said Semiconductor substrate 100, be used to drive the phase change layer of follow-up formation with reference to figure 1.Be formed with interlayer dielectric layer on the said Semiconductor substrate 100, be formed with bottom electrode 102 in the said interlayer dielectric layer.Particularly, said interlayer dielectric layer is a sandwich construction, comprises respectively: first dielectric layer 101, and said first dielectric layer 101 flushes with said bottom electrode 102; Cover first silicon oxide layer 103 of said first dielectric layer 101 and bottom electrode 102; Cover first silicon nitride layer 104 of said first silicon oxide layer 103; Cover second silicon oxide layer 105 of said first silicon nitride layer 104.
Then, with reference to figure 2, on said second silicon oxide layer 105, form photoresist layer 108, be formed with opening in the said photoresist layer 108, the position of said opening is corresponding with the position of bottom electrode 102.
Then, still with reference to figure 2, along said second silicon oxide layer 105 of said opening etching, until exposing said first silicon nitride layer 104, in said second silicon oxide layer 105, form opening, said opening is positioned at said bottom electrode 102 tops.
Then, with reference to figure 3, remove said photoresist layer 108 (Fig. 2).Above said second silicon oxide layer 105, be formed into second silicon nitride layer 106.Said second silicon nitride layer 106 covers the sidewall and the bottom of the opening that is positioned at said second silicon oxide layer 105 at least.
Then, please refer to Fig. 4, carry out etching technics, remove other second silicon nitride layers 106 beyond the opening sidewalls in said second silicon oxide layer 105; With said second silicon nitride layer 106 that is positioned at the opening sidewalls of second silicon oxide layer 105 is mask; First silicon nitride layer 104 and first oxide layer 103 of etching below; In said first silicon nitride layer 104 and first oxide layer 103, form contact hole, said contact hole exposes the bottom electrode 102 of below.
At last; Please refer to Fig. 5, on said Semiconductor substrate 100, form phase change layer 107, said phase change layer 107 is filled full said contact hole; Be positioned at said contact hole phase change layer in addition as top electrodes, said top electrodes is electrically connected with bottom electrode 102 through the phase change layer in the contact hole.
, publication number can find more information in being the one Chinese patent application of CN101728492A about existing phase transition storage.
Find that in reality the power consumption of the phase transition storage that prior art is made is big.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of phase transition storage, and said method has improved the yield of phase transition storage, has improved the reliability of phase transition storage work.
For addressing the above problem, the invention provides a kind of manufacture method of phase transition storage, said method comprises:
Semiconductor substrate is provided, and said semiconductor substrate surface is formed with interlayer dielectric layer, is formed with bottom electrode in the said interlayer dielectric layer;
Form guide layer at said inter-level dielectric laminar surface, be formed with the guide layer opening in the said guide layer, the position of said guide layer opening is corresponding with the position of said bottom electrode;
In said guide layer surface and part guide layer opening, form mask layer, have the gap between the said mask layer in the said guide layer opening, the interlayer dielectric layer of below is exposed in said gap, and the width range in said gap is 10～50 nanometers;
With said mask layer is mask, along the said interlayer dielectric layer of said gap etching, in said interlayer dielectric layer, forms contact hole, and said contact hole exposes the bottom electrode of below;
Remove said mask layer and said guide layer;
Form phase change layer at said inter-level dielectric laminar surface, be positioned at said contact hole phase change layer in addition as top electrodes.
Alternatively, said mask layer is made by polystyrene and polymethyl methacrylate copolymerization.
Alternatively, the manufacture method of said mask layer comprises:
In said guide layer surface and guide layer opening, form the copolymerization layer; Said copolymerization layer is formed by polystyrene and polymethyl methacrylate copolymerization; The molecular size of said copolymerization layer equals the width of said guide layer opening; The polymethyl methacrylate bulk of molecule equals the width in the gap of follow-up formation in the said copolymerization layer molecule; The molecule of said copolymerization layer is formed with being arranged in a plurality of polystyrene molecule self assembly on every side of said polymethyl methacrylate molecule by a polymethyl methacrylate molecule, and the molecule of one of them copolymerization layer is positioned at said guide layer opening, and the molecule of all the other copolymerization layers is positioned at said guide layer surface;
Carry out etching technics, remove the polymethyl methacrylate molecule in the molecule of said copolymerization layer, in said copolymerization layer, form said gap, said copolymerization layer is as said mask layer.
Alternatively, the manufacture method of said copolymerization layer comprises:
The method of utilization spraying or spin coating forms the mixture of polystyrene and polymethyl methacrylate in said guide layer surface and guide layer opening.
Alternatively, the mass ratio of the polystyrene in the said mixture is 30～80%.
Alternatively, said etching technics is a plasma etch process.
Alternatively; The parameter of said plasma etch process is set to: temperature range is 240～310 degrees centigrade; Vacuum ranges is 1300～1700Mtorr; Etching gas is the mist of oxygen and nitrogen, and the volume ratio of said oxygen and nitrogen is 7/1～15/1, and power is 2300～2700W.
Alternatively, said interlayer dielectric layer comprises first dielectric layer and second dielectric layer that is positioned at first dielectric layer surface, and said bottom electrode is positioned at said first dielectric layer, and said bottom electrode flushes with said first dielectric layer.
Alternatively, the material of said guide layer is a metal.
Alternatively, the material of said guide layer is a chromium.
Alternatively, the thickness range of said guide layer is 200～1000 dusts.
Alternatively, said mask layer utilizes plasma etching to remove.
Alternatively, the parameter of said plasma etch process is: temperature range is 240～310 degrees centigrade, and vacuum ranges is 1300～1700Mtorr, and etching gas is oxygen and N
2H
2Mist, oxygen and N in the said mist
2H
2Volume ratio be 5/1～10/1, power is 1300～1700W.
Alternatively, the material of said phase change layer is a chalcogenide alloy.
Alternatively, the removal method of said guide layer is the method for wet etching.
Alternatively, the said wet etching utilization solution that contains sulfuric acid carries out.
Compared with prior art, the present invention has the following advantages:
The Semiconductor substrate that is formed with interlayer dielectric layer is provided, is formed with bottom electrode in the said interlayer dielectric layer, on said interlayer dielectric layer, form guide layer; Be formed with the guide layer opening corresponding in the said guide layer with the position of said bottom electrode; On said Semiconductor substrate, form mask layer then, be formed with the gap in the said mask layer, the width range in said gap is 10～50 nanometers; Thereby with said gap is mask; Carry out etching technics, the width of the contact hole that in said interlayer dielectric layer, forms is less, and the contact area of final phase change layer that forms and said bottom electrode is less; Thereby make said phase change layer under less phase change current, to undergo phase transition, reduced the required phase change current of phase change layer phase transformation;
Further optimally; Said mask layer is made by polystyrene and polymethyl methacrylate copolymerization, and said mask layer is formed on the said guide layer by the method for polystyrene and polymethyl methacrylate utilization spraying or spin coating, and said polystyrene molecule and polymethyl methacrylate molecule are with said guide layer opening mask; Independently adorn copolymerization; Form the copolymerization layer, the molecule of said copolymerization layer is made up of in a plurality of polystyrene molecules around the said polymethyl methacrylate molecule a polymethyl methacrylate molecule and copolymerization, and the molecule of one of them copolymerization layer is positioned at said guide layer opening; Remaining copolymerization layer is positioned at the said laminar surface that is guided out; Thereby through over etching, remove said polymethyl methacrylate and divide the period of the day from 11 p.m. to 1 a.m, the width in the gap that in said copolymerization layer, forms is even; Improve the uniformity of technology, improved the stability of technology.
Description of drawings
Fig. 1～Fig. 5 is the cross-sectional view that prior art is made phase transition storage;
Fig. 6 is the manufacture method schematic flow sheet of phase transition storage of the present invention;
Fig. 7～Figure 14 is the manufacture method cross-sectional view of the phase transition storage of one embodiment of the invention;
Figure 15 is the plan structure sketch map of copolymerization layer of the present invention without etching technics.
Embodiment
The power consumption of the phase transition storage that prior art is made is big.Discover that through the inventor reason that causes the problems referred to above is because the phase change current of phase transition storage is bigger than normal.And cause the bigger reason of said phase change current to be because the top electrodes and the contact area between the bottom electrode of phase transition storage are bigger.Because said top electrodes is connected through the phase-change material that is positioned at contact hole with bottom electrode, the aperture of said contact hole is bigger than normal, makes that the contact area between said top electrodes and the bottom electrode is bigger than normal.Need reduce the aperture of said contact hole, reducing the contact area between said top electrodes and the bottom electrode, thereby reduce the phase change current of institute's phase transition storage.
In conjunction with accompanying drawing 5; The inventor also finds; Along with the aperture of said contact hole reduces, the width of the openings that need correspondingly reduce to form in said second silicon oxide layer 105 and the thickness of second silicon nitride layer 106, and the thickness of the width of the openings that reduce to form in said second silicon oxide layer 105 and second silicon nitride layer 106 possibly influence the uniformity of the thickness of second silicon nitride layer, 106 depositions; Thereby have influence on said second silicon nitride layer 106 is the uniformity of the etching technics that carries out of mask; Make that the pore size of the final contact hole that forms is inhomogeneous, thereby the part aperture is bigger than normal, the phase change current of corresponding phase transition storage is bigger than normal.
In order to address the above problem, the inventor provides a kind of manufacture method of phase transition storage, please refer to the manufacture method schematic flow sheet of phase transition storage of the present invention shown in Figure 6.Said method comprises:
Step S1 provides Semiconductor substrate, and said semiconductor substrate surface is formed with interlayer dielectric layer, is formed with bottom electrode in the said interlayer dielectric layer;
Step S2 forms guide layer at said inter-level dielectric laminar surface, is formed with the guide layer opening in the said guide layer, and the position of said guide layer opening is corresponding with the position of said bottom electrode;
Step S3 forms mask layer in said guide layer surface and part guide layer opening, have the gap between the said mask layer in the said guide layer opening, and the interlayer dielectric layer of below is exposed in said gap, and the width range in said gap is 10～50 nanometers;
Step S4 is a mask with said mask layer, along the said interlayer dielectric layer of said gap etching, in said interlayer dielectric layer, forms contact hole, and said contact hole exposes the bottom electrode of below;
Step S5 removes said mask layer and said guide layer;
Step S6 forms phase change layer at said inter-level dielectric laminar surface, is positioned at said contact hole phase change layer in addition as top electrodes.
To combine concrete embodiment that technical scheme of the present invention is carried out detailed explanation below.
For better explanation technical scheme of the present invention, please combine the manufacture method cross-sectional view of phase transition storage of the one embodiment of the invention of accompanying drawing 7～shown in Figure 14.
At first, please refer to Fig. 7, Semiconductor substrate 200 is provided.Said Semiconductor substrate 200 surfaces are formed with interlayer dielectric layer, are formed with bottom electrode 202 in the said interlayer dielectric layer.
As one embodiment of the present of invention, said interlayer dielectric layer is a double-layer structure, and promptly said interlayer dielectric layer comprises first dielectric layer 201, second dielectric layer 203.Said bottom electrode 202 is positioned at said first dielectric layer 201, and flushes with said first dielectric layer 201; Said second dielectric layer 203 covers said first dielectric layer 201 and bottom electrode 202.
The material of said first dielectric layer 201 is the electric insulation material, for example can be preferably silica for silica, silicon nitride, carborundum, silicon oxynitride etc.
The material of said second dielectric layer 203 is the electric insulation material, for example can be silica, silicon nitride, silicon nitride or silicon oxynitride etc.The material of said second dielectric layer 202 can be identical or different with the material of first dielectric layer 201.As an embodiment, the material of said second dielectric layer 202 is identical with the material of said first dielectric layer 201, and promptly the material of said second dielectric layer 202 is a silica.The thickness range of said second dielectric layer 203 is 300～1700 dusts, is preferably 500～1500 dusts, for example can be 500 dusts, 1000 dusts or 1500 dusts etc.
Will be in the inherent follow-up processing step of said second dielectric layer 203 through etching technics formation contact hole, said contact hole is used to fill phase change layer.
In the present embodiment, the material of said Semiconductor substrate 200 is a silicon.In other embodiment, the material of said Semiconductor substrate 200 can also be germanium silicon, silicon-on-insulator etc.As an embodiment, also be formed with transistor in the said Semiconductor substrate 200, said transistor is electrically connected with the phase change layer of follow-up formation through said bottom electrode 202, and said transistor is used to drive said phase change layer.
Then; Please refer to 8, form guide layer 204, be formed with the guide layer opening in the said guide layer 204 at said inter-level dielectric laminar surface; Said guide layer opening exposes the interlayer dielectric layer of below, and the position of said guide layer opening is corresponding with the position of said bottom electrode 202.In the present embodiment, said guide layer opening is positioned at the top of said bottom electrode 202.
Said guide layer opening is used for the copolymerization layer that direct subsequent forms, and makes the molecule of said copolymerization layer be arranged in the said guide layer opening surperficial with guide layer along said guide layer opening.The width of said guide layer opening depends on that with the material of said copolymerization layer the width in the follow-up gap that will in the guide layer opening, form is relevant.In the present embodiment, the width range of said guide layer opening is 30～100 nanometers.
The material of said guide layer 204 is a metal.Said metal can be manganese, chromium, copper, gold, silver, aluminium etc.As preferred embodiment, the material of said guide layer 204 is a chromium.
In the present embodiment, said guide layer 204 is positioned on said second dielectric layer 203, and said guide layer opening exposes second dielectric layer 203 of below.
Then, please refer to Fig. 9, in said guide layer 204 surfaces and part guide layer opening, form the copolymerization layer, said copolymerization layer is made by polystyrene and polymethyl methacrylate copolymerization.Said copolymerization layer will be removed polymethyl methacrylate wherein through etching technics, thereby utilize said copolymerization layer to form mask layer.
Particularly, please refer to Fig. 9, carry out spin coating or spraying coating process, on said guide layer 204, form the copolymerization layer, said copolymerization layer is formed by polystyrene and polymethyl methacrylate copolymerization.For the ease of the structure of explanation copolymerization layer, the position at said polymethyl methacrylate molecule place is represented with 212, position 213 expressions at said polystyrene molecule place.
Molecule of polymethyl methacrylate described in the present invention and said polystyrene molecule have following characteristic; Be that both are under the guiding of guide layer 204; Can carry out self assembly; Form the molecule of copolymerization layer, the molecule of each copolymerization layer is formed by a polymethyl methacrylate molecule and a plurality of polystyrene molecule self assembly that is arranged in around the said polymethyl methacrylate molecule.The molecule of one of them copolymerization layer is positioned at said guide layer opening.The molecular size of said copolymerization layer equals the width of said guide layer opening, and the polymethyl methacrylate bulk of molecule equals the width in the follow-up gap that will in said guide layer opening, form in the said copolymerization layer molecule.
For the structure of said copolymerization layer is described better, please refer to the plan structure sketch map of copolymerization layer without over etching shown in Figure 15.Polymethyl methacrylate molecule in the said copolymerization layer (its position is represented with 212) a plurality of polystyrene molecules (its position is represented with 213) of arranging on every side.
The bulk of molecule of said copolymerization layer depends in spin coating or spraying coating process, the mass ratio of said polymethyl methacrylate.The mass ratio that is said polymethyl methacrylate is big more, and the final copolymerization layer molecule that forms is more little, and accordingly, the width in the gap 206 that in said mask layer 205, forms is also more little.As an embodiment, the mass ratio of polystyrene is 30～80% in said spin coating or the spraying coating process, and the mass ratio of said polymethyl methacrylate is 20～70%, and accordingly, the width range in the said gap 206 of formation is 10～50 nanometers.
Polymethyl methacrylate molecule in the said copolymerization layer will be removed through etching technics, thereby keep said polystyrene molecule, in said copolymerization layer, form the gap, and the width in said gap equals the width of said polymethyl methacrylate molecule.
Particularly, please refer to Figure 10, optionally remove the polymethyl methacrylate molecule in the molecule of said copolymerization layer, in said copolymerization layer, form said gap 206, said copolymerization layer forms said mask layer 205.
As an embodiment, the removal method of the polymethyl methacrylate molecule in the molecule of said copolymerization layer is an etching technics, and said etching technics utilizes the technology of plasma etching to carry out.
As preferred embodiment; Need the parameter of said plasma etch process preferably be provided with; To guarantee that polymethyl methacrylate in the molecule of the said copolymerization layer of etching divides interlayer dielectric layer 203, the guide layer 204 of the period of the day from 11 p.m. to 1 a.m below can not damaging; And said plasma etching industrial can not damage the polystyrene molecule in the molecule of said copolymerization layer, thereby can not destroy polystyrene molecule and the structure of mask layer 205 of the mask layer 205 of formation.
As preferred embodiment; The parameter of said plasma etch process is set to: temperature range is 240～310 degrees centigrade, for example is 240 degrees centigrade, 275 degrees centigrade or 310 degrees centigrade, and vacuum ranges is 1300～1700Mtorr; For example be 1300Mtorr, 1500Mtorr or 1700Mtorr; Etching gas is the mist of oxygen and nitrogen, and the volume ratio of said oxygen and nitrogen is 7/1～15/1, for example is 7/1,10/1 or 15/1; Power is 2300～2700W, for example is 2300W, 2500W, 2700W.Be provided with down in above-mentioned etching parameters; The plasma that forms is far longer than the corrasion to the polystyrene molecule in the molecule of interlayer dielectric layer 203, guide layer 204 and said copolymerization layer to the corrasion of the polymethyl methacrylate molecule in the molecule of said copolymerization layer; Effectively avoided the polystyrene molecular damage in the molecule of said interlayer dielectric layer 203, guide layer 204 and said copolymerization layer, thereby formed the mask layer 205 of according with process requirements.
Then, please refer to Figure 11, is mask with said mask layer 205, along said second dielectric layer 203 of said gap 206 etchings in the guide layer opening, in said second dielectric layer 203, forms contact hole 207, and said contact hole 207 exposes bottom electrode 202.Said contact hole 207 is used for filling phase change layer in subsequent process steps, and said phase change layer contacts with said bottom electrode 202.Because the aperture in said gap 206 is less; Thereby; The width of the contact hole 207 that said gap 206, corresponding edge forms is also less; Help in follow-up processing step, reducing the phase change layer of filling in this contact hole 207 and the contact area of bottom electrode 202, help reducing the required phase change current of phase change layer.
The method of said second dielectric layer 203 of etching is identical with prior art, as those skilled in the art's known technology, does not do detailed explanation at this.
Then, please refer to Figure 12, remove said mask layer 205 and guide layer 204.The removal method of said mask layer 205 is the method for plasma etching.For fear of in said plasma etch process, said interlayer dielectric layer 203, second dielectric layer 204 being caused damage, need be optimized setting to the parameter of said plasma etching.
As an embodiment, the parameter of said plasma etching is set to: temperature range is 240～310 degrees centigrade, and vacuum ranges is 1300～1700Mtorr, and etching gas is oxygen and N
2H
2Mist, oxygen and N in the said mist
2H
2Volume ratio be 5/1～10/1, power is 1300～1700W.
As an embodiment, the removal method of said guide layer 204 is the method for wet etching.Said wet etching adopts the solution that contains sulfuric acid to carry out, and wherein the ratio of sulfuric acid can be 0.1～90%, for example is 0.1%, 10%, 50%, 90%.
Then, please refer to Figure 13, on said Semiconductor substrate 200, form phase change layer 208, said phase change layer 208 is filled full said contact hole 207 at least.
The material of said phase change layer 208 is selected from chalcogenide alloy.Said chalcogenide alloy can be Ge-Sb-Te, Ag-In-Te or Ge-BiTe.
At last, please refer to Figure 14, etching is positioned at the partial phase change layer 208 of said second dielectric layer 203 tops, on said remaining phase change layer 208, forms the 3rd dielectric layer 209.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (16)
1. the manufacture method of a phase transition storage is characterized in that, comprising:
Semiconductor substrate is provided, and said semiconductor substrate surface is formed with interlayer dielectric layer, is formed with bottom electrode in the said interlayer dielectric layer;
Form guide layer at said inter-level dielectric laminar surface, be formed with the guide layer opening in the said guide layer, the position of said guide layer opening is corresponding with the position of said bottom electrode;
In said guide layer surface and part guide layer opening, form mask layer, have the gap between the said mask layer in the said guide layer opening, the interlayer dielectric layer of below is exposed in said gap, and the width range in said gap is 10～50 nanometers;
With said mask layer is mask, along the said interlayer dielectric layer of said gap etching, in said interlayer dielectric layer, forms contact hole, and said contact hole exposes the bottom electrode of below;
Remove said mask layer and said guide layer;
Form phase change layer at said inter-level dielectric laminar surface, be positioned at said contact hole phase change layer in addition as top electrodes.
2. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, said mask layer is made by polystyrene and polymethyl methacrylate copolymerization.
3. the manufacture method of phase transition storage as claimed in claim 2 is characterized in that, the manufacture method of said mask layer comprises:
In said guide layer surface and guide layer opening, form the copolymerization layer; Said copolymerization layer is formed by polystyrene and polymethyl methacrylate copolymerization; The molecular size of said copolymerization layer equals the width of said guide layer opening; The polymethyl methacrylate bulk of molecule equals the width in the gap of follow-up formation in the said copolymerization layer molecule; The molecule of said copolymerization layer is formed with being arranged in a plurality of polystyrene molecule self assembly on every side of said polymethyl methacrylate molecule by a polymethyl methacrylate molecule, and the molecule of one of them copolymerization layer is positioned at said guide layer opening, and the molecule of all the other copolymerization layers is positioned at said guide layer surface;
Carry out etching technics, remove the polymethyl methacrylate molecule in the molecule of said copolymerization layer, in said copolymerization layer, form the gap, said copolymerization layer is as said mask layer.
4. the manufacture method of phase transition storage as claimed in claim 3 is characterized in that, the manufacture method of said copolymerization layer comprises:
The method of utilization spraying or spin coating forms the mixture of polystyrene and polymethyl methacrylate in said guide layer surface and guide layer opening.
5. the manufacture method of phase transition storage as claimed in claim 4 is characterized in that, the mass ratio of the polystyrene in the said mixture is 30～80%.
6. the manufacture method of phase transition storage as claimed in claim 4 is characterized in that, said etching technics is a plasma etch process.
7. the manufacture method of phase transition storage as claimed in claim 6; It is characterized in that; The parameter of said plasma etch process is set to: temperature range is 240～310 degrees centigrade, and vacuum ranges is 1300～1700Mtorr, and etching gas is the mist of oxygen and nitrogen; The volume ratio of said oxygen and nitrogen is 7/1～15/1, and power is 2300～2700W.
8. the manufacture method of phase transition storage as claimed in claim 1; It is characterized in that; Said interlayer dielectric layer comprises first dielectric layer and second dielectric layer that is positioned at first dielectric layer surface, and said bottom electrode is positioned at said first dielectric layer, and said bottom electrode flushes with said first dielectric layer.
9. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the material of said guide layer is a metal.
10. the manufacture method of phase transition storage as claimed in claim 9 is characterized in that, the material of said guide layer is a chromium.
11. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the thickness range of said guide layer is 200～1000 dusts.
12. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, said mask layer utilizes plasma etching to remove.
13. the manufacture method of phase transition storage as claimed in claim 12 is characterized in that, the parameter of said plasma etch process is: temperature range is 240～310 degrees centigrade, and vacuum ranges is 1300～1700Mtorr, and etching gas is oxygen and N
2H
2Mist, oxygen and N in the said mist
2H
2Volume ratio be 5/1～10/1, power is 1300～1700W.
14. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the material of said phase change layer is a chalcogenide alloy.
15. the manufacture method of phase transition storage as claimed in claim 1 is characterized in that, the removal method of said guide layer is the method for wet etching.
16. the manufacture method of phase transition storage as claimed in claim 15 is characterized in that, the solution that said wet etching utilization contains sulfuric acid carries out.
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| CN107134526B (en) * | 2017-06-22 | 2019-10-25 | 南京工业大学 | A kind of non-volatile write-once with universality repeatedly reads memory and preparation method thereof |
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