CN102456405A - Dynamic reference source circuit applied to Flash EEPROM (electrically erasable programmable read-only memory) - Google Patents
Dynamic reference source circuit applied to Flash EEPROM (electrically erasable programmable read-only memory) Download PDFInfo
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- CN102456405A CN102456405A CN2010105288159A CN201010528815A CN102456405A CN 102456405 A CN102456405 A CN 102456405A CN 2010105288159 A CN2010105288159 A CN 2010105288159A CN 201010528815 A CN201010528815 A CN 201010528815A CN 102456405 A CN102456405 A CN 102456405A
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- flash eeprom
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Abstract
The invention provides a dynamic reference source circuit applied to a Flash EEPROM (electrically erasable programmable read-only memory). A perception window is not remarkably changed with data retention and programming/erasing times during the application process of a storage chip by utilizing a realization method of disposing a group of reference units in a storage array. The dynamic reference source circuit comprises a reference unit array and a reference unit decoding circuit. Reference units and common units are stored together in the storage array. The reference unit decoding circuit decodes according to the operation address provided by a chip operation unit to select a correct operation unit. The aforementioned dynamic reference source circuit applied to a Flash EEPROM can efficiently track the threshold shifts of storage units in the storage array, thereby improving the performance stability and reliability of the chip.
Description
Technical field
The present invention relates to a kind of Flash EEPROM storage chip circuit, relate in particular to the dynamic reference source circuit of a kind of FlashEEPROM.
Technical background
Development along with semiconductor fabrication process and IC design; People are comprising that processor, storer, mimic channel, interface logic even radio circuit all are integrated on the chip in the design; Be called system level chip (System-on-Chip is called for short " SoC ").Along with the data throughout in the chip design constantly rises and the system low-power consumption requirement, the system level chip design is increasing to the demand of storer.It is predicted that the storer that will be had difference in functionality to the silicon area in 2010 about 90% is occupied, in-line memory will become the deciding factor of domination total system.Flash EEPROM with its power down not obliterated data superperformance and become important component part indispensable in the in-line memory, it is improving system performance, is improving chip reliability, is reducing cost and aspect such as power consumption has all played positive effect.
Along with improving constantly of technological level; Flash EEPROM performance more and more becomes the key index of system level chip; Wherein data throughout constantly rises; The performance of reading to Flash EEPROM has proposed increasingly high requirement, and the performance of reading of Flash EEPROM is decided by the accuracy and the stability of reference source in the sensing circuit to a great extent.Compare with the static reference source that adopts in the common Flash eeprom circuit; The dynamic reference source can be followed the tracks of the threshold drift of storage array stored unit effectively; Guarantee in the chip use; Perceived window (sensing window) does not keep (dataretention) and program/erase number of times (P/E cycling) that marked change takes place with data, therefore designs a reliable and stable dynamic reference source circuit and has very positive meaning.
Summary of the invention
The object of the invention provides the dynamic reference source circuit of a kind of Flash of being applied to EEPROM; Through in storage array (memory array), one group of reference unit being set; Make in the storage chip application process; Perceived window (sensing window) does not keep (data retention) and program/erase number of times (P/E cycling) that marked change takes place with data, effectively improves the stability and the reliability of chip performance.
A kind of dynamic reference source circuit that is applied to Flash EEPROM comprises reference unit and reference unit decoding scheme.Reference unit and common unit coexist as in the storage array.Reference unit is uniformly distributed in the storage array, and each operating unit has unique reference unit corresponding with it on every word line.
The operation address that the reference unit decoding scheme provides according to chip, correct reference unit is chosen in decoding.Decoding scheme is selected in the word select of reference unit decoding scheme reusable storage array, is implemented in the selection operation unit and accomplishes the selection to reference unit simultaneously.For guaranteeing that reference unit has identical bit-line load with normal memory cell, the reference unit decoding scheme is set up the one-level redundant decoder.
During Flash EEPROM read operation; With the bit location (bitcell) and the reference unit (reference cell) that will read choose simultaneously; The conducting current delivery of two kinds of unit is arrived the input end of current comparison circuit through coupled bit line (bitline) and reference bit lines (refbitline); Through comparing the conducting electric current of bit location and reference unit, judge the data of bit location stored.
When Flash EEPROM carries out programming operation (Erase/write); With treat programming unit corresponding reference units synchronization and carry out refresh operation; Storage unit ambient temperature in reference unit and the storage array and stress distribution have the height consistance; And reference unit and array element synchronous refresh, then the reference unit threshold voltage shift that the tracking array unit is erasable owing to data or the data maintenance causes well.
Through in the above-mentioned Flash of the being employed in EEPROM storage array dynamic reference source design being set; Make its threshold drift that dynamic reference source can be followed the tracks of storage array stored unit effectively when read operation and programming operation; Guarantee in the chip use; Perceived window does not have greatly changed with data maintenance and program/erase, has improved stability, the reliability of chip performance effectively.
Description of drawings
Fig. 1 Flash EEPROM storage array and reference source circuit structural drawing
Fig. 2 Flash EEPROM reference source array decoding circuit structure figure
A kind of dynamic reference structures figure that is applied to Flash EEPROM of Fig. 3
Embodiment
According to accompanying drawing provided by the present invention summary of the invention is carried out detailed description below.Fig. 1 is the circuit structure of Flash EEPROM storage array and reference source, and its concrete work implementation process is:
WL is that signal enables, and according to the address decode results, the block selection signal BS of selected operating unit is changed to high level, and the electric current of storage unit can flow into sense amplifier through bit line.Identical block selection signal BS also can open the corresponding reference unit, and reference cell current also will be sent into sense amplifier via reference bit lines and compare.All by unique block selection signal control, this signal is controlled the unlatching of corresponding reference unit to each operating block simultaneously, therefore can guarantee that this reference unit remains with corresponding operating block synchronously.
Fig. 2 is a Flash EEPROM reference source storage array decoding scheme, and its concrete work implementation process is:
The array unit, block selection signal BS links to each other correct bit line (BL) with the column selection code translator with sensitive bit line (sabl), and wherein sensitive bit line (sabl) will be sent into the current input terminal of sense amplifier as storage unit.
For reference unit; Block selection signal chooses correct reference bit lines (refBL) to link to each other with sensitive reference bit lines (saref); Input as sense amplifier is relatively held, and is simultaneously approaching for the parasitic load that makes two input ends, increased the one-level redundant decoder.
Fig. 3 is the complete structural drawing of dynamic reference source circuit that is applied to Flash EEPROM, wherein mark part for the present invention complete practice example.
Claims (5)
1. a dynamic reference source circuit that is applied to Flash EEPROM is characterized in that: comprise reference unit and reference unit decoding scheme.
2. a kind of dynamic reference source circuit that is applied to Flash EEPROM as claimed in claim 1, it is characterized in that: said reference unit is uniformly distributed in the storage array.
3. according to claim 1 or claim 2 a kind of dynamic reference source circuit that is applied to Flash EEPROM, it is characterized in that: on every word line, said each reference unit is unique corresponding with each operating unit.
4. a kind of dynamic reference source circuit that is applied to Flash EEPROM as claimed in claim 1; It is characterized in that: decoding scheme is selected in the word select of said reference unit decoding scheme reusable storage array, is implemented in the selection operation unit and accomplishes the selection to reference unit simultaneously.
5. like claim 1 or 4 described a kind of dynamic reference source circuits that are applied to Flash EEPROM, it is characterized in that: said reference unit decoding scheme is set up the one-level redundant decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105288159A CN102456405A (en) | 2010-11-02 | 2010-11-02 | Dynamic reference source circuit applied to Flash EEPROM (electrically erasable programmable read-only memory) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105288159A CN102456405A (en) | 2010-11-02 | 2010-11-02 | Dynamic reference source circuit applied to Flash EEPROM (electrically erasable programmable read-only memory) |
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| CN102456405A true CN102456405A (en) | 2012-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010105288159A Pending CN102456405A (en) | 2010-11-02 | 2010-11-02 | Dynamic reference source circuit applied to Flash EEPROM (electrically erasable programmable read-only memory) |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903650A (en) * | 2014-03-17 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Memory array and control method thereof as well as flash memory |
| CN107885669A (en) * | 2017-11-09 | 2018-04-06 | 上海华力微电子有限公司 | A kind of distributed storage block access circuit |
| WO2022110636A1 (en) * | 2020-11-30 | 2022-06-02 | 无锡华润上华科技有限公司 | Semiconductor memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101681679A (en) * | 2007-05-02 | 2010-03-24 | 美光科技公司 | By non-volatile multilevel memory cell to the data read of reference unit |
| CN101777381A (en) * | 2009-01-13 | 2010-07-14 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and method for operating data in flash memory |
| CN101821812A (en) * | 2007-10-17 | 2010-09-01 | 美光科技公司 | Memory device program window is adjusted |
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2010
- 2010-11-02 CN CN2010105288159A patent/CN102456405A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101681679A (en) * | 2007-05-02 | 2010-03-24 | 美光科技公司 | By non-volatile multilevel memory cell to the data read of reference unit |
| CN101821812A (en) * | 2007-10-17 | 2010-09-01 | 美光科技公司 | Memory device program window is adjusted |
| CN101777381A (en) * | 2009-01-13 | 2010-07-14 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and method for operating data in flash memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903650A (en) * | 2014-03-17 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Memory array and control method thereof as well as flash memory |
| CN107885669A (en) * | 2017-11-09 | 2018-04-06 | 上海华力微电子有限公司 | A kind of distributed storage block access circuit |
| CN107885669B (en) * | 2017-11-09 | 2021-06-04 | 上海华力微电子有限公司 | Distributed storage block access circuit |
| WO2022110636A1 (en) * | 2020-11-30 | 2022-06-02 | 无锡华润上华科技有限公司 | Semiconductor memory |
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Application publication date: 20120516 |