CN102456392A - Memory device having a clock skew generator - Google Patents
Memory device having a clock skew generator Download PDFInfo
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- CN102456392A CN102456392A CN2011103116843A CN201110311684A CN102456392A CN 102456392 A CN102456392 A CN 102456392A CN 2011103116843 A CN2011103116843 A CN 2011103116843A CN 201110311684 A CN201110311684 A CN 201110311684A CN 102456392 A CN102456392 A CN 102456392A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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Abstract
A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.
Description
The cross reference of related application
The application requires to be called in the name that on October 15th, 2010 submitted to the U.S. Provisional Patent Application the 61/393rd of " MEMORY DEVICEHAVING A CLOCK SKEW GENERATOR "; No. 444 rights and interests, its full content are attached among this paper as a reference by reference.
Technical field
The present invention relates to a kind of storage component part with clock skew generator.
Background technology
In dual-port static random access memory (SRAM), can occur usually influencing minimum input voltage V
CCmin" reading-disturb-write " and " writing-disturb-write " phenomenon.For example, when carrying out write operation at a port (for example, " A-port "), and (for example, " when B-port ") carries out virtual read operation simultaneously, the situation of " reading-disturb-write " may appear at another port.Suppose to write/row that reads the address appointment is identical, but row are different, and the possibility of result is: (1) appointment-position is write by the A-port, reads by the B-port is virtual; (2) B-port BL precharge under the VDD level, thus the virtual voltage level that reads frequent interference A-port made, thus influence the write operation of A-port; And (3) reduce the V of " writing-position "
CCmin, this can confirm through test result.
Summary of the invention
To prior art; The invention provides a kind of storage component part; Comprise memory component, be contained in the housing, wherein; Said memory component is supported at least two of said storage component part basic operations simultaneously, and (coincident) operation of said basic while comprises a kind of in read operation and the write operation; And the clock skew generator, be contained in the said housing, be connected with said memory component; Wherein, At least two clock signals are applied in the said memory component, and, wherein; The clock channel with balance is stablized at least two of said clock skew generator generations, and said clock channel is relevant with said at least two clock signals that are used for said storage component part function timing.
According to storage component part of the present invention, further comprise: clock generator and clock skew steering logic element.
According to storage component part of the present invention, wherein, said clock skew steering logic element design is the different read/write state of the said storage component part of response, thereby changes the sequential of said at least two clock signals.
According to storage component part of the present invention, wherein, said combinational logic is configured at least one to said at least two clock signals, postpone respectively with virtual loading at least a.
According to storage component part of the present invention, wherein, said combinational logic produces signal that postpone or virtual loading, and said combined signal is used at least one said memory component of read operation and write operation with operation.
According to storage component part of the present invention, wherein, said combinational logic is created in first clock signal and the second clock signal of basically identical in the reading of said memory component-read mode.
According to storage component part of the present invention, wherein, in the writing of said memory component-read mode, said combinational logic produces the rising edge of said second clock signal between said first rising edge of clock signal and negative edge.
According to storage component part of the present invention, wherein, writing-writing in the pattern, said combinational logic produces the rising edge of said second clock signal after said first rising edge of clock signal and negative edge.
According to storage component part of the present invention, wherein, said memory component comprises and reads-write at least a in steering logic, address register, demoder and the memory array.
According to of the present invention a kind of in memory chip the method for clocking; Be included in the said memory chip memory component is provided; Wherein, Said memory component is supported the read operation and the write operation of said storage component part, and said operation can comprise that operation reads-a kind of in read mode, read-write operation mode and writing-write operation mode; The clock skew generator is provided in said memory chip; Producing relevant with at least two clock signals at least two stablizes and the clock channel of balance; On said passage, produce the signal controlling sequential of said read operation and write operation; Wherein, Said sequential changes according to different patterns, and wherein, said read operation and said write operation are carried out basically simultaneously; And said at least two clock signals are sent to said memory component.
According to method of the present invention, further comprise postponing and/or said at least two clock signals of virtual loading.
According to method of the present invention, further comprise: during the sequential of said read operation of control and write operation, will pass through the signal of delay and the signal of the virtual loading of process and send to said memory component.
According to method of the present invention, further be included in and read-produce in the read mode first clock signal and the second clock signal of basically identical.
According to method of the present invention, further be included in write-read mode in, between said first rising edge of clock signal and negative edge, produce the rising edge of said second clock signal.
According to method of the present invention, further be included in and write-write in the pattern, after said first rising edge of clock signal and negative edge, produce the rising edge of said second clock signal.
According to a kind of memory circuitry of the present invention, comprising: housing limits the encapsulation of said storage component part; Memory component is arranged in said housing, supports the read operation and the write operation of said memory device, and wherein, in the various combination of the different operation modes that defines storage component part, a plurality of operations can be carried out basically simultaneously; And clock skew generator; First clock signal and second clock signal are sent to said memory component; Wherein, Said clock skew generator produces said first clock signal and said second clock signal, said first clock signal and said second clock signal basically identical at least a pattern, and at least a other patterns, squint.
According to memory circuitry of the present invention, wherein, said clock skew generator comprises combinational logic, postpones or said first clock signal of virtual loading and said second clock signal.
According to memory circuitry of the present invention, wherein, said combinational logic will pass through signal delay or the virtual loading of process and send to said memory cell.
According to memory circuitry of the present invention, wherein, reading-read mode in; Said combinational logic produces the clock edge of basically identical, and, writing-read mode in; Between said first rising edge of clock signal and negative edge, produce the rising edge of said second clock signal.
According to memory circuitry of the present invention, wherein, reading-read mode in; Said combinational logic produces the clock edge of basically identical, and, writing-writing in the pattern; After said first rising edge of clock signal and negative edge, produce the rising edge of said second clock signal.
Description of drawings
Accompanying drawing shows the preferred embodiments of the present invention, and other information relevant with the present invention, wherein:
Fig. 1 shows the overall construction drawing of the embodiment of the storage component part with clock skew generator;
Fig. 2 shows the high-order structural drawing of the embodiment of storage component part with clock skew steering logic (such as shown in Fig. 1);
Fig. 3 shows the more detailed structural drawing of the embodiment of storage component part (such as shown in Fig. 2);
Fig. 4 shows the more detailed structural drawing of the embodiment of clock skew steering logic (such as shown in Fig. 3);
Fig. 5-Fig. 7 shows respectively and is reading-read mode, writes-read mode and write-write in the pattern, from the embodiment of the output waveform of clock skew steering logic (such as shown in Fig. 3); RR wherein shown in Figure 5 reads-read mode in; Use identical CLK; WR shown in Figure 6 writes-read mode in; The clki-rd rising edge is displaced to after the clki-wt rising edge, and WW shown in Figure 7 writes-writes in the pattern, and the clki2-wt rising edge is displaced to after the clki-wt rising edge.
Fig. 8 shows the clock skew control table by clock skew steering logic (such as shown in Fig. 3) generation; And
Fig. 9 illustrates the process flow diagram that is used for making and using the method for storage component part (shown in Fig. 1).
Embodiment
At first, through describing for exemplary storage component part with reference to accompanying drawing.Although described these storage component parts in detail, these are used for explanation, and can make various changes.After having described the example memory device, the instance of the process flow diagram of storage component part is provided, to explain the mode that in storage component part, produces with at least two relevant clock channels stable and balance of clock signal according to some preferred exemplary.
Fig. 1 shows the overall construction drawing of the embodiment of the storage component part 100 with clock skew generator 110.Storage component part 100 can be, but be not limited to the storage chip of dual-port static random access memory (SRAM) or any other types.Storage component part 100 comprises housing 125, memory component 105 and clock skew generator 110.Housing 125 can be defined as the encapsulation of storage component part 100.Memory component 105 is contained in the housing 125, supports at least two simultaneous basically operations of storage component part, and this simultaneous basically operation comprises a kind of in read operation and the write operation.Clock skew generator 110 is contained in the housing 125, and sends at least two clock signals to memory component 105.Clock skew generator 110 produces relevant with at least two clock signals stablizing and the clock channel of balance, is used to the function timing of storage component part.Clock skew generator 110 comprises the clock generator 115 and the clock skew steering logic 120 that is used for stable and balance clock channel of clocking.Clock skew steering logic 120 will further describe in Fig. 2-Fig. 8.
Fig. 2 shows the high-order structural drawing of the embodiment of storage component part 100 with clock skew steering logic element 120 (such as shown in Fig. 1).By clock generator 115 clocking A (CLK_A) and clock signal B (CLK_B); And this clock signal A (CLK_A) and clock signal B (CLK_B) are sent to clock skew steering logic 120, and clock skew steering logic 120 becomes clock signal Ai (CLKAi) and clock signal Bi (CLKBi) with CLK_A with the CLK_B data processing.
Usually, storage component part 100 is supported three kinds of operations: read, write and standby; These can read-write steering logic element 205,210 through utilization, impact damper 215,220, address register 225,230; Demoder 235,240,245,250; Memory access array 255, sense amplifier 260,265 and data output controller 270,275 are realized.A plurality of operations can basically side by side be carried out with different combinations, and different combinations has formed the different mode of the operation of storage component part 100.Except a set of address bits; Use clock signal A and B (CLK_A and CLK_B); Chip enable signal (CEB_A and CEB_B); Write signal (WEB_A and WEB_B) and output enable signal (OEB_A and OEB_B), array 255 can read or write digital data word in any position of its addressing space.Memory access can be synchronous, and can be triggered by rising edge of clock signal.INADD, input data, WE, output enable and chip enable can be latched by rising edge of clock signal.This clock signal usually or be used for the precharge of bit line or is used to start read operation or write operation, or be used for above-mentioned both.During last half clock period, bit-line pre-charge is high, in second clock period, can carry out read operation or write operation.
If WE signal (WEB), and chip enable signal (CEB_A and CEB_B) comes into force in rising edge of clock signal, then begins the write cycle in the storage component part 100.The memory cell or the space of input signal (DIN_A and DIN_B) write store array 255.Similarly, if chip enable signal and output enable signal (OEB_A and OEB_B) come into force, and the WE signal is low at the rising edge of clock signal place, and then read cycle begins.Will be to data-out bus (DOUT_A and DOUT_B) by the content driven of specified storage component part position, the address that is applied to memory array.Standby mode can reduce the power consumption during the nothing operation (for example, when CEB=1).
Fig. 3 shows the more detailed structural drawing of the embodiment of storage component part 100 (such as shown in Fig. 2), especially describes memory array 255 in detail.Similar parts use identical reference numerals, such as clock skew steering logic 120, read-write steering logic 205,210 and demoder 235,240,245,250.Yet, as shown in, address register A255 (Fig. 2) realizes with row address register A305, column address register A315, and address register B230 (Fig. 2) realizes with row address register B340 and column address register B310, and is as shown in Figure 3.Simultaneously, Fig. 3 also illustrates, and memory array 255 comprises the driver 330,335 that is connected with impact damper 320,325 respectively.
Row decoder 245,250 has, for example, and the selection of two (2) INADDs and a word line.Each unit 345 on this word line all is connected with specific bit line, and the data that are stored in the unit 345 can be visited and read to this specific bit line, perhaps in unit 345, writes new data.Driver 330,335 is usually located at the bottom of every bit lines.Column decoder 235,240 is usually located under the driver 330,335, and confirms that which bit lines is connected with chip output.
Read operation starts from usually, and row address is input in the row decoder 245,250.After the buffer address, row decoder 245,250 sends signal to a selected output line, thereby confirms to activate which bar word line.All unit 345 that are connected to word line optionally produce small voltage (approximately 100mV), this voltage are applied to unit 345 corresponding bit lines, to demonstrate 0 or 1 of storage.Driver 330,335 is poor with the complete logic level that bit-line voltage is amplified to corresponding 0 value or 1 value.With the data buffering on the selected word line, and output to output buffer 320,325 from unit 345.Here, data can be stored in the shift register (not shown).Data can be under the control of system clock (not shown), for example, under the control of the predetermined phase of system clock cycle, shifts out from memory chip.
Write operation also starts from producing column address, as the same in read operation.Afterwards, new data is input to the input buffer (not shown).Under the control of system clock, data can be passed through driver 330,335 and column decoder 235,240.Data are applied to unit 345, on the word line of selecting before this unit 345 is positioned at.Legacy data is replaced by new data, for example, according to the value of applied input data, is provided with or the resetting memory unit.
Fig. 4 shows the more detailed structural drawing of the embodiment of clock skew steering logic 120 (such as shown in Fig. 3).Clock skew steering logic 120 comprises combinational logic, and said combinational logic element comprises multiplexer 405,410,415,420, virtual loading device 425, and delay device 430.Clock signal clk A, CLKB are input in the multiplexer 405,410, and signal CLKA0, CLKB0 are handled and produced to this multiplexer 405,410 respectively.Usually, combinational logic 120 is designed to the different read/write states of response storage device, thereby changes the sequential of at least two clock signals, and/or in the reading of memory component-read mode, basic clocking simultaneously.Signal CLKA0 sends to virtual loading device 425, these virtual loading device 425 storage signal CLKA0, and this signal CLKA0 will be input in the multiplexer 415.
The process of confirming for the result of signal CLKAi, CLKBi will further describe in Fig. 5-Fig. 8.Fig. 5-Fig. 7 shows respectively and is reading-read mode, writes-read mode, and writes-write in the pattern, from the embodiment of the output waveform of clock skew steering logic 120 (such as shown in Fig. 3).In Fig. 5, reading-read mode in, combinational logic 120 clocking clkiA and clock signal clkiB, this clock signal clkiA consistent basically with clock signal clkiB (for example, phase place is identical, and waveform is identical).
In Fig. 6, writing-read mode in, combinational logic 120 produces rising edge or the level that writes clock signal clki_wt between rising edge that reads clock signal clki_rd and negative edge.Especially, if clock signal clk A, CLKB (Fig. 4) correspond respectively to write operation and read operation, then combinational logic 120 produces between rising edge that reads clock signal clkB_rd and negative edge and writes the rising edge among the clock signal clkiA_wt.If clock signal clk A, CLKB (Fig. 4) correspond respectively to read operation and write operation, then combinational logic 120 produces between rising edge that reads clock signal clkA_rd and negative edge and writes the rising edge among the clock signal clkiB_wt.Should understand, in description, rise on " edge " or descend " edge " is actually the inclined-plane (ramp) with finite d v/dt.Between high level and low level, perhaps between current level and the level in response to the switch of activation level or latch, the level change process that is taken place is one period short period,
In Fig. 7, writing-writing in the pattern, after second write the rising edge and negative edge of clock signal clk2_wt, combinational logic 120 write among the clock signal clk1_wt first and produces rising edge.Especially, after rising edge that writes clock signal clkiB_st and negative edge, combinational logic 120 can produce rising edge in writing clock signal clkiA_st.After rising edge that writes clock signal clkA_wt and negative edge, combinational logic 120 can produce the rising edge that writes clock signal clkiB_wt equally.
Fig. 8 shows the clock skew control table by clock skew steering logic 120 (such as shown in Fig. 3) generation.In mode standard, signal TM_RWM, TM_ALD, TM_BLD are 0, and write signal WEBA, WEBB can be 1 or 0, and the result is not skew in standard read operation and write operation.Reading-read mode in; Signal TM_RWM is 1; Signal TM_ALD, TM_BLD are 0, and write signal WEBA, WEBB are 1, and the result is; " dual reading " operation through not being superior to " single reading " operation has produced essentially identical signal (for example, signal " CLKAi " is identical with waveform with the phase place of signal " CLKBi ").
Writing-read mode in; Clock signal clk A, CLKB (Fig. 4) correspond respectively to and write and read; Signal TM_RWM, TM_BLD are 1, and signal TM_ALD is 0, and write signal WEBA, WEBB are respectively 0 and 1; The result is to have produced clock signal clk B skew through " reading-disturb-write " operation that is not superior to " single writing " operation.Because in identical bit location SRAM, a port reads, and another port writes, so the possibility of result is the situation of " reading-disturb-write ".If clock signal clk A, CLKB (Fig. 4) correspond respectively to and read and write; Signal TM_RWM, TM_ALD are 1; Signal TM_BLD is 0; Write signal WEBA, WEBB are respectively 1 and 0, and then the result is, have produced clock signal clk A skew through " reading-disturb-write " operation that is not superior to " single writing " operation.
Writing-writing in the pattern, signal TM_RWM, TM_BLD are 1, signal TM_ALD be 0 and write signal WEBA, WEBB be 0, the result is to have produced clock signal clk B skew through " writing-write " the clock collision time that detects.This means that when two clock difference of injection time during greater than " clock collision time " Tcc, the second write operation data can write data by first and replace.If two clock difference of injection time are less than Tcc, then the second write operation data can not write data by first and replace, thereby have produced unknown data.If signal TM_RWM, TM_ALD are 1, signal TM_BLD is 0, and write signal WEBA, WEBB are 0, and then the result is, has produced clock signal clk A skew through " writing-write " the clock collision time that detects (choosing).
Fig. 9 illustrates the process flow diagram that is used for making and using the method for storage component part 100 (shown in Fig. 1).Start from square frame 905,910, housing 125 is provided, memory component 105 is loaded in encapsulation or the housing 125.In square frame 915 and 920, clock skew generator 110 is contained in the housing 125, and produces relevant with at least two clock signals at least two and stablize and the clock channel of balance.Clock signal can postpone and/or virtual loading.In square frame 925, clock skew generator 110 sends to clock signal in the memory component 105.
As stated, improved storage component part 100 utilizes clock skew generator 110 to produce, and this clock skew generator 110 is embedded in the housing 125 of storage component part 100.Clock skew generator 110 produces relevant with at least two clock signals at least two and stablizes and the clock channel of balance.In order to achieve the above object, clock skew generator 110 can postpone or virtual loading clock signal, as said, helps like this avoiding a conflict.Reading-read mode in; Clock skew generator 110 can produce first clock signal and second clock signal; First clock signal and second clock signal are basic identical; Writing-read mode in, clock skew generator 110 can produce the rising edge of second clock signal between first rising edge of clock signal and negative edge, and; Writing-writing in the pattern, clock skew generator 110 can produce the rising edge of second clock signal after first rising edge of clock signal and negative edge.
Although be described for the present invention, be not limited to this according to exemplary embodiment.On the contrary; Should carry out the understanding of broad sense for additional claim; Thereby comprise other variation patterns of the present invention and embodiment that those of ordinary skills may make, these variation patterns and embodiment can't exceed equivalent scope of the present invention and boundary.
Claims (10)
1. storage component part comprises:
Memory component is contained in the housing, and wherein, said memory component is supported at least two of said storage component part basic operations simultaneously, and the operation of said basic while comprises a kind of in read operation and the write operation; And
The clock skew generator is contained in the said housing, is connected with said memory component; Wherein, At least two clock signals are applied in the said memory component, and, wherein; The clock channel with balance is stablized at least two of said clock skew generator generations, and said clock channel is used for the clock signal of said storage component part operation carrying out timing relevant with said at least two.
2. storage component part according to claim 1 further comprises: clock generator and clock skew steering logic element.
3. storage component part according to claim 2, wherein, said clock skew steering logic element design is the different read/write state in response to said storage component part, thereby changes the sequential of said at least two clock signals.
4. storage component part according to claim 3, wherein, said combinational logic circuit is configured at least one to said at least two clock signals, postpone respectively with virtual loading at least a.
5. storage component part according to claim 4; Wherein, Said combinational logic circuit produces signal that postpone or virtual loading, and signal said delay or virtual loading is used at least one said memory component of read operation and write operation in order to operation.
6. storage component part according to claim 3, wherein, said combinational logic circuit is created in first clock signal and the second clock signal of basically identical in the reading of said memory component-read mode.
7. storage component part according to claim 6, wherein, in the writing of said memory component-read mode, said combinational logic circuit produces the rising edge of said second clock signal between said first rising edge of clock signal and negative edge.
8. storage component part according to claim 6 wherein, is writing-is writing in the pattern, and said combinational logic circuit produces the rising edge of said second clock signal after said first rising edge of clock signal and negative edge.
9. the method for a clocking in memory chip:
In said memory chip, memory component is provided; Wherein, Said memory component is supported the read operation and the write operation of said storage component part, and said operation can comprise that operation reads-a kind of in read mode, read-write operation mode and writing-write operation mode;
The clock skew generator is provided in said memory chip;
Producing relevant with at least two clock signals at least two stablizes and the clock channel of balance; On said passage, produce the signal controlling sequential of said read operation and write operation; Wherein, Said sequential changes according to different patterns, and wherein, said read operation and said write operation are carried out basically simultaneously; And
Said at least two clock signals are sent to said memory component.
10. memory circuitry comprises:
Housing limits the packaging part of said storage component part;
Memory component is arranged in said housing, supports the read operation and the write operation of said memory device, and wherein, in the various combination of the different operation modes that defines storage component part, a plurality of operations can be carried out basically simultaneously; And
The clock skew generator; First clock signal and second clock signal are sent to said memory component; Wherein, Said clock skew generator produces said first clock signal and said second clock signal, said first clock signal and said second clock signal basically identical at least a pattern, and at least a other patterns, squint.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39344410P | 2010-10-15 | 2010-10-15 | |
| US61/393,444 | 2010-10-15 | ||
| US12/968,582 | 2010-12-15 | ||
| US12/968,582 US8395950B2 (en) | 2010-10-15 | 2010-12-15 | Memory device having a clock skew generator |
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| CN102456392A true CN102456392A (en) | 2012-05-16 |
| CN102456392B CN102456392B (en) | 2014-09-10 |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102456392B (en) | 2014-09-10 |
| US8395950B2 (en) | 2013-03-12 |
| US20120092944A1 (en) | 2012-04-19 |
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