CN102446901B - Failure analysis structure, formation method of failure analysis structure and failure analysis method - Google Patents
Failure analysis structure, formation method of failure analysis structure and failure analysis method Download PDFInfo
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- CN102446901B CN102446901B CN 201010509365 CN201010509365A CN102446901B CN 102446901 B CN102446901 B CN 102446901B CN 201010509365 CN201010509365 CN 201010509365 CN 201010509365 A CN201010509365 A CN 201010509365A CN 102446901 B CN102446901 B CN 102446901B
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Abstract
The invention provides a formation method of a failure analysis structure, which comprises the following steps that: a substrate is provided, and a first metal layer is formed on the substrate; a first conductive plug and a second metal layer are sequentially formed on the first metal layer, and the second metal layer is sequentially connected with the first metal layer through the first conductive plug to form a serial-connection structure; a second insulation layer and a second conductive plug are formed on the second metal layer, and the second conductive plug is connected with the second metal layer; and a test metal layer is formed on the insulation layer, and the test metal layer is connected with the second metal layer through the second conductive plug. The invention also provides a failure analysis structure and a failure analysis method thereof. Due to the adoption of the failure analysis structure and the failure analysis method, only the test metal layer is required to expose, so the second metal layer is free from being damaged, and the accuracy of the failure analysis result can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of failure analysis structure, its formation method and failure analysis method thereof.
Background technology
Along with semiconductor fabrication is advanced to deep sub-micron technique, the number of plies of semiconductor metal line is more and more, the conductive plunger quantity that connects the different layers metal line also increases thereupon, thereby the size reduction of conductive plunger, the difficulty of etching that causes forming the through hole of conductive plunger increases, defective occurs and the etching of through hole is not in place, opening circuit of interconnection structure between metal line just may occur, cause the inefficacy of semiconductor device.
for this reason, the failure analysis of conductive plunger becomes present study hotspot, existing failure analysis method mainly adopts the electron beam aberration to distinguish method, be that voltage contrast is as technology (Voltage Contrast, VC) whether the testing conductive connector is connected with two metal layers effectively, the wherein layer of metal layer surface that connects at conductive plunger by electron beam scanned, if conductive plunger has open defect, be presented as that the layer on surface of metal that is scanned exists conduction property poor, as the metal level potential difference, it is poor that described potential difference will be converted into electron beam brightness, detect the poor and brightness separation of above-mentioned electron beam brightness and can judge whether conductive plunger has the position of open defect and open defect.The patent No. is the United States Patent (USP) of US5970167, has elaborated how to use above-mentioned voltage contrast and carry out the failure analysis of conductive plunger as technology.
Concrete testing process is: semiconductor product and the failure analysis structure thereof of analysis to be tested are provided, comprise: substrate; Be positioned at successively the first metal layer and second metal level of described substrate surface, described the first metal layer be connected metal level and connect by conductive plunger.Wherein, described the first metal layer and the second metal level are made of a plurality of metal derbies respectively, and by conductive plunger, described the first metal layer metal derby are connected successively with the second metal level metal derby, consist of cascaded structure.
Conductive plunger in described failure analysis structure and the conductive plunger in semiconductor product are to form simultaneously by same semiconductor technology, and the quantity of described conductive plunger is identical with quantity and the layout of the conductive plunger of described semiconductor product with layout.
Failure analysis process particularly comprises: at first described failure analysis structure is carried out delamination to exposing the second metal level; With an end ground connection of described the second metal level or be connected to other fixed voltages, make the first metal layer of whole cascaded structure and the second metal level all remain on equipotential.
Then, produce electron beam by ESEM, described electron beam is incident to described the second metal level, described the second metal level generation secondary electron under the exciting of described electron beam.
Then, the secondary electron that utilizes described the second metal level of signal collection systematic collection to produce after electron excitation according to the secondary electron of collecting, utilizes image demonstration and register system to show and record the secondary electron image of described the superiors metal.
At last, described secondary electron image is analyzed, if the described secondary electron of collecting exists luminance difference, illustrate that in described failure analysis structure, conductive plunger has open defect, cause the failure analysis structure of whole series connection to disconnect, cause potential difference, form the secondary electron image with luminance difference.Accordingly, in described semiconductor product, the conductive plunger of correspondence position has identical open defect.
When but the failure analysis structure by technique scheme is carried out failure analysis to the conductive plunger of semiconductor product, the inaccurate problem of analysis result usually appears.
Summary of the invention
The problem that the present invention solves is to provide a kind of failure analysis structure, its formation method and failure analysis method thereof, improves the accuracy of failure analysis.
For addressing the above problem, the invention provides a kind of formation method of failure analysis structure, described failure analysis structure is used for the conductive plunger of semiconductor product is carried out failure analysis, and described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprising:
Substrate is provided, and forms the first metal layer in described substrate, described the first metal layer is made of discrete metal derby;
Form successively the first insulating barrier and the second metal level on the metal derby of described the first metal layer, has the first conductive plunger that runs through its thickness in described the first insulating barrier, described the second metal level is made of discrete metal derby, and described the second metal level metal derby is connected successively by the first conductive plunger and the first metal layer metal derby and consists of cascaded structure;
Form the second insulating barrier and be positioned at the second conductive plunger of described the second insulating barrier on described the second metal level, described the second conductive plunger is connected with the second metal level metal derby;
Form the test metal level on described the second insulating barrier, described test metal level is made of discrete metal derby, and described test metal level metal derby is corresponding connected one by one with the second metal level metal derby by the second conductive plunger.
Optionally, in described the first metal layer and semiconductor product, the layer of metal layer forms simultaneously by same processing step.
Optionally, the quantitative relation of described the second metal level and the first metal layer is one of following: the quantity of described the first metal layer metal derby is lacked one than the second metal level metal derby quantity; The quantity of described the second metal level metal derby is lacked one than the first metal layer metal derby quantity; The quantity of described the second metal level metal derby equals the first metal layer metal derby quantity.
Optionally, the size of described the second conductive plunger is not less than the size of described the first conductive plunger.
Optionally, the area of described test metal level metal derby is not more than described the second metal level metal derby area.
Optionally, also be included on described test metal level and be formed with dielectric layer.
The present invention also provides a kind of failure analysis structure, is used for the conductive plunger of semiconductor product is carried out failure analysis, and described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprising:
Substrate;
Be positioned at successively the first metal layer and second metal level of described substrate surface, described the first metal layer and the second metal level are made of a plurality of discrete metal derbies respectively, connect successively the first metal layer metal derby by the first conductive plunger and become cascaded structure with the second metal level metal block shaped, quantity and the layout of the conductive plunger in the first conductive plunger in described failure analysis structure and semiconductor product are identical;
Be formed with the test metal level on described the second metal level, described test metal level is made of a plurality of metal derbies, and the metal derby of the metal derby of described test metal level by the second conductive plunger and described the second metal level is corresponding to be connected one by one.
Optionally, described the first metal layer and the second metal interlevel are formed with the first insulating barrier, the first conductive plunger is positioned between described the first insulating barrier, be used for being electrically connected to the first metal layer and the second metal level, described the second metal level and described test metal interlevel are formed with the second insulating barrier, the second conductive plunger is positioned between described the second insulating barrier, is used for being electrically connected to the second metal level and test metal level.
Optionally, described the first metal layer metal derby is identical with quantity and the layout of layer of metal layer metal derby in semiconductor product.
Optionally, described the first metal layer metal derby is identical with quantity and the layout of layer of metal layer metal derby in semiconductor product.
Optionally, the quantitative relation of described the second metal level and the first metal layer is one of following: the quantity of described the first metal layer metal derby is lacked one than the second metal level metal derby quantity; The quantity of described the second metal level metal derby is lacked one than the first metal layer metal derby quantity; The quantity of described the second metal level metal derby equals the first metal layer metal derby quantity.
Optionally, the size of described the second conductive plunger is not less than the size of described the first conductive plunger.
Optionally, the area of described test metal level metal derby is not more than described the second metal level metal derby area.
Optionally, also be formed with dielectric layer on described test metal level.
The present invention also provides a kind of failure analysis method of described failure analysis structure, is used for the conductive plunger of semiconductor product is carried out failure analysis, and described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprising:
Semiconductor product and corresponding failure analysis structure thereof are provided, and the first conductive plunger in described failure analysis structure has identical quantity and layout with the conductive plunger in semiconductor product;
Described failure analysis structure is carried out delamination to exposing the test metal level;
One end of described test metal level is connected to fixed voltage;
Electron beam is incident to described test metal level, and described test metal level produces secondary electron under the bombardment of described incident beam;
Collect the secondary electron that described test metal level produces, record and show described secondary electron image;
Described secondary electron image is analyzed: if having luminance difference in described secondary electron image,
First conductive plunger at its brightness separation place has open defect, and accordingly, on described semiconductor product, the conductive plunger of correspondence position has open defect.
Optionally, described fixed voltage is earth terminal.
Optionally, described electron beam forms by electron gun, and the voltage that described electron gun applies is 3～10KV, and the electric current that makes electron beam is 10～20 μ A.
Optionally, if the secondary electron image of described test metal level does not have luminance difference, the first conductive plunger in described failure analysis structure does not have open defect, and there is not open defect in the conductive plunger of described semiconductor product.
Optionally, if having luminance difference in described secondary electron image, and take described brightness separation as the boundary, near the brightness of the test metal level of fixed voltage one end higher than the brightness away from the test metal level of fixed voltage one end.
Compared with prior art, have following advantage: failure analysis structure of the present invention and failure analysis method thereof only need to expose the test metal level, do not need to carry out delamination to the second metal level, can not damage described the second metal level, improve precision of analysis; Simultaneously, can not cause damage to the second insulating barrier and the first insulating barrier, further improve precision of analysis.
Further, the size of described the second conductive plunger is not less than the size of described the first conductive plunger, reduces the technology difficulty of the second conductive plunger, the inaccurate problem of analysis result of avoiding the loose contact because of the second conductive plunger to cause.
At last, described test metal level metal derby area is not more than described the second metal level metal derby area, reduces the test metal level area that need expose because of delamination excessive, and the delamination that causes is inhomogeneous.
Description of drawings
Fig. 1 is the formation method flow schematic diagram of failure analysis structure of the present invention.
Fig. 2 to Fig. 8 is the formation method structural representation of the failure analysis structure of one embodiment of the invention.
Fig. 9 to Figure 14 is the failure analysis structural representation of one embodiment of the invention.
Figure 15 is failure analysis method schematic flow sheet of the present invention.
Figure 16 to Figure 17 is the failure analysis method schematic diagram of one embodiment of the invention.
Embodiment
When the failure analysis structure of use prior art scheme was carried out failure analysis, the inaccurate problem of analysis result usually appearred.The inventor finds, because prior art must be carried out delamination with the failure analysis structure, until expose failure analysis structure metal level to be scanned, because metal level area in the failure analysis structure is larger, if during delamination, mill is inhomogeneous, can destroy described metal level, make analysis result have inaccuracy; Simultaneously, the megohmite insulant material that is positioned at the interconnecting metal interlayer is softer, and delamination technique can cause the failure analysis structure and morphology to deform, and is unfavorable for analysis result.
For addressing the above problem, the invention provides a kind of formation method of failure analysis structure, described failure analysis structure is used for the conductive plunger of semiconductor product is carried out failure analysis, described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprises as shown in Figure 1:
Execution in step S101 provides substrate, and forms the first metal layer in described substrate, and described the first metal layer is made of discrete metal derby.
Execution in step S102, form successively the first insulating barrier and the second metal level on the metal derby of described the first metal layer, has the first conductive plunger that runs through its thickness in described the first insulating barrier, described the second metal level is made of discrete metal derby, and described the second metal level metal derby is connected successively by the first conductive plunger and the first metal layer metal derby and consists of cascaded structure.
Execution in step S103 forms the second insulating barrier and is positioned at the second conductive plunger of described the second insulating barrier on described the second metal level, described the second conductive plunger is connected with the second metal level metal derby.
Execution in step S104 forms the test metal level on described the second insulating barrier, described test metal level is made of discrete metal derby, and described test metal level metal derby is corresponding connected one by one with the second metal level metal derby by the second conductive plunger.
For the essence that those skilled in the art be can better understand the present invention, make the present invention clearer, describe the formation method of failure analysis structure of the semiconductor device of the specific embodiment of the invention in detail below in conjunction with accompanying drawing.
The failure analysis structure that provides in the present invention is whether effectively to connect two metal layers corresponding with it in semiconductor product for the conductive plunger of analyzing above-mentioned semiconductor product.As an embodiment, one deck conductive plunger in the selected semiconductor product, and the two metal layers of connection corresponding to it are respectively upper metal layers and lower metal layer.Below conductive plunger in mentioned semiconductor product be selected this layer conductive plunger.
Continuation forms the first metal layer 002 with reference to figure 2 in described substrate 001, described the first metal layer 002 is made of the metal derby of a plurality of discrete mutual insulatings.
In the present embodiment, described the first metal layer 002 forms by same processing step simultaneously with lower metal layer in semiconductor product, and the metal derby of described the first metal layer 002 can be identical with quantity and the layout of the metal derby of described lower metal layer.As other embodiment, described the first metal layer 002 also can adopt and independently form technique, and is different from quantity and the layout of described lower metal layer metal derby.
The concrete technology of described the first metal layer 002 can for: at first form insulating barrier in described substrate 001, and described insulating barrier carried out patterned process, form through hole in described insulating barrier; To described filling through hole metallics, form the discrete metal derby of some numbers at last, form the first metal layer 002.
As shown in Figure 3, form the first insulating barrier 003 on described the first metal layer 002, described the first insulating barrier 003 can be silica or other dielectric material; Described the first insulating barrier 003 is carried out patterned process, form the first through hole that exposes the first metal layer 002 part surface, in the quantity of described the first through hole and layout and semiconductor product, the quantity of conductive plunger and layout are identical; To described the first filling through hole metal, form the first conductive plunger 004 that is electrically connected to the first metal layer 002 at last; Described the first conductive plunger 004 has identical quantity and layout with conductive plunger in semiconductor product, have in even described semiconductor product and fail the conductive plunger that effectively connects, in described failure analysis structure, the first conductive plunger 004 of correspondence position fails effectively to connect equally.
As shown in Figure 4, form the second metal level 005 on described the first insulating barrier 003, described the second metal level 005 is made of the metal derby of a plurality of discrete mutual insulatings.In the present embodiment, each metal derby in described the second metal level 005 connects the metal derby of two adjacent the first metal layers 002 by the first conductive plunger 004, by described the first conductive plunger 004 formation cascaded structure that successively the first metal layer 002 metal derby and the second metal level 005 metal derby joined end to end, and described the first conductive plunger 004 only is used for being electrically connected to the first metal layer 002 metal derby and second metal level 005 metal derby.
The concrete technology of described the second metal level 005 can for: at first form insulating barrier being formed with on the first insulating barrier 003 of the first conductive plunger 004, and described insulating barrier is carried out patterned process, form through hole in described insulating barrier, at last to described filling through hole metallics, form the discrete metal derby of some numbers, namely form the second metal level 005.
Wherein, described quantitative relation by the first metal layer 002 and the second metal level 005 can be following three kinds of situations.
As shown in Figure 4, the quantity of described the first metal layer 002 metal derby is lacked one than the second metal level 005 metal derby quantity, and namely the metal derby at the second metal level 005 two ends only is connected with the metal derby of a first metal layer 002.
Described cascaded structure can also be as shown in Figure 5, and the quantity of described the second metal level 005 metal derby is lacked one than the first metal layer 002 metal derby quantity, and namely the metal derby at the first metal layer 002 two ends only is connected with the metal derby of second metal level 005.
Perhaps can also be as shown in Figure 6, the quantity of described the second metal level 005 metal derby equals the first metal layer 002 metal derby quantity.
As shown in Figure 7, form the second insulating barrier 006 on described the second metal level 005, described the second insulating barrier 006 can be silica or other dielectric material; Described the second insulating barrier 006 is carried out patterned process, form the second through hole that exposes the second metal level 005 metal derby part surface, described the second through hole is corresponding connected with the metal derby of each the second metal level 005; To described the second filling through hole metal, form the second conductive plunger 007 that is electrically connected to the metal derby of the second metal level 002 at last.
As shown in Figure 8, form test metal level 008 on described the second insulating barrier 006, test metal level 008 is made of the metal derby of a plurality of discrete mutual insulatings, and described test metal level 008 metal derby is by the second conductive plunger 007 and the corresponding electrical connection one by one of described the second metal level 005 metal derby.After being formed with described test metal level 008, also comprise also forming dielectric layer thereon, be not described in detail herein.
For the second conductive plunger 007 that makes follow-up formation does not impact described failure analysis construction analysis result with the formation technique of testing metal level 008, the size of described the second conductive plunger 007 is not less than the size of described the first conductive plunger 004, to avoid causing technology difficulty to increase because described the second conductive plunger size is little, easily cause the Joint failure of the second conductive plunger 007.
Simultaneously, described test metal level 008 metal derby area is not more than described the second metal level 005 metal derby area, avoids test metal level 008 area that need expose because of delamination excessive, the problem that the delamination that causes is inhomogeneous.
The failure analysis structure that the present invention also provides a kind of formation method of described failure analysis structure to form, be used for the conductive plunger of semiconductor product is carried out failure analysis, described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprising:
Substrate;
Be positioned at successively the first metal layer and second metal level of described substrate surface, described the first metal layer and the second metal level are made of a plurality of discrete metal derbies respectively, connect successively the first metal layer metal derby by the first conductive plunger and become cascaded structure with the second metal level metal block shaped, quantity and the layout of the conductive plunger in the first conductive plunger in described failure analysis structure and semiconductor product are identical;
Be formed with the test metal level on described the second metal level, described test metal level is made of a plurality of metal derbies, and the metal derby of the metal derby of described test metal level by the second conductive plunger and described the second metal level is corresponding to be connected one by one.
For the essence that those skilled in the art be can better understand the present invention, make the present invention clearer, describe failure analysis structure and the analytical method thereof of the semiconductor device of the specific embodiment of the invention in detail below in conjunction with accompanying drawing.
The failure analysis structure that provides in the present invention is whether effectively to connect two metal layers corresponding with it in semiconductor product for the conductive plunger of analyzing above-mentioned semiconductor product.As an embodiment, one deck conductive plunger in the selected semiconductor product, and the two metal layers of connection corresponding to it are respectively upper metal layers and lower metal layer.Below conductive plunger in mentioned semiconductor product be selected this layer conductive plunger.
At first, be illustrated in figure 9 as failure analysis structure of the present invention, comprise substrate (not shown), and be positioned at described suprabasil the first metal layer 110 and the second metal level 120, described the first metal layer 110 is made of a plurality of metal derbies discrete and mutually insulated.Similarly, described the second metal level 120 is made of a plurality of metal derbies discrete and mutually insulated.
Described the first metal layer 110 and 120 of the second metal levels also are formed with the first insulating barrier, and successively described the first metal layer 110 is electrically connected to the formation cascaded structure with the corresponding metal derby of the second metal level 120 by the first conductive plunger 210 that is arranged in described the first insulating barrier, and described the first conductive plunger 210 only is used for being electrically connected to the first metal layer 110 metal derbies and second metal level 120 metal derbies.As other embodiment, the lower floor of described the first metal layer 110 can also include other metal-layer structure.
Wherein, described the first metal layer 110 metal derbies can be identical with quantity and the layout of the metal derby of lower metal layer in described semiconductor product.As other embodiment, described the first metal layer 110 also can be different from quantity and the layout of described lower metal layer metal derby.
Simultaneously described the first conductive plunger 210 has identical quantity and layout with conductive plunger in semiconductor product, have in even described semiconductor product and fail the conductive plunger that effectively connects, in described failure analysis structure, the first conductive plunger 210 of correspondence position fails effectively to connect equally.
Continue Fig. 9, described failure analysis structure also comprises the second conductive plunger 220 and the test metal level 130 that is positioned at successively on described the second metal level 120, and described test metal level 130 is made of a plurality of metal derbies discrete and mutually insulated.Described test metal level 130 and 120 of the second metal levels are formed with the second insulating barrier, and by the second conductive plunger 220 that is arranged between described the second insulating barrier, the corresponding metal derby of described test metal level 130 with the second metal level 120 are electrically connected to.Wherein, the metal derby of the metal derby of described test metal level 130 and the second metal level 120 is the relation of connecting one to one.
Described failure analysis structure has first end and the second end.In the present embodiment, the first end of described failure analysis structure and the second end are respectively the side a and b of test metal level 130.
As shown in Figure 10 and Figure 11, be the first metal layer 110 and second metal level 120 of failure analysis structure in failure analysis structure of the present invention.Originally the first metal layer 110 that illustrates and the second metal level 120 are array architecture, as other embodiment, also can be other structures of arranging.
As shown in figure 12, be the profile at 001 place of failure analysis structure shown in Figure 9.Comprise successively:
The first metal layer 110, and be positioned at successively the first conductive plunger 210, the second metal level 120, the second conductive plunger 220 on described the first metal layer 110 and test metal level 130, described the first metal layer 110, the second metal level 120 and test metal derby 130 comprise respectively one or more metal derby, and respectively by the megohmite insulant mutually insulated.
Described the first conductive plunger 210 is electrically connected to the formation cascaded structure with metal derby corresponding in the first metal layer 110 and the second metal level 120, and described the second conductive plunger 220 is electrically connected to corresponding metal derby in the second metal level 120 and test metal level 130.
Wherein, described quantitative relation by the first metal layer 110 and the second metal level 120 can be following three kinds of situations.
As shown in figure 12, the quantity of described the first metal layer 110 metal derbies is lacked one than the second metal level 120 metal derby quantity, and namely the metal derby at the second metal level 120 two ends only is connected with the metal derby of a first metal layer 110.
Described quantitative relation can be as shown in figure 13, and the quantity of described the second metal level 120 metal derbies is lacked one than the first metal layer 110 metal derby quantity, and namely the metal derby at the first metal layer 110 two ends only is connected with the metal derby of second metal level 120.
Described quantitative relation can also be as shown in figure 14, and the quantity of described the second metal level 120 metal derbies equals the first metal layer 110 metal derby quantity.
In order to make described the second conductive plunger 220 and the structure of test metal level 130 not impact described failure analysis construction analysis result, the size of described the second conductive plunger 220 is more than or equal to the size of described the first conductive plunger 210, increase to avoid causing forming technology difficulty because described the second conductive plunger 220 sizes are little, cause the Joint failure of the second conductive plunger 220.
Simultaneously, the area of described test metal level 130 metal derbies is not more than described the second metal level 120 metal derby areas, avoids test metal level 130 areas that need expose because of delamination excessive, the problem that the delamination that causes is inhomogeneous.
The present invention also provides a kind of failure analysis method of described failure analysis structure, is used for the conductive plunger of semiconductor product is carried out failure analysis, and described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, comprising:
Execution in step S201 provides semiconductor product and corresponding failure analysis structure thereof, and the first conductive plunger in described failure analysis structure has identical quantity and layout with the conductive plunger in semiconductor product.
Execution in step S202 carries out delamination to exposing the test metal level to described failure analysis structure.
Execution in step S203 is connected to fixed voltage with an end of described test metal level.
Execution in step S204 is incident to described test metal level with electron beam, and described test metal level produces secondary electron under the bombardment of described incident beam.
Execution in step S205 collects the secondary electron that described test metal level produces, and records and shows described secondary electron image.
Execution in step S206, described secondary electron image is analyzed: if having luminance difference in described secondary electron image, first conductive plunger at its brightness separation place has open defect, and accordingly, on described semiconductor product, the conductive plunger of correspondence position has open defect.
The failure analysis method of the present invention's one specific embodiment is to utilize ESEM to carry out failure analysis, and in prior art, ESEM comprises electron-optical system, scanning system, and the signal collection system, image shows and register system.Electron-optical system is comprised of parts such as electron gun, condenser, object lens and sample rooms, its effect is to become the incident beam that brightness is high, diameter is little to bombard sample the Electron Beam Focusing that electron gun is launched, make sample produce various physical signallings, electronic signal for example, this electronic signal comprises secondary electron, back reflection electronics, transmitted electron, absorption electronics etc.Scanning system is the particular component of ESEM, it is comprised of sweeping generator and scanning coil, its effect is: incident beam is scanned at the failure analysis body structure surface, and make the cathode-ray picture tube electron beam do synchronous scanning on phosphor screen, 2) change incident beam at the scan amplitude of failure analysis body structure surface, thereby change the multiplication factor of scanning picture.The signal collection system comprises electron collector, secondary electron detector for example, the parts that common electron collector is comprised of scintillator, photoconductive tube and photomultiplier etc., its effect is that electronic signal is collected, then convert pro rata light signal to, convert signal of telecommunication output after amplifying to, this signal of telecommunication just is used as the modulation signal of scanning picture.Image shows and register system is that the signal of telecommunication that signal collector is exported is converted to the variation of cathode-ray picture tube electron beam intensity with being ratio, so just obtain the scanning picture of the directly proportional brightness variation of a certain physics signal of a width and failure analysis structure scanning element generation on phosphor screen, perhaps record with the mode of taking a picture.The present invention carries out the image that uses in failure analysis and is the secondary electron image of ESEM, the secondary electron detector is collected the failure analysis structure and is excited the secondary electron of lower generation at incident beam, is shown and register system demonstration and record secondary electron image by image.The below describes the failure analysis method of the specific embodiment of the invention in detail.
At first, provide as shown in Figure 9 semiconductor product and failure analysis structure thereof to be analyzed, the concrete structure of described failure analysis structure can be with reference to aforementioned.Described failure analysis structure is electrically connected to the formation cascaded structure by the first conductive plunger 210 successively with the first metal layer 110 metal derbies and the second metal level 120 metal derbies, and passes through the second conductive plunger 220 with the second metal level 120 metal derbies and the corresponding electrical connection one by one successively of test metal level 130 metal derbies.Quantity and the layout of the conductive plunger in the semiconductor product of the quantity of described the first conductive plunger 210 and layout and analysis to be detected are identical.
In described failure analysis structure, the size of the second conductive plunger 220 is not less than the size of described the first conductive plunger 210, and the area of described test metal level 130 is not more than the area of described the second metal level 120.Wherein, described failure analysis structure also comprises dielectric layer or other semiconductor device (not shown) that is positioned on described test metal level 130.Described failure analysis structure has first end and the second end.In the present embodiment, the first end of described failure analysis structure and the second end are respectively the side a and b of test metal level 130.
As shown in figure 16, described failure analysis structure is carried out delamination test metal level 130 to exposing, and select an end of described failure analysis structure to be connected to fixed voltage, as earth terminal or other fixed voltages.In the present embodiment, the A of the test metal level 130 that will expose end is connected to earth terminal, and the failure analysis structure current potential of whole series connection all remains on zero potential.In the present embodiment, the test metal derby 130 that only exposes can receive incident beam, is positioned at the first metal layer 110 under described test metal derby 130 and the second metal level 120 because stopping of megohmite insulant can't receive described electron beam.
Then, make the electron gun outgoing electron bundle of ESEM, the voltage that electron gun is applied is 3～10KV, the electric current that makes electron beam is 10～20 μ A, in this voltage and current scope, can analyze the open defect that exists in the first conductive plunger 210 in described failure analysis structure, and then can analyze the open defect of the conductive plunger in semiconductor product.
In one embodiment, the voltage that electron gun is applied is 8KV, and the electric current of electron beam is 10 μ A.Be incident to the failure analysis structure from the electron beam of electron gun outgoing after the scanning system of ESEM, scanning system makes incident beam at test metal level 130 surface scans of failure analysis structure.
Then, collect the secondary electron that described test metal level 130 produces after electron excitation, record and show the secondary electron image of described test metal level 130.In the present embodiment, utilize the electron collector of signal collection system, for example the secondary electron detector, collect secondary electron signal, then convert secondary electron signal to light signal pro rata, convert signal of telecommunication output to after amplifying, this signal of telecommunication just is used as the modulation signal of scanning picture.When collecting secondary electron signal, because secondary electron is launched to all directions, apply bias voltage this moment before electron collector makes secondary electron to a direction deflection, can collect secondary electron signal in a direction, in the present embodiment, the direction that is 30 °～50 ° on test metal level 130 surfaces with the failure analysis structure is collected secondary electron.Preferably, the direction that is 35 ° on test metal level 130 surfaces with the failure analysis structure is collected secondary electron.
When collecting described secondary electron image, voltage and the contrast that can manifest by regulating secondary electron image instrument make described secondary electron image manifest highlighted state.
At last, described secondary electron image is analyzed.With reference to Figure 16, if in secondary electron image, described test metal level 130 does not have luminance difference, shown is uniform luminance, the first conductive plunger 210 that described failure analysis structure is described does not have open defect, accordingly, the conductive plunger in described semiconductor product does not have open defect yet.
With reference to Figure 17, if in described secondary electron image, described test metal level 130 has luminance difference, and its corresponding brightness separation position has open defect.In the present embodiment, 002 is the boundary take the position, the brightness of described test metal level 130 is divided into two sections, near A end test metal level 130 be highlighted state, and be black dull state near the test metal level 130 of B end, first conductive plunger 210 at the separation place of described highlighted state and black dull state exists open defect, and accordingly, in semiconductor product, the conductive plunger of correspondence position also has open defect.
As follows in conjunction with the concrete principle of Figure 17: because A end ground connection, near the test metal level 130 of A end and be connected the first metal layer 110 with it and the second metal level 120 is in ground state, (in other words the electron beam that is incident to described test metal level 130 will transfer to earth terminal, to pull on positive charge and electron beam neutralization from earth terminal), make described test metal level 130 near the A end less because of the secondary electron that receives the incident beam generation; Because described position 002 has the connection open defect, make the test metal level 130 of holding near B and be connected the first metal layer 110 with it and be not connected with earth terminal with the second metal level 120, be vacant state, be incident to described nearly test metal level 130 electron beams near the B end and can not be transferred to earth terminal (in other words, there is no the neutralization of positive charge and electron beam), make described test metal level 130 near the B end more because of the secondary electron number that receives the incident beam generation.By comparing, described test metal level 130 near the B end has more secondary electron number than the test metal level 130 that close A holds, the current potential of the test metal level 130 of described close B end is less than the current potential of the test metal level 130 of holding near A, be that described test metal level 130 near the B end has negative potential, the test metal level 130 of holding near A has zero potential.In secondary electron image, voltage difference shows as the luminance difference of secondary electron image, and current potential is high has larger brightness.Can judge at last the separation of voltage difference from the luminance difference of secondary image, described separation is the open defect position of the first conductive plunger 210 in the failure analysis structure, accordingly, in semiconductor product, the conductive plunger of corresponding position also has open defect.
Compared with prior art, have following advantage: failure analysis structure of the present invention and failure analysis method thereof only need to expose the test metal level, do not need to carry out delamination to the second metal level, can not damage described the second metal level, improve precision of analysis; Simultaneously, can not cause damage to the second insulating barrier and the first insulating barrier, further improve precision of analysis.
Further, the size of described the second conductive plunger is not more than the size of described the first conductive plunger, reduces technology difficulty, the inaccurate problem of analysis result of avoiding the loose contact because of the second conductive plunger to cause.
At last, the area of described test metal level metal derby is not more than described the second metal level metal derby area, reduces the test metal level area that need expose because of delamination excessive, and the delamination that causes is inhomogeneous.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (18)
1. the formation method of a failure analysis structure, described failure analysis structure is used for the conductive plunger of semiconductor product is carried out failure analysis, described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, it is characterized in that, comprising:
Substrate is provided, and forms the first metal layer in described substrate, described the first metal layer is made of discrete metal derby;
Form successively the first insulating barrier and the second metal level on the metal derby of described the first metal layer, has the first conductive plunger that runs through its thickness in described the first insulating barrier, described the second metal level is made of discrete metal derby, and described the second metal level metal derby is connected successively by the first conductive plunger and the first metal layer metal derby and consists of cascaded structure;
Form the second insulating barrier and be positioned at the second conductive plunger of described the second insulating barrier on described the second metal level, described the second conductive plunger is connected with the second metal level metal derby;
Form the test metal level on described the second insulating barrier, described test metal level is made of discrete metal derby, and described test metal level metal derby is corresponding connected one by one with the second metal level metal derby by the second conductive plunger.
2. the formation method of failure analysis structure according to claim 1, is characterized in that, in described the first metal layer and semiconductor product, the layer of metal layer forms simultaneously by same processing step.
3. the formation method of failure analysis structure according to claim 1, is characterized in that, the quantitative relation of described the second metal level and the first metal layer is one of following: the quantity of described the first metal layer metal derby is lacked one than the second metal level metal derby quantity; The quantity of described the second metal level metal derby is lacked one than the first metal layer metal derby quantity; The quantity of described the second metal level metal derby equals the first metal layer metal derby quantity.
4. the formation method of failure analysis structure according to claim 1, is characterized in that, the width of described the second conductive plunger is not less than the width of described the first conductive plunger.
5. the formation method of failure analysis structure according to claim 1, is characterized in that, the area of described test metal level metal derby is not more than described the second metal level metal derby area.
6. the formation method of failure analysis structure according to claim 1, is characterized in that, also is included on described test metal level to be formed with dielectric layer.
7. a failure analysis structure, be used for the conductive plunger of semiconductor product is carried out failure analysis, and described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, it is characterized in that, comprising:
Substrate;
Be positioned at successively the first metal layer and second metal level of described substrate surface, described the first metal layer and the second metal level are made of a plurality of discrete metal derbies respectively, connect successively the first metal layer metal derby by the first conductive plunger and become cascaded structure with the second metal level metal block shaped, quantity and the layout of the conductive plunger in the first conductive plunger in described failure analysis structure and semiconductor product are identical;
Be formed with the test metal level on described the second metal level, described test metal level is made of a plurality of metal derbies, and the metal derby of the metal derby of described test metal level by the second conductive plunger and described the second metal level is corresponding to be connected one by one.
8. failure analysis structure according to claim 7, it is characterized in that, described the first metal layer and the second metal interlevel are formed with the first insulating barrier, the first conductive plunger is positioned between described the first insulating barrier, be used for being electrically connected to the first metal layer and the second metal level, described the second metal level and described test metal interlevel are formed with the second insulating barrier, and the second conductive plunger is positioned between described the second insulating barrier, are used for being electrically connected to the second metal level and test metal level.
9. failure analysis structure according to claim 7, is characterized in that, described the first metal layer metal derby is identical with quantity and the layout of layer of metal layer metal derby in semiconductor product.
10. failure analysis structure according to claim 7, is characterized in that, the quantitative relation of described the second metal level and the first metal layer is one of following: the quantity of described the first metal layer metal derby is lacked one than the second metal level metal derby quantity; The quantity of described the second metal level metal derby is lacked one than the first metal layer metal derby quantity; The quantity of described the second metal level metal derby equals the first metal layer metal derby quantity.
11. failure analysis structure according to claim 7 is characterized in that, the width of described the second conductive plunger is not less than the width of described the first conductive plunger.
12. failure analysis structure according to claim 7 is characterized in that, the area of described test metal level metal derby is not more than described the second metal level metal derby area.
13. failure analysis structure according to claim 7 is characterized in that, also is formed with dielectric layer on described test metal level.
14. the failure analysis method of a failure analysis structure as claimed in claim 7, be used for the conductive plunger of semiconductor product is carried out failure analysis, described conductive plunger is used for being electrically connected to the metal derby of the adjacent two metal layers of semiconductor product, it is characterized in that, comprising:
Semiconductor product and corresponding failure analysis structure thereof are provided, and the first conductive plunger in described failure analysis structure has identical quantity and layout with the conductive plunger in semiconductor product;
Described failure analysis structure is carried out delamination to exposing the test metal level;
One end of described test metal level is connected to fixed voltage;
Electron beam is incident to described test metal level, and described test metal level produces secondary electron under the bombardment of described incident beam;
Collect the secondary electron that described test metal level produces, record and show described secondary electron image;
Described secondary electron image is analyzed: if having luminance difference in described secondary electron image, first conductive plunger at its brightness separation place has open defect, accordingly, on described semiconductor product, the conductive plunger of correspondence position has open defect.
15. described failure analysis method, is characterized in that according to claim 14, described fixed voltage is earth terminal.
16. described failure analysis method, is characterized in that according to claim 14, described electron beam forms by electron gun, and the voltage that described electron gun applies is 3～10KV, and the electric current that makes electron beam is 10～20 μ A.
17. described failure analysis method according to claim 14, it is characterized in that, if the secondary electron image of described test metal level does not have luminance difference, the first conductive plunger in described failure analysis structure does not have open defect, and there is not open defect in the conductive plunger of described semiconductor product.
18. described failure analysis method according to claim 14, it is characterized in that, if have luminance difference in described secondary electron image, and take described brightness separation as the boundary, near the brightness of the test metal level of fixed voltage one end higher than the brightness away from the test metal level of fixed voltage one end.
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| CN103926264B (en) * | 2014-03-04 | 2016-03-02 | 武汉新芯集成电路制造有限公司 | The localization method of gate oxide failpoint |
| CN105097583B (en) * | 2014-05-09 | 2018-02-13 | 中芯国际集成电路制造(北京)有限公司 | A kind of semiconductor structure failure analysis method |
| CN104897446B (en) * | 2015-05-27 | 2017-08-22 | 上海华力微电子有限公司 | A kind of sample preparation methods analyzed based on dynamic electric voltage contrast |
| CN106601720B (en) * | 2015-10-15 | 2019-03-29 | 中芯国际集成电路制造(北京)有限公司 | A kind of semi-conductor test structure and test method |
| CN111123075B (en) * | 2019-12-30 | 2022-04-22 | 武汉新芯集成电路制造有限公司 | Failure analysis method of packaged device |
| CN112269045A (en) * | 2020-10-12 | 2021-01-26 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN113224035B (en) * | 2021-01-26 | 2024-03-15 | 上海华力微电子有限公司 | Semiconductor test structure and test method |
| CN115881696A (en) * | 2023-01-31 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Test structure and test method for detecting metal bottom internal cutting defects |
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