CN102427051A - Shallow trench isolation filling method - Google Patents
Shallow trench isolation filling method Download PDFInfo
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- CN102427051A CN102427051A CN2011102502691A CN201110250269A CN102427051A CN 102427051 A CN102427051 A CN 102427051A CN 2011102502691 A CN2011102502691 A CN 2011102502691A CN 201110250269 A CN201110250269 A CN 201110250269A CN 102427051 A CN102427051 A CN 102427051A
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- shallow trench
- trench isolation
- filling
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Abstract
The invention relates to a novel method for shallow trench isolation filling. A dielectric substance of shallow trench isolation is formed; and then an active region is formed. Therefore, filling restriction and challenges in the exsiting shallow trench isolation dielectric substance filling method in the prior art are effectively solved; and a dielectric substance filling effect without cavities can be realized. Besides, the method has advantages of simple process, easiness to control and low cost.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, particularly relate to a kind of shallow trench isolation from the method for filling.
Background technologyAlong with the develop rapidly of semiconductor technology, integrated circuit fabrication process has goed deep into the deep-submicron epoch.Shallow trench isolation is from (Shallow Trench Isolation) technology; Because it has excellent isolation performance and smooth surface configuration and good anti-lock performance etc., has become a kind of device separation that is widely used in the cmos device manufacture process.
And the endless form that adopts deposit-etching-deposit-etching-deposit in the practice is usually carried out the isolation filling of shallow trench; A kind of typical method is following: a silicon substrate at first is provided; On silicon substrate, form an active area then; The active area next door that in above-mentioned steps, forms then forms the another one active area, in two active areas, forms the shallow trench across two active areas, and in shallow trench, fills silicon dioxide.This shallow trench isolation is increasingly mature through years of development from filling technique, and it can effectively utilize the live width of active area, improves integrated level, and can reach high flattening surface degree.
But in the manufacturing of cmos device, along with the device critical size constantly proportionally dwindles, it is increasing that the depth-to-width ratio that shallow trench isolation leaves also becomes in modern times.Therefore, above-mentioned shallow trench isolation has from the problem that filling mode produced: the filling of shallow trench is easy to generate hole and space, makes the complete fill process of shallow trench suffer increasing challenge; And shallow trench isolation also becomes to become increasingly complex and be difficult to from the fill process process and controls, and production cost also increases thereupon.
Summary of the invention
The object of the present invention is to provide a kind of shallow trench isolation from the method for filling, it can realize not having the shallow trench filling effect in cavity, and has simple, the manageable advantage of technical process.
To achieve these goals, the technical scheme of the present invention's employing is:
A kind of shallow trench isolation wherein, comprises the steps: from the method for filling
Step S1 a: silicon substrate is provided and deposition layer of silicon dioxide film on said silicon substrate;
Step S2: on said silica membrane, deposit one deck bottom anti-reflection layer and one deck photoresist layer successively;
Step S3: carry out photoetching process, in said photoresist layer, form a plurality of openings;
Step S4: a plurality of grooves that are positioned at silica membrane through the said silica membrane of said opening etching with formation;
Step S5: the grown silicon epitaxial loayer is to be formed with the source region in groove;
Wherein, the silica membrane between the adjacent active area constitutes fleet plough groove isolation structure, and said active area is used to constitute the well region of mos field effect transistor.
A kind of shallow trench isolation of the present invention is from the method for filling; Through at first forming the dielectric medium that shallow trench isolation leaves, then be formed with the source region again, effectively overcome the filling limitation and the challenge that run into of shallow trench isolation of the prior art from the dielectric medium fill method; Realized not having the dielectric medium filling effect in cavity; Technical process is simple, and is easy to control, with low cost.
Description of drawings
Fig. 1 is the flow chart of shallow trench isolation of the present invention from the method for filling.
Fig. 2 is a shallow trench isolation of the present invention from the method for filling.
Embodiment
Below in conjunction with Figure of description shallow trench isolation of the present invention is done further detailed explanation from the method for filling.
Just be based on shallow trench isolation technology of the prior art and proposing various concrete execution mode of the present invention.
Shown in Fig. 1 and Fig. 2 a to 2d, shallow trench isolation of the present invention is from the method for filling, and it comprises the steps:
A kind of shallow trench isolation comprises the steps: from the method for filling
Step S1 a: silicon substrate 101 is provided, and on silicon substrate 101, deposits layer of silicon dioxide film 102;
Step S2: on silica membrane 102, deposit one deck bottom anti-reflection layer 103 and photoresist layer 104 successively; Photoresist layer 104 is formed on the bottom anti-reflection layer 103 through spin-coating method;
Step S3: through in said photoresist layer 104, forming a plurality of openings 105 corresponding after the photoetching processes such as overexposure, development with required shallow trench;
Step S4: form shallow trench 106 through the 105 etch silicon dioxide films 102 of a plurality of openings in the photoresist layer 104; Wherein, In this step; With photoresist layer 104 is mask, via opening 105, adopts the method etching bottom anti-reflection layer 103 and silica membrane layer 102 of dry etching; Make silica membrane 102 form shallow trench 106, and remove photoresist layer 104 and bottom anti-reflection layer 103 with ashing method.
Step S5: in the shallow trench 106 that forms, be formed with source region 107; Wherein, in this step, at first; Deposition growing one deck epitaxial loayer (homogeneity epitaxial layer in shallow trench 107; Also be silicon epitaxy layer), and then doping is formed with source region 108 in epitaxial loayer, for example the present invention is applied to the preparation of cmos device; Be chosen in epitaxial growth P type silicon in the groove 106, the active area 107 that then is made up of P type silicon epitaxy layer can form the P type well region (P-WELL) of nmos device; And be chosen in epitaxial growth N type silicon in the groove 109; The active area 110 that then is made up of N type silicon epitaxy layer can form the N type well region (N-WELL) of PMOS device, and adjacent active area 108 and the zone of the silica membrane between the active area 109 106a then constitute fleet plough groove isolation structure (STI).
In sum, a kind of shallow trench isolation of the present invention is from the method for filling, through at first forming the dielectric medium that shallow trench isolation leaves; Then be formed with the source region again; Effectively overcome the filling limitation and the challenge that run into of shallow trench isolation of the prior art from the dielectric medium fill method, realized not having the dielectric medium filling effect in cavity, technical process is simple; Easy to control, with low cost.
Should be pointed out that foregoing is enumerating of preferred forms of the present invention, the part of wherein not describing in detail to the greatest extent is construed as with the general fashion in present technique field and implements.Simultaneously, for one of ordinary skill in the art, in not departing from spiritual category of the present invention,, all will fall within the protection range of claim of the present invention equivalent transformation and modification that the present invention did.
Claims (1)
1. a shallow trench isolation is characterized in that from the method for filling, and comprises the steps:
Step S1 a: silicon substrate is provided and deposition layer of silicon dioxide film on said silicon substrate;
Step S2: on said silica membrane, deposit one deck bottom antireflective coating and one deck photoresist layer successively;
Step S3: carry out photoetching process, in said photoresist layer, form a plurality of openings;
Step S4: a plurality of grooves that are positioned at silica membrane through the said silica membrane of said opening etching with formation;
Step S5: the grown silicon epitaxial loayer is to be formed with the source region in groove;
Wherein, the silica membrane between the adjacent active area constitutes fleet plough groove isolation structure, and said active area is used to constitute the well region of mos field effect transistor.
Priority Applications (1)
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CN2011102502691A CN102427051A (en) | 2011-08-29 | 2011-08-29 | Shallow trench isolation filling method |
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CN2011102502691A CN102427051A (en) | 2011-08-29 | 2011-08-29 | Shallow trench isolation filling method |
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CN102427051A true CN102427051A (en) | 2012-04-25 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108470709A (en) * | 2018-03-29 | 2018-08-31 | 上海华力集成电路制造有限公司 | The manufacturing method of insulation structure of shallow groove |
CN114242651A (en) * | 2022-02-24 | 2022-03-25 | 北京芯可鉴科技有限公司 | Shallow trench isolation structure manufacturing method and shallow trench isolation structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1428835A (en) * | 2001-12-20 | 2003-07-09 | 东部电子株式会社 | Method for forming isolated film of semiconductor element |
CN101093799A (en) * | 2006-06-23 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
CN101828260A (en) * | 2007-10-18 | 2010-09-08 | Nxp股份有限公司 | Method of manufacturing localized semiconductor-on-insulator (soi) structures in a bulk semiconductor wafer |
-
2011
- 2011-08-29 CN CN2011102502691A patent/CN102427051A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1428835A (en) * | 2001-12-20 | 2003-07-09 | 东部电子株式会社 | Method for forming isolated film of semiconductor element |
CN101093799A (en) * | 2006-06-23 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
CN101828260A (en) * | 2007-10-18 | 2010-09-08 | Nxp股份有限公司 | Method of manufacturing localized semiconductor-on-insulator (soi) structures in a bulk semiconductor wafer |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108470709A (en) * | 2018-03-29 | 2018-08-31 | 上海华力集成电路制造有限公司 | The manufacturing method of insulation structure of shallow groove |
CN114242651A (en) * | 2022-02-24 | 2022-03-25 | 北京芯可鉴科技有限公司 | Shallow trench isolation structure manufacturing method and shallow trench isolation structure |
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Application publication date: 20120425 |