CN102427029A - Preparation technology of testing device structure for monitoring relevant manufacturing procedure and follow-up manufacturing procedure of grid electrode - Google Patents
Preparation technology of testing device structure for monitoring relevant manufacturing procedure and follow-up manufacturing procedure of grid electrode Download PDFInfo
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- CN102427029A CN102427029A CN2011102221490A CN201110222149A CN102427029A CN 102427029 A CN102427029 A CN 102427029A CN 2011102221490 A CN2011102221490 A CN 2011102221490A CN 201110222149 A CN201110222149 A CN 201110222149A CN 102427029 A CN102427029 A CN 102427029A
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Abstract
The invention discloses a preparation technology of a testing device structure for monitoring a relevant manufacturing procedure and a follow-up manufacture procedure of a grid electrode. Only single crystal silicon is adopted as a substrate, and a commonly used STI lamination structure (silicon substrate + silicon oxide + silicon nitride + photoresist) can be adopted before patterning. The preparation technology can be widely applied to the detection of step coverage of an offset spacer, a spacer, a stress memorization technique (SMT), a contact etch strop layer (CESL), moreover, the development time can be reduced effectively, the development cost is lowered, and the preparation technology is simple and easy to control.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate to a kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof specifically.
Background technology
Integrated circuit is exactly on the semiconductor-based end, to form a series of element, to accomplish function corresponding.But the existing processes monitor mode generally adopts the silicon chip (structure wafer) of entire flow, usually, in order to save monitoring cost, in practical operation, generally can select monocrystalline substrate control sheet; And in the operating procedure of reality, can omit steps such as ion injection usually, with on the basis that does not influence geomery (profile), reduce cost.
Shown in Figure 1A-1C; The preparation technology of the test component structure that is used for relevant processing procedure of grid and successive process monitoring thereof that is adopted in the prior art comprises the steps: at first; One silicon substrate 11 is provided, on silicon substrate 11, deposits an one deck cushion oxide layer 12 and a polysilicon layer 13 successively; Next, polysilicon layer 13 is carried out etching, expose cushion oxide layer 12, formation is positioned at polysilicon gate construction 13a and the 13b on the cushion oxide layer 12.But this process general cost is higher, and relatively prolongs the Products Development time, therefore, needs to propose a kind of preparation technology of the test component structure that is used for relevant processing procedure of grid and successive process monitoring thereof newly.
Summary of the invention
The object of the present invention is to provide a kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof, it can effectively save the development time, reduces cost.
For solving above-mentioned purpose, technical scheme provided by the present invention is:
A kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof wherein, comprises the steps:
Step S1 a: silicon substrate is provided, on said silicon substrate, deposits a cushion oxide layer and a silicon nitride layer successively, and on said silicon nitride layer, apply one deck photoresist;
Step S2: said photoresist layer is carried out photoetching process, expose said silicon nitride layer, form the photoresist that is positioned on the said silicon nitride layer and keep structure;
Step S3: with said photoresist reservation structure is the said silicon nitride layer of mask etching, exposes said cushion oxide layer, forms to be positioned at the silicon nitride reservation structure that said photoresist keeps the structure below, and removes said photoresist reservation structure;
Step S4: keeping structure with said silicon nitride is said cushion oxide layer of mask etching and said silicon substrate, forms the cushion oxide layer that is arranged in the sample grid of said silicon substrate and is covered on the said sample grid and keeps structure;
Step S5: remove said cushion oxide layer and keep structure.
Above-mentioned preparation technology wherein, adopts the said silicon nitride layer of dry etching etching in said step S3.
Above-mentioned preparation technology wherein, adopts said cushion oxide layer of dry etching etching and said silicon substrate in said step S4.
Above-mentioned preparation technology, wherein, described cushion oxide layer be silicon dioxide layer.
A kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof wherein, comprises the steps:
Step S1 a: silicon substrate is provided, on said silicon substrate, deposits a cushion oxide layer and a silicon nitride layer successively, and on said silicon nitride layer, apply one deck photoresist;
Step S2: said photoresist layer is carried out photoetching process, expose said silicon nitride layer, form the photoresist that is positioned on the said silicon nitride layer and keep structure;
Step S3: with said photoresist reservation structure is the mask said silicon nitride layer of etching successively, exposes said cushion oxide layer, forms to be positioned at the silicon nitride reservation structure that said photoresist keeps the structure below, and removes said photoresist reservation structure;
Step S4: with said silicon nitride reservation structure is the said cushion oxide layer of mask etching, exposes said silicon substrate, forms to be positioned at the cushion oxide layer reservation structure that said silicon nitride keeps the structure below, and removes said silicon nitride reservation structure;
Step S5: keeping structure with said silicon nitride is the said silicon substrate of mask etching, forms to be positioned at the sample grid that said cushion oxide layer keeps the structure below.
Step S6: remove said cushion oxide layer and keep structure.
Above-mentioned preparation technology wherein, adopts the said silicon nitride layer of dry etching etching respectively in said step S3.
Above-mentioned preparation technology wherein, adopts the said cushion oxide layer of dry etching etching respectively in said step S4.
Above-mentioned preparation technology wherein, adopts the said silicon substrate of dry etching etching respectively in said step S5.
Above-mentioned preparation technology, wherein, described cushion oxide layer is a silicon dioxide layer.
A kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof of the present invention; It only adopts monocrystalline silicon as substrate, and before graphical, can adopt STI laminated construction commonly used (silicon substrate+silicon dioxide+silicon nitride+photoresist); It can be widely used in skew side wall (offset spacer), side wall separator (spacer), stress memory film (Stress memorization technique; Abbreviation SMT), via etch stops a layer (Contact etch stop layer; The detection of step coverage abbreviation CESL); And can effectively reduce the development time, and reducing development cost, preparation technology is simple and easy to control.
Description of drawings
Figure 1A-1C is the preparation technology's of a kind of test component structure of the prior art formed sectional structure chart of each step;
Fig. 2 is the flow chart of first kind of embodiment of the preparation technology of a kind of test component structure that is used for relevant processing procedure of grid and successive process monitoring thereof of the present invention;
Fig. 2 A-2E is formed cross-sectional view by each step of the preparation technology of of the present invention a kind of test component structure that is used for relevant processing procedure of grid and successive process monitoring thereof shown in Figure 2;
Fig. 3 is the flow chart of second kind of embodiment of the preparation technology of a kind of test component structure that is used for relevant processing procedure of grid and successive process monitoring thereof of the present invention;
Fig. 3 A-3F is of the present invention a kind of formed cross-sectional view of each step that is used for the test component structure preparation technology of relevant processing procedure of grid and successive process monitoring thereof shown in Figure 3;
Fig. 4 is used for the application sketch map of the test component structure of relevant processing procedure of grid and successive process monitoring thereof at the step coverage that detects side wall silicon nitride or oxide for application invention is formed;
Fig. 5 uses sketch map for using the formed monitoring that is used for the space filling capacity of test component structure between adjacent two grids of PMD processing procedure of relevant processing procedure of grid and successive process monitoring thereof of the present invention.
Embodiment
Come a kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof of the present invention is done explanation in further detail below in conjunction with Figure of description and embodiment.
Please, in embodiments of the invention one, be used for the preparation technology of the test component structure of relevant processing procedure of grid and successive process monitoring thereof, comprise the steps: especially referring to shown in Fig. 2 A-2E
Step S1 a: silicon substrate 101 is provided, on silicon substrate 101, deposits a silicon dioxide layer 102 and a silicon nitride layer 103 successively, and on silicon nitride layer 103, apply one deck photoresist 104 with spin-coating method;
Step S2: photoresist 104 is carried out photoetching process (comprising processing steps such as exposure, development), expose silicon nitride layer 103, form the photoresist that is positioned on the silicon nitride layer 103 and keep structure 104a, 104b;
Step S3: with photoresist reservation structure 104a, 104b is that mask adopts dry etching etch silicon nitride layer 103; Expose silicon dioxide layer 102; Formation is positioned at silicon nitride reservation structure 103a, the 103b that photoresist keeps structure 104a, 104b below, and removes photoresist reservation structure 104a, 104b;
Step S4: with silicon nitride reservation structure 103a, 103b is mask etching silicon dioxide layer 102 and silicon substrate 101, forms the silicon dioxide layer that is arranged in sample grid 101a, the 101b of silicon substrate 101 and is covered on the sample grid and keeps structure 102a, 102b;
Step S5: remove silicon dioxide layer and keep structure 102a, 102b; And on said sample grid 101a, 101b and silicon substrate 101, deposit testing film; Utilize said sample grid to monitor the step coverage of the testing film that covers the sample grid; Side wall (offset spacer), side wall separator (spacer), stress memory film (Stress memorization technique for example squint; Abbreviation SMT), via etch stops layer (Contact etch stop layer is called for short CESL) (seeing also shown in Figure 4).In addition, in like manner can utilize sample grid 101a, 101b that other technologies are monitored accordingly, dry etching for example, (the seeing also shown in Figure 5) such as monitorings of the space filling capacity between adjacent two grids of PMD processing procedure.
Further, please, comprise the steps: at embodiments of the invention two especially referring to shown in the 3A-3F
Step S1 a: silicon substrate 101 is provided, on silicon substrate 101, deposits a silicon dioxide layer 102 and a silicon nitride layer 103 successively, and on silicon nitride layer 103, apply one deck photoresist 104 with spin-coating method;
Step S2: photoresist 104 is carried out photoetching process (comprising processing steps such as exposure, development), expose silicon nitride layer 103, form the photoresist that is positioned on the silicon nitride layer 103 and keep structure 104a, 104b;
Step S3: with photoresist reservation structure 104a, 104b is that mask adopts dry etching etch silicon nitride layer 103; Expose silicon dioxide layer 102; Formation is positioned at silicon nitride reservation structure 103a, the 103b that photoresist keeps structure 104a, 104b below, and removes photoresist reservation structure 104a, 104b;
Step S4: with silicon nitride reservation structure 103a, 103b is mask etching silicon dioxide layer 102, exposes layer silicon dioxide layer 102, forms to be positioned at silicon dioxide layer reservation structure 102a, the 102b that silicon nitride keeps structure 103a, 103b below;
Step S5: with silicon dioxide layer reservation structure 102a, 102b is mask etching silicon substrate 101, forms to be positioned at silicon dioxide layer reservation structure 102a, the sample grid 101a of 102b, 101b;
Step S6: remove silicon dioxide layer and keep structure 102a, 102b; And on said sample grid 101a, 101b and silicon substrate 101, deposit testing film; Utilize said sample grid 101a, 101b to monitor the step coverage of the testing film that covers the sample grid; Side wall (offset spacer), side wall separator (spacer), stress memory film (Stress memorization technique for example squint; Abbreviation SMT), via etch stops layer (Contact etch stop layer is called for short CESL) (seeing also shown in Figure 4).In addition, in like manner can utilize the sample grid that other technologies are monitored accordingly, dry etching for example, (the seeing also shown in Figure 5) such as monitorings of the space filling capacity between adjacent two grids of PMD processing procedure.
In sum; A kind of preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof of the present invention; It only adopts monocrystalline silicon as substrate, and before graphical, can adopt STI laminated construction commonly used (silicon substrate+silicon dioxide+silicon nitride+photoresist); It can be widely used in skew side wall (offset spacer), side wall separator (spacer), stress memory film (Stress memorization technique; Abbreviation SMT), via etch stops a layer (Contact etch stop layer; The detection of step coverage abbreviation CESL); And can effectively reduce the development time, and reducing development cost, preparation technology is simple and easy to control.
Should be pointed out that foregoing is enumerating of specific embodiment of the present invention, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; And above-mentioned specific embodiment is not to be used for limiting practical range of the present invention, and promptly all equivalent transformation and modifications of doing according to content of the patent of the present invention all fall into protection scope of the present invention.
Claims (10)
1. a preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof is characterized in that, comprises the steps:
Step S1 a: silicon substrate is provided, on said silicon substrate, deposits a cushion oxide layer and a silicon nitride layer successively, and on said silicon nitride layer, apply one deck photoresist;
Step S2: said photoresist layer is carried out photoetching process, expose said silicon nitride layer, form the photoresist that is positioned on the said silicon nitride layer and keep structure;
Step S3: with said photoresist reservation structure is the said silicon nitride layer of mask etching, exposes said cushion oxide layer, forms to be positioned at the silicon nitride reservation structure that said photoresist keeps the structure below, and removes said photoresist reservation structure;
Step S4: keeping structure with said silicon nitride is said cushion oxide layer of mask etching and said silicon substrate, forms the cushion oxide layer that is arranged in the sample grid of said silicon substrate and is covered on the said sample grid and keeps structure;
Step S5: remove said cushion oxide layer and keep structure.
2. preparation technology as claimed in claim 1 is characterized in that, in said step S3, adopts the said silicon nitride layer of dry etching etching.
3. preparation technology as claimed in claim 1 is characterized in that, in said step S4, adopts said cushion oxide layer of dry etching etching and said silicon substrate.
4. like claim 1 or 3 described preparation technologies, it is characterized in that, described cushion oxide layer be silicon dioxide layer.
5. a preparation technology who is used for the test component structure of relevant processing procedure of grid and successive process monitoring thereof is characterized in that, comprises the steps:
Step S1 a: silicon substrate is provided, on said silicon substrate, deposits a cushion oxide layer and a silicon nitride layer successively, and on said silicon nitride layer, apply one deck photoresist;
Step S2: said photoresist layer is carried out photoetching process, expose said silicon nitride layer, form the photoresist that is positioned on the said silicon nitride layer and keep structure;
Step S3: with said photoresist reservation structure is the mask said silicon nitride layer of etching successively, exposes said cushion oxide layer, forms to be positioned at the silicon nitride reservation structure that said photoresist keeps the structure below, and removes said photoresist reservation structure;
Step S4: with said silicon nitride reservation structure is the said cushion oxide layer of mask etching, exposes said silicon substrate, forms to be positioned at the cushion oxide layer reservation structure that said silicon nitride keeps the structure below, and removes said silicon nitride reservation structure;
Step S5: keeping structure with said silicon nitride is the said silicon substrate of mask etching, forms to be positioned at the sample grid that said cushion oxide layer keeps the structure below.
6. step S removes said cushion oxide layer reservation structure.
7. preparation technology as claimed in claim 5 is characterized in that, in said step S3, adopts the said silicon nitride layer of dry etching etching respectively.
8. preparation technology as claimed in claim 5 is characterized in that, in said step S4, adopts the said cushion oxide layer of dry etching etching respectively.
9. preparation technology as claimed in claim 5 is characterized in that, in said step S5, adopts the said silicon substrate of dry etching etching respectively.
10. like claim 5 or 7 described preparation technologies, it is characterized in that described cushion oxide layer is a silicon dioxide layer.
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| CN2011102221490A CN102427029A (en) | 2011-08-04 | 2011-08-04 | Preparation technology of testing device structure for monitoring relevant manufacturing procedure and follow-up manufacturing procedure of grid electrode |
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| CN2011102221490A CN102427029A (en) | 2011-08-04 | 2011-08-04 | Preparation technology of testing device structure for monitoring relevant manufacturing procedure and follow-up manufacturing procedure of grid electrode |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106098549A (en) * | 2016-08-27 | 2016-11-09 | 力特半导体（无锡）有限公司 | Use the method that surface mask structure carries out silicon etching |
| CN107968058A (en) * | 2017-11-23 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of measurement characterizing method of deep hole etching bottom silicon substrate pattern |
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| US20050282352A1 (en) * | 2003-10-14 | 2005-12-22 | Samsung Electronics Co., Ltd. | Method of forming dual gate dielectric layer |
| CN1941319A (en) * | 2005-09-29 | 2007-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method and structure of double lining for isolating shallow slot |
| CN101009236A (en) * | 2006-01-24 | 2007-08-01 | 中芯国际集成电路制造(上海)有限公司 | A method for making CDSEM calibration sample |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
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2011
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Patent Citations (5)
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| US20040175950A1 (en) * | 2003-03-03 | 2004-09-09 | Lam Research Corporation | Method to improve profile control and n/p loading in dual doped gate applications |
| US20050282352A1 (en) * | 2003-10-14 | 2005-12-22 | Samsung Electronics Co., Ltd. | Method of forming dual gate dielectric layer |
| CN1941319A (en) * | 2005-09-29 | 2007-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method and structure of double lining for isolating shallow slot |
| CN101009236A (en) * | 2006-01-24 | 2007-08-01 | 中芯国际集成电路制造(上海)有限公司 | A method for making CDSEM calibration sample |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106098549A (en) * | 2016-08-27 | 2016-11-09 | 力特半导体（无锡）有限公司 | Use the method that surface mask structure carries out silicon etching |
| CN107968058A (en) * | 2017-11-23 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of measurement characterizing method of deep hole etching bottom silicon substrate pattern |
| CN107968058B (en) * | 2017-11-23 | 2020-11-13 | 长江存储科技有限责任公司 | Measuring and representing method for deep hole etching bottom silicon substrate appearance |
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Application publication date: 20120425 |