CN102426370B - Block correlation accumulation method used for GPS (Global Positioning System) signal acquisition algorithm - Google Patents
Block correlation accumulation method used for GPS (Global Positioning System) signal acquisition algorithm Download PDFInfo
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Abstract
The invention discloses a block correlation accumulation method used for GPS (Global Positioning System) signal acquisition algorithm. The block correlation accumulation method is characterized in that length of a matched filtering block is set to be the length of an I circuit register block, a Q circuit register block and a local C/A (Coarse/Acquisition) code register block, meanwhile obtained block correlation data is stored by utilizing result distinguished by a series of divisions, and finally the block correlation data is output to a backward stage of FFT (Fast Fourier Transform) processing module. By adopting the technical scheme of the invention, register resource occupancy of the whole correlation accumulation process is optimized, application amount of register is saved on one hand, and design is beneficial.
Description
Technical field
The present invention relates to the method used in the gps signal capture technique, specifically a kind of relevant accumulation method of segmentation that belongs in part matched filtering parallel frequency catching algorithm.
Background technology
Gps satellite navigation neceiver baseband digital signal is processed mainly to use and is caught and follow the tracks of two modules.Trapping module is mainly realized the estimation to satellite signal carrier frequency and pseudo-code code phase, the initial value of frequency and code phase is provided for the carrier wave ring of tracking module and code ring, the accurate and fragile carrier wave ring of tracking module and code ring can be worked and the locking satellite signal.
In the technology that trapping module uses, be one of important acquisition algorithm based on the parallel frequency catching algorithm of part matched filtering always.This algorithm is relevant cumulative by the zero intermediate frequency digital signal on I road and Q road is carried out respectively segmentation, not only obtained spreading gain, and reduced data rate, thus reduced counting of follow-up Fast Fourier Transform (FFT) (FFT) module, reduced and realized difficulty.Although this algorithm does not need very complicated Fourier transform module, if the relevant accumulator module of segmentation is not optimized design, its realization often needs to expend huge register resources, increases greatly the power consumption of trapping module.Based on this, the relevant accumulation method of segmentation is reasonably designed, make its characteristics with saving resource, the inevitable demand when just becoming such trapping module design.
Summary of the invention
Inevitable demand during based on above trapping module design, the present invention proposes the relevant accumulation method of a kind of segmentation for the gps signal acquisition algorithm, and its technical scheme is as follows:
The relevant accumulation method of a kind of segmentation for the gps signal acquisition algorithm, it comprises the following steps:
Step 1: initialization comprises: synchronizing sequence receives I from Digital Down Convert, Q road zero intermediate frequency digital signal; Set periodic sampling in the C/A code 1ms H that counts, the sampling number A of half chip, and the number C of the length B of a matched filter block and described matched filter block; Make D=B/A, D is integer; Separately establish initial value and be a variable k of 0;
Step 2: division is differentiated, and after completing above-mentioned steps one, take k as dividend, D is divisor, makes that its business be Y, and remainder is X, constructs a bivector [X, Y]:
4) if X=Y=0, the sequence order of pressing signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with the local C/A code of the B length of order, deposit in separately in I road block of registers, Q road block of registers and the C/A block of registers of B length; Then k increases progressively 1;
5) if Y＞0 and X=0 continue to read the zero intermediate frequency digital signal on I road, the Q road of A length, and deposit separately described I road block of registers and Q road block of registers in; Continue simultaneously to read the local C/A code of B length and deposit described C/A Code memory piece in; Then k increases progressively 1;
6) if the zero intermediate frequency digital signal on I road, the Q road of A length is continued to read in X＞0 and Y＞0, and deposit separately described I road block of registers and Q road block of registers in, then k increases progressively 1;
Step 3: relevant cumulative; After carrying out step 2, the common mark of current data in described I road block of registers, Q road block of registers and C/A block of registers is designated as current X, described bivector [X, Y] corresponding to Y value; Data in described I road block of registers that again will be this moment and Q road block of registers respectively to C/A Code memory piece in data make relevant accumulating operation, each operation result that obtains is corresponding described bivector [X, Y] still, and preservation separately;
Step 4: reset: set up criterion with k=D*C, if, with described I road block of registers, Q road block of registers with C/A Code memory piece empties, k zero setting, all described I road, Q road zero intermediate frequency digital signal is initial reads and the initial original order of pressing each sequence that reads of sequence of local C/A code is reset, X=Y=0 in described bivector; If not, still get back to other situations of step 2 judgement k value;
Step 5: read: the described operation result that previous step is obtained, will wait each time the owner of X value mark to read by the sequence of X, successively all carry out FFT and process.
As the preferred person of the technical program, on the basis of above technical scheme, following improvement can be arranged:
In one preferred embodiment, described I road block of registers prime also arranges an input block, I road, and described Q road block of registers prime also arranges an input block, Q road; The control that this input block, I road and input block, Q road are subjected to sequential circuit transfers to respectively described I road block of registers and Q road block of registers with the I road zero intermediate frequency digital signal of correspondence and Q road zero intermediate frequency digital signal by its sequence order.
In one preferred embodiment, described C/A Code memory block prefix has a storer by sequence sequential loop output C/A code.
In one preferred embodiment, it is D that a line number is set, and columns is the storage matrix of C, and each described operation result deposits the unit corresponding to the capable Y row of X of this storage matrix in by described bivector [X, Y]; In described step 5, described storage matrix is read by the row full line.
Be provided with on the scheme basis of I road, input block, Q road, in one preferred embodiment, the data of (G*H-B*C) length are read respectively in input block, I road described in described step 4, input block, Q road on existing state, simultaneously the reading pointer of described local C/A code recovers initial value, reads a little with the initial of each corresponding sequence of resetting.
As the corresponding device of above technical scheme, can be following scheme:
A kind of segmentation of gps signal acquisition algorithm adding up device of being correlated with, it comprises:
One I road input buffer, its input end connect the I road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects an I road block of registers;
One Q road input buffer, its input end connect the Q road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects a Q road block of registers;
One C/A code sequence storage unit, its output terminal connects a C/A Code memory piece;
Has the relevant totalizer in I road between described I road block of registers and C/A Code memory piece; Has the relevant totalizer in Q road between described Q road block of registers and C/A Code memory piece; This relevant totalizer in I road all is connected to one first buffer register to the relevant totalizer output terminal in Q road;
Described the first buffer register output terminal connects a RAM matrix, and this RAM matrix connects the FFT processing module by one second buffer register;
Wherein, the memory length of described I road block of registers, Q road block of registers and C/A Code memory piece is the matched filtering block length B of setting; The line number of described RAM matrix is that the matched filtering block length is except the business D of 1 chip samples point; Described RAM matrix column number is matched filter block number C; Separately there is time schedule controller to connect simultaneously described I road input buffer, Q road input buffer, C/A code sequence storage unit and described RAM matrix.
The beneficial effect that the present invention brings is:
With the matched filtering block length as I road, Q road and local C/A Code memory length, the register resources occupancy volume of whole relevant cumulative process is optimized, saved the register use amount.
2. adopting D length line number, C length is the storage matrix of columns, and the Optimum Path storage resources also is beneficial to being connected and reading of summation module and rear class FFT module.
3. whole treating apparatus is simple for structure, and treatment effeciency is high.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing embodiment:
Fig. 1 is the embodiment process flow diagram of the relevant segmentation accumulation method of the present invention;
Fig. 2 is the segmentation adding up device block diagram of correspondence embodiment illustrated in fig. 1.
Embodiment
As Fig. 1, the embodiment process flow diagram of the relevant segmentation accumulation method of the present invention; Fig. 2 is the segmentation adding up device block diagram of correspondence embodiment illustrated in fig. 1.Be explained in conjunction with this two figure:
From flow process, initialization step 10 has comprised the periodic sampling of setting in the C/A code 1ms H=16367667 that counts, the sampling number A=8 of half chip, and so the length B=664 of matched filter block, and the number C=49 of described matched filter block be D=B/A=83.Specifically, it is optimal values after emulation that the length B of matched filter block is set as 664, and this length 664 is also the length of I road block of registers 112 in Fig. 2, Q road block of registers 122 and C/A Code memory piece 102.
Level has I road input buffer 111 before the input end of I road block of registers 112, and accordingly, the input end value prime of Q road block of registers 122 has Q road input buffer 121; I road, Q road input buffer has an input end Iport and Qport separately, connects respectively from the I road after Digital Down Convert and Q road orthogonal signal; The input end prime of C/A block of registers 102 is C/A code sequence storage unit 101 of a ROM form, under the control of time schedule controller 170, I road input buffer 111, Q road input buffer 121 is synchronously exported respectively the two-way orthogonal signal to level thereafter, and C/A code sequence storage unit is also synchronously exported the C/A code of 1ms loop cycle simultaneously; I this moment road block of registers 112, Q road block of registers 122 and the C/A Code memory piece 102 controlled receiving sequences separately of beginning are also processed, and enter division discriminating step 20.
In division discriminating step 20, take k (initial value 0) as dividend, D as divisor, make that its business is Y, remainder is X, structure one bivector [X, Y], according to processing respectively after following condition distinguishing:
1) judgement in step 21, if k=0, be X=Y=0, be [0 to the bivector assignment in step 22,0], press the sequence order of signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with the local C/A code of the B length of order, deposit in separately in I road block of registers 112, Q road block of registers 122 and C/A block of registers 102; Then k increases progressively 1;
2) judgement in step 23, if k is non-vanishing and be the n of D doubly (n is integer), be Y＞0 and X=0, the bivector assignment is [0 in step 24, k/D], continue to read the zero intermediate frequency digital signal on I road, the Q road of A length, and deposit separately I road block of registers 112 and Q road block of registers 122 in; Continue simultaneously to read the local C/A code of B length and deposit C/A Code memory piece 102 in; Then k increases progressively 1;
3) as the judgement of step 23, if k is non-vanishing and be not also the integral multiple of D, get final product to get X＞0 and Y＞0, namely change step 25 over to, bivector [X, Y] occurs with non-zero; Continue to read the zero intermediate frequency digital signal on I road, the Q road of A length, and deposit separately I road block of registers 112 and Q road block of registers 122 in, then k increases progressively 1;
Above 1), 2) and 3) three kinds of situations, carry out flow process as can be known from actual sequence, begin to increase progressively gradually from 0 from the k value, only can select one each time and carry out, whenever carrying out once, must keep in corresponding data in I road block of registers 112, Q road block of registers 122 and C/A Code memory piece 102, simultaneously can concrete bivector [X of assignment, Y], often obtain a bivector, change next relevant accumulation step 30 over to.
In relevant accumulation step 30,102 the common mark of current data in described I road block of registers 112, Q road block of registers 122 and C/A block of registers is designated as current X, described bivector [X, Y] corresponding to Y value; Data in described I road block of registers 112 that again will be this moment and Q road block of registers 122 respectively to C/A Code memory piece 102 in data make relevant accumulating operation, accordingly, processing element is be correlated with totalizer 113 and the relevant totalizer 123 in Q road of I road; Each operation result that obtains still corresponding this moment the bivector of assignment [X, Y], and preserve separately; Every correlations accumulation step 30 is carried out and is obtained an operation result and its corresponding bivector [X, Y], and preserves in order these corresponding results.
determine each operation result and corresponding bivector [X, Y] after, the capital enters reset process 40, the effect of this step is to judge whether all data due to the segmentation addition in a complete process are disposed, so, instantaneous value with reference to the k value, take k=D*C as setting up criterion, if result is yes in determining step 41, know that the preservation of segmentation phase of all data adduction is complete, so enter replacement step 42, with I road block of registers 112, Q road block of registers 122 and C/A Code memory piece 102 empty, k sets to 0, all I road, Q road zero intermediate frequency digital signal is initial to be read and the initial original order of pressing each sequence that reads of sequence of local C/A code is reset, comprise I road input buffer 111, Q road input buffer 121 is read respectively (G*H-B*C) length on existing state data read a little to reach the initial of each corresponding sequence of resetting.In bivector, X, Y all set to 0;
If in determining step 41, the judged result of k=D*C is no, and meaning is not disposed for the data of matched filtering segmentation addition, still gets back to other situations of step 2 judgement k value this moment, in this example, gets back to step 23 and continues judgement k value; As long as k is not incremented to net result D*C, division discriminating step 20 can be carried out repeatedly, until bivector [X, Y] and corresponding operation result thereof are all preserved.The method of this preservation is to obtain by depositing operation result in RAM matrix 140 through the first buffer register 130 each time, and this RAM matrix is a two-dimensional storage environment, and its line number is matched filtering block length B except the half chip samples A that counts, namely 83; Its columns is matched filter block number C, namely 49.
When reset process 40 is able to complete execution, be after 140 storages of RAM matrix finish, enter reading step 50: in this reading step 50, under time schedule controller 170 is controlled, all operation results with 140 storages of RAM matrix, read by its row full line, arrive the FFT processing module 160 of rear class via the second impact damper 150, all FFT conversion of finishing dealing with line by line; The way of output of these RAM matrix 140 full lines, its every delegation is the row that in corresponding bivector [X, Y], the vector of all under same X value forms.
As seen, in whole relevant cumulative processing procedure, block of registers, no matter be I road, Q road or the block of registers of C/A code, its length all is not more than the matched filtering block length B of setting, and by simulation optimization, controlled register length can be optimized, the design that facilitates register resources distributes, and also is beneficial to the relevant accumulator module that obtains saving very much register resources.
The above, only for preferred embodiment of the present invention, therefore can not limit according to this scope of the invention process, the equivalence of namely doing according to the scope of the claims of the present invention and description changes and modifies, and all should still belong in the scope that the present invention contains.
Claims (5)
1. relevant accumulation method of segmentation that is used for the gps signal acquisition algorithm, it is characterized in that: it comprises the following steps:
Step 1: initialization comprises: synchronizing sequence receives I from Digital Down Convert, Q road zero intermediate frequency digital signal; Set periodic sampling in the C/A code 1ms H that counts, the sampling number A of half chip, and the number C of the length B of a matched filter block and described matched filter block; Make D=B/A, D is integer; Separately establish initial value and be a variable k of 0;
Step 2: division is differentiated, and after completing above-mentioned steps one, take k as dividend, D is divisor, makes that its business be Y, and remainder is X, constructs a bivector [X, Y]:
1) if X=Y=0, the sequence order of pressing signal, read respectively a B length I road, Q road the zero intermediate frequency digital signal and with the local C/A code of the B length of order, deposit in separately in I road block of registers, Q road block of registers and the C/A block of registers of B length; Then k increases progressively 1;
2) if Y〉0 and X=0, continue to read the zero intermediate frequency digital signal on I road, the Q road of A length, and deposit separately described I road block of registers and Q road block of registers in; Continue simultaneously to read the local C/A code of B length and deposit described C/A Code memory piece in; Then k increases progressively 1;
3) if X〉0 and Y 0, continue to read the zero intermediate frequency digital signal on I road, the Q road of A length, and deposit separately described I road block of registers and Q road block of registers in, then k increases progressively 1;
Step 3: relevant cumulative; After carrying out step 2, the common mark of current data in described I road block of registers, Q road block of registers and C/A block of registers is designated as current X, described bivector [X, Y] corresponding to Y value; Data in described I road block of registers that again will be this moment and Q road block of registers respectively to C/A Code memory piece in data make relevant accumulating operation, each operation result that obtains is corresponding described bivector [X, Y] still, and preservation separately;
Step 4: reset: set up criterion with k=D*C, if, with described I road block of registers, Q road block of registers with C/A Code memory piece empties, k zero setting, all described I road, Q road zero intermediate frequency digital signal is initial reads and the initial original order of pressing each sequence that reads of local C/A code sequence is reset, X=Y=0 in described bivector; If not, still get back to other situations of step 2 judgement k value;
Step 5: read: the described operation result that previous step is obtained, will wait each time the owner of X value mark to read by the sequence of X, successively all carry out FFT and process.
2. the relevant accumulation method of a kind of segmentation for the gps signal acquisition algorithm according to claim 1 is characterized in that: described I road block of registers prime also arranges an input block, I road, and described Q road block of registers prime also arranges an input block, Q road; The control that this input block, I road and input block, Q road are subjected to sequential circuit transfers to respectively described I road block of registers and Q road block of registers with the I road zero intermediate frequency digital signal of correspondence and Q road zero intermediate frequency digital signal by its sequence order.
3. the relevant accumulation method of a kind of segmentation for the gps signal acquisition algorithm according to claim 1, it is characterized in that: described C/A Code memory block prefix has a storer by sequence sequential loop output C/A code.
4. the relevant accumulation method of a kind of segmentation for the gps signal acquisition algorithm according to claim 1, it is characterized in that: it is D that a line number is set, columns is the storage matrix of C, and each described operation result deposits the unit corresponding to the capable Y row of X of this storage matrix in by described bivector [X, Y]; In described step 5, described storage matrix is read by the row full line.
5. the relevant adding up device of the segmentation of a gps signal acquisition algorithm, it is characterized in that: it comprises:
One I road input buffer, its input end connect the I road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects an I road block of registers;
One Q road input buffer, its input end connect the Q road zero intermediate frequency digital signal from Digital Down Convert output, and its output terminal connects a Q road block of registers;
One C/A code sequence storage unit, its output terminal connects a C/A Code memory piece;
Has the relevant totalizer in I road between described I road block of registers and C/A Code memory piece; Has the relevant totalizer in Q road between described Q road block of registers and C/A Code memory piece; This relevant totalizer in I road all is connected to one first buffer register to the relevant totalizer output terminal in Q road;
Described the first buffer register output terminal connects a RAM matrix, and this RAM matrix connects the FFT processing module by one second buffer register;
Wherein, the memory length of described I road block of registers, Q road block of registers and C/A Code memory piece is the matched filtering block length B of setting; The line number of described RAM matrix is that the matched filtering block length is divided by the business D of 1 chip samples point; Described RAM matrix column number is matched filter block number C; Separately there is time schedule controller to connect simultaneously described I road input buffer, Q road input buffer, C/A code sequence storage unit and described RAM matrix.
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| CN101625404A (en) * | 2008-07-09 | 2010-01-13 | 杭州中科微电子有限公司 | GPS signal large-scale parallel quick capturing method and module thereof |
| CN101741424A (en) * | 2009-12-24 | 2010-06-16 | 航天恒星科技有限公司 | Method for rapidly capturing multi-mode high dynamic spread spectrum signal |
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| CN101741424A (en) * | 2009-12-24 | 2010-06-16 | 航天恒星科技有限公司 | Method for rapidly capturing multi-mode high dynamic spread spectrum signal |
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