CN102420604A - Duty ratio recovery circuit of low noise - Google Patents
Duty ratio recovery circuit of low noise Download PDFInfo
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- CN102420604A CN102420604A CN2011103786718A CN201110378671A CN102420604A CN 102420604 A CN102420604 A CN 102420604A CN 2011103786718 A CN2011103786718 A CN 2011103786718A CN 201110378671 A CN201110378671 A CN 201110378671A CN 102420604 A CN102420604 A CN 102420604A
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- circuit
- duty ratio
- rising edge
- low noise
- trigger
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Abstract
The invention discloses a duty ratio recovery circuit of low noise. The circuit comprises: a rising edge alignment circuit and a falling edge alignment circuit. And the circuit is formed by a feedback signal D and a reference clock C based on a PLL. The circuit is characterized in that: for the falling edge alignment, output of a trigger can be satisfied; for the rising edge alignment, the output of a trigger can be satisfied. By using the technical scheme of the invention, the duty ratio of the clock can be recovered to 50% of an ideal ratio. Simultaneously, at least one of the rising edge and the falling edge possesses low noise performance. The circuit is simple and costs are low.
Description
Technical field
The present invention relates to pulse signal duty ratio modulation circuit, relate in particular to a kind of being used for and reach 50% restore circuit keeping recovering duty ratio under the low noise conditions.
Background technology
Many electronic systems need the good clock of duty ratio, usually need be in 50% ± 5%.As shown in Figure 1, because input clock, possibly pass through long PCB cabling from chip exterior, the duty ratio that arrives the input clock signal of chip may depart from 50%, particularly the clock frequency higher system.
Just can generate a clock that frequency is consistent with it to input clock signal as the reference of phase-locked loop (PLL), the duty ratio of this clock can accomplish desirable about 50%.But the clock signal that is produced by PLL often has bigger shake, can not satisfy system requirements in some applications.On the modulation recovery problem of duty ratio, be conceived to use feedback signal D and the reference clock C of this phase-locked loop PPL, be to be expected to accomplish that the duty ratio that arrives the input clock signal of chip keeps 50%.
Summary of the invention
Deficiency in view of above-mentioned prior art exists the objective of the invention is to propose a kind of low noise duty ratio restore circuit, to obtain under the low noise state desirable about 50% duty ratio.
A kind of implementation of the object of the invention is:
A kind of low noise duty ratio restore circuit; Comprise two versions of rising edge alignment circuit and trailing edge alignment circuit; And feedback signal D and reference clock C based on phase-locked loop constitute; It is characterized in that: aim at for trailing edge,
satisfied in the output of trigger; Aim at for rising edge,
satisfied in the output of trigger.
Further, the data terminal of said trigger presets switchable 1 or 0.
Use technical scheme of the present invention, its remarkable advantage is presented as: can the duty ratio of clock be returned to desirablely about 50%, can guarantee again simultaneously to have at least to rise and prolong or of decline Yanzhong has low-noise performance, and circuit be simple, cost is low.
Description of drawings
Fig. 1 is the sketch map of traditional die external timing signal duty ratio substantial deviation behind the PCB cabling;
Fig. 2 is restore circuit of the present invention is aimed at a preferred embodiment at trailing edge a structural representation;
Fig. 3 is restore circuit of the present invention is aimed at a preferred embodiment at rising edge a structural representation;
Fig. 4 is restore circuit of the present invention is aimed at a preferred embodiment at trailing edge a structural representation;
Fig. 5 is restore circuit of the present invention is aimed at a preferred embodiment at rising edge a structural representation.
Embodiment
Following constipation closes the embodiment accompanying drawing, and specific embodiments of the invention is done further to detail, so that technical scheme of the present invention is easier to understand, grasp.
The present invention obtains low noise about 50% duty ratio for modulation, and innovation has proposed a kind of duty ratio restore circuit.It comprises rising edge alignment circuit and trailing edge alignment circuit two parts, and constitutes based on the feedback signal D of phase-locked loop and reference clock C, and wherein this restore circuit is actual effectively only aims at or trailing edge in aiming at has low-noise performance at rising edge.
From the concrete scheme of preferred embodiment, as shown in Figure 2, be the circuit diagram that restore circuit trailing edge of the present invention is aimed at.Its principle explanation as follows.
The feedback signal D of phase-locked loop has 50% duty ratio but shake is big, and the reference clock C of phase-locked loop shakes low but the duty ratio.The phase frequency detector PFD of phase-locked loop can make the rising edge of D signal and C signal or trailing edge aim at.For the PFD that trailing edge is aimed at, the requirement of aiming at according to trailing edge can calculate logical formula
through truth table.And then obtain preferred embodiment circuit diagram as shown in Figure 2.Select circuit through logic, make the trailing edge of rising edge and the C of D control the upset of trigger respectively, rising edge has C to determine by the D decision just to export the trailing edge of Q.
As shown in Figure 3, be the circuit diagram that restore circuit rising edge of the present invention is aimed at.Its principle explanation as follows.
The feedback signal D of phase-locked loop has 50% duty ratio but shake is big, and the reference clock C of phase-locked loop shakes low but the duty ratio.The phase frequency detector PFD of phase-locked loop can make the rising edge of D signal and C signal or trailing edge aim at.For the PFD that rising edge is aimed at, the requirement of aiming at according to rising edge can calculate logical formula
through truth table.And then obtain preferred embodiment circuit diagram as shown in Figure 3.Select circuit through logic, make the rising edge of trailing edge and the C of D control the upset of trigger respectively, trailing edge has C to determine by the D decision just to export the rising edge of Q.
Again from the present invention's one improved circuit structure, like Fig. 4 and shown in Figure 5.Improved circuit need not to wait for data stabilization through presetting number at the flip-flop data end, therefore can significantly improve the operating frequency of duty ratio restore circuit.Because trigger input data by the decision of output feedback, if come the also unstable state that just possibly lead to errors of feedback signal then at rising edge clock, have limited operating frequency.Select to export the opposite logic of signal in advance at data terminal and can eliminate the required stand-by period of prototype version.If output Q is low then data terminal switches to height.Otherwise, if output Q is a height then data terminal switches to low.The clock end operation is similar with prototype version, whenever output switching activity switches to another group input immediately, waits for that the arrival of its rising edge triggers next group output switching activity.
Visible in sum; Use technical scheme of the present invention, its remarkable advantage is presented as: can the duty ratio of clock be returned to desirablely about 50%, can guarantee again simultaneously to have at least to rise and prolong or of decline Yanzhong has low-noise performance; And circuit is simple, and cost is low.
Claims (2)
1. low noise duty ratio restore circuit; Comprise two versions of rising edge alignment circuit and trailing edge alignment circuit; And feedback signal D and reference clock C based on phase-locked loop constitute; It is characterized in that: aim at for trailing edge,
satisfied in the output of trigger; Aim at for rising edge,
satisfied in the output of trigger.
2. a kind of low noise duty ratio restore circuit as claimed in claim 1, it is characterized in that: the data terminal of said trigger presets switchable 1 or 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103786718A CN102420604A (en) | 2011-11-24 | 2011-11-24 | Duty ratio recovery circuit of low noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103786718A CN102420604A (en) | 2011-11-24 | 2011-11-24 | Duty ratio recovery circuit of low noise |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102420604A true CN102420604A (en) | 2012-04-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103786718A Pending CN102420604A (en) | 2011-11-24 | 2011-11-24 | Duty ratio recovery circuit of low noise |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102420604A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329847B1 (en) * | 1998-09-29 | 2001-12-11 | U.S. Phillips Corporation | Radio device including a frequency synthesizer and phase discriminator for such a device |
| US7734001B2 (en) * | 2004-02-09 | 2010-06-08 | Nec Electronics Corporation | Fractional frequency divider circuit and data transmission apparatus using the same |
| CN102281059A (en) * | 2010-03-25 | 2011-12-14 | 硅谷实验室公司 | Method and apparatus for quantization noise reduction in fractional-N PLLS |
-
2011
- 2011-11-24 CN CN2011103786718A patent/CN102420604A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329847B1 (en) * | 1998-09-29 | 2001-12-11 | U.S. Phillips Corporation | Radio device including a frequency synthesizer and phase discriminator for such a device |
| US7734001B2 (en) * | 2004-02-09 | 2010-06-08 | Nec Electronics Corporation | Fractional frequency divider circuit and data transmission apparatus using the same |
| CN102281059A (en) * | 2010-03-25 | 2011-12-14 | 硅谷实验室公司 | Method and apparatus for quantization noise reduction in fractional-N PLLS |
Non-Patent Citations (1)
| Title |
|---|
| 池保勇等: "《CMOS射频集成电路分析与设计》", 16 January 2006, article "锁相环路的基本原理与性能分析" * |
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Owner name: SUZHOU 3PEAK ELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: 3PEAKIC (SUZHOU) MICROELECTRONICS CO., LTD. Effective date: 20120604 |
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Effective date of registration: 20120604 Address after: Xinghu Street Industrial Park of Suzhou city in Jiangsu province 215123 No. 328 Creative Industry Park 2-B304-1 Applicant after: Suzhou Ruipu Electronic Technology Co. Ltd. Address before: Suzhou City, Jiangsu province 215123 Xinghu Park Street No. 328 Creative Industry Park 2-B304 Applicant before: 3peakic (Suzhou) Microelectronics Co., Ltd. |
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Owner name: 3PEAKIC MICROELECTRONICS (SUZHOU) CO., LTD. Free format text: FORMER OWNER: SUZHOU 3PEAKIC MICROELECTRONIC TECHNOLOGY CO., LTD. Effective date: 20130201 |
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Effective date of registration: 20130201 Address after: Xinghu Street Industrial Park of Suzhou city in Jiangsu province 215123 No. 328 Creative Industry Park 2-B304-1 Applicant after: Scarlett Ruipu microelectronics technology (Suzhou) Co., Ltd. Address before: Xinghu Street Industrial Park of Suzhou city in Jiangsu province 215123 No. 328 Creative Industry Park 2-B304-1 Applicant before: 3peakic (Suzhou) Microelectronics Co., Ltd. |
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Application publication date: 20120418 |