CN102420244A - One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof - Google Patents
One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof Download PDFInfo
- Publication number
- CN102420244A CN102420244A CN201110359848XA CN201110359848A CN102420244A CN 102420244 A CN102420244 A CN 102420244A CN 201110359848X A CN201110359848X A CN 201110359848XA CN 201110359848 A CN201110359848 A CN 201110359848A CN 102420244 A CN102420244 A CN 102420244A
- Authority
- CN
- China
- Prior art keywords
- electrode
- electrode pair
- dimensional metal
- semiconductor
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Junction Field-Effect Transistors (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a one-dimensional metal/semiconductor nanometer heterojunction transistor and a preparation method thereof. The preparation method comprises the following steps of: providing a silicon sheet with an oxide layer; arranging a first electrode pair and a second electrode pair on the oxide layer, wherein a pre-set angle is formed between the first electrode pair and the second electrode pair, the first electrode pair comprises a first electrode and a second electrode, the second electrode pair comprises a third electrode and a fourth electrode; putting electroplate liquid between the first electrode and the second electrode and applying an alternative current to forming a one-dimensional metal nanometer wire with a disconnected middle part; putting suspension solution containing a semiconductor nanometer wire at the middle disconnected part and applying the alternative current to connecting the semiconductor nanometer wire with the one-dimensional metal nanometer wire; and forming another one-dimensional metal nanometer wire between the third electrode and the fourth electrode. According to the method provided by the invention, the influence on scattering effects by one-dimensional conduction of current carriers is weakened and a one-dimensional heterojunction is assembled on a target position by utilizing an alternative current deposition and dielectrophoresis combined method. The one-dimensional metal/semiconductor nanometer heterojunction transistor has the advantages of no need of masks, vacuum environment and the like, has low cost, and is suitable for the batch production.
Description
Technical field
The present invention relates to little/receive Mechatronic Systems, little/the Nanoelectronic Technology field, the preparation method of particularly a kind of one-dimensional metal/semiconductor nano heterojunction transistor and this one-dimensional metal/semiconductor nano heterojunction transistor.
Background technology
Different systems has different Fermi levels; After when two kinds of different objects of work function contact, having flow of charge to reach heat balance identical Fermi level is arranged between the two; And the mobile formation space charge region of electric charge causes that band curvature produces Schottky (Schottky) potential barrier at the interface.Today, the operation principle of nearly all important semiconductor device was all relevant with heterojunction and schottky junction; And one-dimensional metal/heterojunction semiconductor is an ideal functionality primitive of constructing nanometer electronic device; Therefore, it is one type of novel nano-material that presses for research and development.
Along with the development of nanometer technology, developed the FET device of some nano wires at present.For example based on field-effect transistor (the Sander J.Tans of CNT; Alwin R.M.Verschueren&Cees Dekker, Room-temperature transistor based on a single carbon nanotube.Nature, 1998; 393; 49-51), at present the FET device of nanoscale mainly adopts the method for electric field controls, thereby promptly makes hearth electrode or top electrode utilizes the carrier concentration in the field intensity control nano material to realize the field effect controlled function; But this method exists control voltage height, response speed to wait problem slowly because control electrode and nano material have certain distance.
At present the preparation method of heterojunction has a lot, as: chemical vapour deposition technique (CVD), template, intermolecular non-covalent bond self-assembly method, thermal evaporation sedimentation, liquid phase method, gas-liquid-solid sedimentation (VLS), electron beam lithography and reactive ion etching method, electrochemistry " dip in " (dip-pen) method such as nanometer etching method and molecular beam epitaxial growth method are used to prepare one-dimensional metal/heterojunction semiconductor nanostructure in succession.But the above-mentioned method existence for preparing metal/semiconductor heterojunction nanostructure needs costliness, complex apparatus; Need problems such as template and high temperature and condition of high vacuum degree environment, thereby limited the batch low-cost production and the application of metal/semiconductor heterojunction nanostructure.
Therefore the present invention has disclosed and has utilized electro-deposition and dielectrophoresis to combine to assemble the method for one-dimensional nano heterogeneous knot, and based on the transistor of employing base stage and the direct contacting structure of semiconductor and the control method of one-dimensional metal/heterojunction semiconductor
Summary of the invention
The present invention is intended to one of solve the problems of the technologies described above at least.
For this reason; One object of the present invention is to propose the nano heterogeneous junction transistors of a kind of metal/semiconductor: adopt base stage and direct contacting structure of semiconductor and control method, the transistor of this structure has realized that the one dimension electron motion of conductivity process is charge carrier one dimension transmission having weakened scattering.
Another object of the present invention is to propose the transistorized preparation method of a kind of as above-mentioned embodiment.This method can guarantee the integrality of this body structure of nano material and performance, has improved the performance of transistorized circuit.And this method preparation cost is low, is fit to produce in batches.
To achieve these goals, the one-dimensional metal of first aspect present invention embodiment/semiconductor nano heterojunction transistor comprises substrate, and the upper surface of said substrate is formed with oxide layer; First electrode pair, said first electrode pair is arranged on the said oxide layer, and said first electrode pair comprises spaced apart first and second electrodes, and wherein said first and second electrodes link to each other through one-dimensional metal/semiconductor heterojunction nanowire; Second electrode pair; Said second electrode pair is arranged on the said oxide layer and with said first electrode pair and becomes predetermined angular; Said second electrode pair comprises spaced apart third and fourth electrode; Wherein said third and fourth electrode links to each other through the one-dimensional metal nano wire, and wherein, the semiconductor nanowires of the one-dimensional metal/semiconductor heterojunction nanowire between one-dimensional metal nano wire between said second electrode pair and said first electrode pair crosses.
Cut-in voltage according to the one-dimensional metal/semiconductor nano heterojunction transistor of the embodiment of the invention is low; The power consumption time-delay is long-pending low; Therefore this transistor has the fast advantage of response speed; And therefore the structural integrity of this transistorized with a high standard, one-dimensional metal nano wire and semiconductor nano heterojunction has promoted transistorized performance.In addition, this is transistorized low in energy consumption.
Preparation method according to one-dimensional metal/semiconductor nano heterojunction transistor of second aspect present invention embodiment may further comprise the steps: silicon chip is provided, and oxidation is carried out to form oxide layer in the surface of said silicon chip; Through photoetching method first electrode pair is set on the said oxide layer and on said oxide layer to become the direction of predetermined angular that second electrode pair is set with said first electrode pair; Wherein said first electrode pair comprises spaced apart first and second electrodes, and said second electrode pair comprises spaced apart third and fourth electrode; Between said first and second electrodes, put into electroplate liquid and said first and second electrodes applied first alternating current of first scheduled time, through electro-deposition with exchange the dielectrophoresis method that combines and between said first and second electrodes, form the one-dimensional metal nano wire that mid portion breaks off; Put into the suspension that comprises semiconductor nanowires and said first and second electrodes are applied second alternating current of second scheduled time at the middle gap of said one-dimensional metal nano wire, the method through dielectrophoresis is connected semiconductor nanowires with said one-dimensional metal nano wire; Between said third and fourth electrode, put into said electroplate liquid and said third and fourth electrode applied the 3rd alternating current of the 3rd scheduled time, through said electro-deposition with exchange the dielectrophoresis method that combines and between said third and fourth electrode, form another one-dimensional metal nano wire.Thereby the formation transistor arrangement, wherein third electrode or the 4th electrode are base stage, first electrode or second electrode are collector electrode or emitter.
The preparation method of one-dimensional metal according to the above embodiment of the present invention/semiconductor nano heterojunction transistor; This method is through applying the control of the size and the frequency of alternating current to first electrode pair and second electrode pair; And the method for utilizing dielectrophoresis and electro-deposition to combine realizes the production of one-dimensional metal nano wire, one dimension semiconductor nano heterojunction; And when producing, realize once being connected with the assembling of first electrode pair or second electrode pair; Therefore, transistorized preparation efficiency is high, and speed is fast.And can be simultaneously to multi-group electrode to parallel work-flow, be fit to produce in batches.In addition, this method can guarantee the integrality of this body structure of nano material and performance, improved the performance of transistorized circuit, and this method preparation cost is low.
In addition, the preparation method of one-dimensional metal according to the above embodiment of the present invention/semiconductor nano heterojunction transistor can also have following additional technical characterictic:
In one embodiment of the invention; Before the middle gap of said one-dimensional metal nano wire is put into the suspension that comprises semiconductor nanowires, also comprise: the suspension that will comprise semiconductor nanowires through the excusing from death process for dispersing disperseed 30-90 minute in the ultrasonic cleaning pond.
In one embodiment of the invention, between said third and fourth electrode, form after another one-dimensional metal nano wire, the one-dimensional metal that obtains/semiconductor nano heterojunction transistor is cleaned and dries through semiconductor cleaning method.
In one embodiment of the invention, said first and second electrodes being applied peak value is that 1～20V, frequency are 10
3～10
7After first scheduled time of first alternating current of Hz, breaking off the alternating current that is applied to said first and second electrodes through monitoring device is the breaking part of 10nm-10 μ m between said first and second electrodes, to form length.
In one embodiment of the invention, said first and second electrodes being applied for second scheduled time is that 5～10 seconds peak value is that 1～20V, frequency are 10
3～10
7Second alternating current of Hz is to be connected semiconductor nanowires with said one-dimensional metal nano wire.
The concentration of the electroplate liquid of between said third and fourth electrode, putting into according to one embodiment of present invention, is 2 * 10
-8Mol/l～2 * 10
-3Mol/l, said the 3rd scheduled time is 4～6 seconds, the peak value of said the 3rd alternating current between 1～20V and frequency 10
3～10
7Between the Hz.
In one embodiment of the invention, said first electrode pair and said second electrode pair are Pt/Cr electrode pair or Cr/Au electrode pair.
Additional aspect of the present invention and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage obviously with are easily understood becoming the description of embodiment from combining figs, wherein:
Fig. 1 is the structure chart of the one-dimensional metal/semiconductor nano heterojunction transistor of the embodiment of the invention;
Fig. 2 is preparation method's the flow chart of the one-dimensional metal/semiconductor nano heterojunction transistor of the embodiment of the invention;
Fig. 3 is the sketch map of step S103 and step S104 among the preparation method shown in Figure 2;
Fig. 4 A is the module frame chart of monitoring device among the preparation method of the embodiment of the invention;
Fig. 4 B is the circuit function block diagram of monitoring device among the preparation method of the embodiment of the invention;
Fig. 4 C is the data acquisition control core of monitoring device among the preparation method of the embodiment of the invention;
Fig. 5 is the I-V curve chart of preparation gold/carbon nano-tube heterojunction among the preparation method of the embodiment of the invention;
Fig. 6 is the transmission electron microscope (TEM) and the electron diffraction pattern sketch map of the one dimension nanowires of gold that obtains among the preparation method of one embodiment of the invention; With ESEM (SEM) sketch map of Fig. 7 for gold/single-wall carbon nanotube heterojunction of obtaining among the preparation method of one embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention; It will be appreciated that; The orientation of indications such as term " " center ", " vertically ", " laterally ", " on ", D score, " preceding ", " back ", " left side ", " right side ", " vertically ", " level ", " top ", " end ", " interior ", " outward " or position relation are for based on orientation shown in the drawings or position relation; only be to describe with simplifying for the ease of describing the present invention; rather than the device or the element of indication or hint indication must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.In addition, term " first ", " second " only are used to describe purpose, and can not be interpreted as indication or hint relative importance.
In description of the invention, need to prove that only if clear and definite regulation and qualification are arranged in addition, term " installation ", " linking to each other ", " connection " should be done broad understanding, for example, can be to be fixedly connected, also can be to removably connect, or connect integratedly; Can be mechanical connection, also can be to be electrically connected; Can be directly to link to each other, also can link to each other indirectly through intermediary, can be the connection of two element internals.For those of ordinary skill in the art, can concrete condition understand above-mentioned term concrete implication in the present invention.
Below in conjunction with accompanying drawing the one-dimensional metal/semiconductor nano heterojunction transistor according to the embodiment of the invention is described at first.
As shown in Figure 1, be the structure chart of the one-dimensional metal/semiconductor nano heterojunction transistor of the embodiment of the invention.One-dimensional metal/semiconductor nano heterojunction transistor 100 according to the embodiment of the invention comprises substrate 110, first electrode pair 130 and second electrode pair 150.
The upper surface of substrate 110 is formed with oxide layer 120, and in one embodiment of the invention, the material of substrate 110 is silicon (Si), and advantageously, oxide layer 120 (silicon dioxide) forms through the upper surface oxidation of substrate 110 (silicon chip).
Wherein, the semiconductor nanowires 170 of the one-dimensional metal/semiconductor heterojunction nanowire 140 between said first electrode pair 130 crosses (intersect and link to each other) with another one-dimensional metal nano wire 160 between said second electrode pair 150.In one embodiment of the invention, semiconductor nanowires 170 is a SWCN.
Cut-in voltage according to the one-dimensional metal/semiconductor nano heterojunction transistor 100 of the embodiment of the invention is low; The power consumption time-delay is long-pending low; Therefore one-dimensional metal/semiconductor nano heterojunction transistor 100 has the fast advantage of response speed; And one-dimensional metal/semiconductor nano heterojunction transistor 100 is with a high standard, by the complete structure that one-dimensional metal nano wire and one dimension semiconductor heterojunction nano-wire are formed, has therefore promoted the processing performance of one-dimensional metal/semiconductor nano heterojunction transistor 100.In addition, the one-dimensional metal of the foregoing description/semiconductor nano heterojunction transistor 100 is low in energy consumption.
In examples more of the present invention, for example first electrode pair 130 and second electrode pair 150 are Pt/Cr electrode pair or Cr/Au electrode pair.Promptly first electrode 131 and second electrode 132 can be Pt/Cr electrode pair or Cr/Au electrode pair, and third electrode 151 and the 4th electrode 152 can be Pt/Cr electrode pair or Cr/Au electrode pair equally.Need to prove that first electrode pair 130 can be identical with second electrode pair 150, also can be different, the present invention is to this not restriction.
The preparation method of the one-dimensional metal/semiconductor nano heterojunction transistor according to the embodiment of the invention is described below; For the ease of describing the preparation method of the embodiment of the invention; Below to be example with the one-dimensional metal/semiconductor nano heterojunction transistor of preparation in the foregoing description do detailed description to the preparation method of the embodiment of the invention; But the preparation method of the embodiment of the invention is not limited to prepare the one-dimensional metal/semiconductor nano heterojunction transistor in the foregoing description.
As shown in Figure 2, be the preparation method's of the one-dimensional metal/semiconductor nano heterojunction transistor of the embodiment of the invention flow chart.This method may further comprise the steps:
Step S101 provides silicon chip, and oxidation is carried out to form oxide layer in the surface of said silicon chip.Shown in Fig. 3 A, choose silicon chip 110, oxidation is formed with oxide layer 120 (silicon dioxide layer) on silicon chip 110.
Step S102; Through photoetching method first electrode pair is set on the said oxide layer and on said oxide layer to become the direction of predetermined angular that second electrode pair is set with said first electrode pair; Wherein said first electrode pair comprises spaced apart first and second electrodes, and said second electrode pair comprises spaced apart third and fourth electrode.
Particularly; In conjunction with Fig. 1, one embodiment of the present of invention are utilized Ledit software design electrode structure domain, make mask plate; The two arrays of electrodes that uses photoetching method (photoetching process) pattern-making to arrange as cross then is right; Like the predetermined angular between first electrode pair 130 and second electrode pair, 150, the first electrode pairs 130 and second electrode pair 150 is 90 degree, and this predetermined angular can change as required certainly.Further, in this embodiment, two arrays of electrodes is made electrode pair to all adopting the Pt/Cr metal, and certainly, in other embodiments of the invention, first electrode pair 130 and second electrode pair 150 also can adopt Cr/Au to make.Follow clean silicon chip 110, the embodiment of the invention adopts P type polished silicon slice 110, removes organic substance, metal residue and oxide, adopts thermal oxidations to form 5000 dust SiO2 layer oxide layer 120 on silicon chip 110 surfaces.The mode that adopts centrifugal rotation to throw glue is coated with the positive photoresists glue of 0.5～5 μ m.Make public then and dry, then carry out development treatment.RIE corrodes 1500 dust oxide layers 120; Sputter
adhesion layer is through electron gun evaporation process deposition
electrode layer.Wherein, splash-proofing sputtering process parameter is that 4Pa, sputtering current 5mA, sputtering voltage 1000V, sputtering time are 45s for coating chamber vacuum degree.Through stripping process, be about to silicon chip 110 and be immersed in the remaining photoresist of rinsing in the solvent at last, obtain to have the silicon chip of electrode pair.
Step S103; Between said first and second electrodes, put into electroplate liquid and said first and second electrodes applied first alternating current of first scheduled time, through electro-deposition with exchange the dielectrophoresis method that combines and between said first and second electrodes, form the one dimension nanowires of gold that mid portion breaks off.
Particularly, shown in Fig. 3 A-3C, first electrode 131 and second electrode 132 are introduced external circuit, apply ac signal, in an example of the present invention, applying peak value is that 1～20V, frequency are 10
3～10
7First alternating current of Hz, preferably peak value is 10V, then drips 10 μ l electroplate liquids, be first scheduled time conduction time, like 5～10s, on silicon chip, processes the one-dimensional metal nano wire, in one embodiment of the invention, is the one-dimensional single crystal nanowires of gold.Wherein, transmission electron microscope (TEM) sample prepares according to following steps, utilizes gold-plated tungsten tip to do growth electrode growth nanowires of gold (one dimension nanowires of gold), and slow the moving of gold thread is placed on the copper mesh.Transmission electron microscope (TEM) test result is as shown in Figure 6, significantly, can know that from the electron diffraction pattern of Fig. 6 lower left the lattice fringe line of seeing gold thread is arranged in parallel towards a direction, and therefore, nanowires of gold is a mono-crystalline structures.Mono-crystalline structures has the good conductive heat conductivility, can reduce power consumption and reduce heating.The nanowires of gold pattern evenly, diameter is between 10～50nm.Wherein electroplate liquid is the gold plating liquid of ethanol based, and promptly 0.15g iodine and 0.15g KI dissolve gold to saturated obtaining after being dissolved in 20ml alcohol under 80 degrees centigrade of constant temperature.
Then; When the nanowires of gold growth was connected on first electrode and second electrode, gold thread received Joule heat fusing to form breach, the breach 171 shown in 3C among the figure; Sending the current impulse analog signal is input in the monitoring device;, cut off from outside power supply (disconnection is applied to the alternating current of said first and second electrodes) and stop the gold thread growth, thereby obtain to have the breach nanowires of gold when having detected the pulse signal trailing edge like FPGA.As between said first and second electrodes, form length be 10nm-10 μ m breaking part as, promptly the breach of fusing is 10nm-10 μ m.
Shown in Fig. 4 C, the external monitoring device adopted Xilinx Spatan III Series FPGA as the ADS8365 of main control chip and two TI as modulus conversion chip.Combined circuit functional block diagram 4A and Fig. 4 B, the inner band of ADS8365 sampling hold circuit supports 6 channel difference sub-signal synchronized samplings to keep, the highest 250kSPS of sampling rate, conversion accuracy is 16-bit.Outside 12 tunnel signals collecting of main completion are gathered each road signal respectively when 12 groups of electrodes are grown simultaneously, the AD that after the metal nanometer line assembling, fuses collects pulse signal and sends to FPGA and break off the shutoff signal source at signal trailing edge control optical coupled switch.
Step S104; Put into the suspension that comprises semiconductor nanowires and said first and second electrodes are applied second alternating current of second scheduled time at the middle gap of said one-dimensional metal nano wire, the method through dielectrophoresis connects semiconductor nanowires (the assembling head and the tail mutually) with said one-dimensional metal nano wire.
In conjunction with Fig. 3 D, dripping concentration is 2.5 * 10
-4The suspension that comprises semiconductor nanowires of mg/ml (SWCN dispersion liquid) adopts dielectrophoresis assembling SWCN in the nanowires of gold indentation, there.In one embodiment of the invention, the second alternating current peak value is 1～20V, and frequency is 10
3～10
7Hz.Energising was second scheduled time, like 5～10s.The work function of semiconductor nanowires (SWCN) is about 4.8eV; The work function of gold is about 5.3eV; Can cause band curvature when being in contact with one another, electronics flows in the material of high work function, so constitutes Schottky barrier between metal nanometer line and the SWCN.In this embodiment, measure asymmetrical I-V curve through using Keithley 6487 type picoammeters, as shown in Figure 5, promptly SWCN has overlapped between notched nanowires of gold, as can obviously finding out through Fig. 7.In the above-described embodiments, SWCN dispersion liquid (suspension that comprises semiconductor nanowires) adopts the high-purity SWCN dispersion liquid of U.S. Nano Integris, and wherein the diameter of SWCN is about 1.8nm, and length is 3～5 μ tm.
Step S105; Between said third and fourth electrode, put into said electroplate liquid and said third and fourth electrode applied the 3rd alternating current of the 3rd scheduled time, through said electro-deposition with exchange dielectrophoresis and combine and between said third and fourth electrode, form another one-dimensional metal nano wire.Need to understand, formed transistor arrangement in the foregoing description, third electrode or the 4th electrode are base stage, first electrode or second electrode are collector electrode or emitter.In other words, one of them of electrode pair that between electrode pair, is connected with heterojunction nano-wire is as collector electrode, and another is as emitter.
Identical with the mode of preparation metal nanometer line among the step S103, difference is to reduce the step of mid portion fusing and the change of parameter, is 2 * 10 like the concentration of the electroplate liquid between said third and fourth electrode, put into
-8Mol/l～2 * 10
-3Mol/l, said the 3rd scheduled time is 4～6 seconds, the peak value of said the 3rd alternating current between 5～10V and frequency 10
3～10
7Between the Hz.In order to reduce redundancy, do not do and give unnecessary details.
The preparation method of one-dimensional metal according to the above embodiment of the present invention/semiconductor nano heterojunction transistor; This method is through applying the control of the size and the frequency of alternating current to first electrode pair and second electrode pair; And the method for utilizing dielectrophoresis and electro-deposition to combine realizes the production of one-dimensional metal nano wire, one dimension semiconductor nano heterojunction; And when producing, realize once being connected with the assembling of first electrode pair or second electrode pair; Therefore, transistorized preparation efficiency is high, and speed is fast.And can be simultaneously to multi-group electrode to parallel work-flow, be fit to produce in batches.In addition, this method can guarantee the integrality of this body structure of nano material and performance, improved the performance of transistorized circuit, and this method preparation cost is low.
In one embodiment of the invention; Before the middle gap of said one-dimensional metal nano wire is put into the suspension that comprises semiconductor nanowires, comprise that also the suspension that will comprise semiconductor nanowires through the excusing from death process for dispersing disperseed 30-90 minute in the ultrasonic cleaning pond.Advantageously, the cleaning fluid in the ultrasonic cleaning pond for example adopts absolute ethyl alcohol.
In one embodiment of the invention, between said third and fourth electrode, form after another one-dimensional metal nano wire, the one-dimensional metal that obtains/semiconductor nano heterojunction transistor is cleaned and dries through semiconductor cleaning method.Promptly remove the organic substance and the oxide on surface, obtain the heterojunction transistor that is assembled with of surface cleaning with deionized water wash with the absolute ethyl alcohol cleaning silicon chip.The oven dry sample utilizes ESEM (SEM) that sample is observed, and combines Fig. 6 once more, can be known by figure, and the nano wire pattern of the semiconductor nano heterojunction that gets through method for preparing is even, and the interface is clear.
Certainly, between first electrode and second electrode, the one-dimensional metal nano wire and another one-dimensional metal nano wire that form between third electrode and the 4th electrode be the one-dimensional single crystal metal nanometer line.But embodiments of the invention are not limited to this, and promptly both also can be different, and the present invention is to this not restriction.In addition; First electrode pair of the foregoing description and said second electrode pair are Pt/Cr electrode pair or Cr/Au electrode pair, and promptly two arrays of electrodes also can be different to being Pt/Cr or Cr/Au electrode pair simultaneously; Like first electrode pair is the Pt/Cr electrode pair; Second electrode pair is the Cr/Au electrode pair, and vice versa, and the present invention does not limit this equally.
Transistorized preparation method according to the embodiment of the invention.This method can guarantee the integrality of this body structure of nano material and performance, has improved the performance of transistorized circuit.And this method preparation cost is low, is fit to produce in batches.And semiconductor nano heterostructure pattern homogeneous, this method need not template, and can at room temperature operate, and economy realizes the preparation of one dimension semiconductor nano heterojunction apace.Therefore, be the electronic device microminiaturization, modularization, bottom-up assembling provides example.
Describe and to be understood that in the flow chart or in this any process otherwise described or method; Expression comprises module, fragment or the part of code of the executable instruction of the step that one or more is used to realize specific logical function or process; And the scope of preferred implementation of the present invention comprises other realization; Wherein can be not according to order shown or that discuss; Comprise according to related function and to carry out function by the mode of basic while or by opposite order, this should be understood by the embodiments of the invention person of ordinary skill in the field.
In flow chart the expression or in this logic of otherwise describing and/or step; For example; Can be considered to be used to realize the sequencing tabulation of the executable instruction of logic function; May be embodied in any computer-readable medium; Use for instruction execution system, device or equipment (like computer-based system, comprise that system or other of processor can be from the systems of instruction execution system, device or equipment instruction fetch and execution command), or combine these instruction execution systems, device or equipment and use.With regard to this specification, " computer-readable medium " can be anyly can comprise, storage, communication, propagation or transmission procedure are for instruction execution system, device or equipment or combine these instruction execution systems, device or equipment and the device that uses.The example more specifically of computer-readable medium (non-exhaustive list) comprises following: the electrical connection section (electronic installation) with one or more wirings; Portable computer diskette box (magnetic device); Random-access memory (ram), read-only memory (ROM) can be wiped and can edit read-only memory (EPROM or flash memory); Fiber device, and portable optic disk read-only memory (CDROM).In addition; Computer-readable medium even can be paper or other the suitable media that to print said program above that; Because can be for example through paper or other media are carried out optical scanner; Then edit, decipher or handle to obtain said program with other suitable methods in case of necessity with the electronics mode, then it is stored in the computer storage.
Should be appreciated that each several part of the present invention can use hardware, software, firmware or their combination to realize.In the above-described embodiment, a plurality of steps or method can realize with being stored in the memory and by software or firmware that suitable instruction execution system is carried out.For example; If realize with hardware; The same in another embodiment, each in the available following technology well known in the art or their combination realize: have the discrete logic that is used for data-signal is realized the logic gates of logic function, have the application-specific integrated circuit (ASIC) of suitable combinational logic gate circuit; Programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that and realize that all or part of step that the foregoing description method is carried is to instruct relevant hardware to accomplish through program; Described program can be stored in a kind of computer-readable recording medium; This program comprises one of step or its combination of method embodiment when carrying out.
In addition, each functional unit in each embodiment of the present invention can be integrated in the processing module, also can be that the independent physics in each unit exists, and also can be integrated in the module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, also can adopt the form of software function module to realize.If said integrated module realizes with the form of software function module and during as independently production marketing or use, also can be stored in the computer read/write memory medium.
The above-mentioned storage medium of mentioning can be a read-only memory, disk or CD etc.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means the concrete characteristic, structure, material or the characteristics that combine this embodiment or example to describe and is contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete characteristic, structure, material or the characteristics of description can combine with suitable manner in any one or more embodiment or example.
Although illustrated and described embodiments of the invention; Those having ordinary skill in the art will appreciate that: under the situation that does not break away from principle of the present invention and aim, can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is claim and be equal to and limit.
Claims (8)
1. one-dimensional metal/semiconductor nano heterojunction transistor is characterized in that, comprising:
Substrate, the upper surface of said substrate is formed with oxide layer;
First electrode pair, said first electrode pair is arranged on the said oxide layer, and said first electrode pair comprises spaced apart first and second electrodes, and wherein said first and second electrodes link to each other through one-dimensional metal/semiconductor heterojunction nanowire;
Second electrode pair; Said second electrode pair is arranged on the said oxide layer and with said first electrode pair and becomes predetermined angular; Said second electrode pair comprises spaced apart third and fourth electrode, and wherein said third and fourth electrode links to each other through the one-dimensional metal nano wire
Wherein, the semiconductor nanowires of the one-dimensional metal/semiconductor heterojunction nanowire between one-dimensional metal nano wire between said second electrode pair and said first electrode pair crosses.
2. a transistorized preparation method as claimed in claim 1 is characterized in that, may further comprise the steps:
Silicon chip is provided, and oxidation is carried out to form oxide layer in the surface of said silicon chip;
Through photoetching method first electrode pair is set on the said oxide layer and on said oxide layer to become the direction of predetermined angular that second electrode pair is set with said first electrode pair; Wherein said first electrode pair comprises spaced apart first and second electrodes, and said second electrode pair comprises spaced apart third and fourth electrode;
Between said first and second electrodes, put into electroplate liquid and said first and second electrodes applied first alternating current of first scheduled time, through electro-deposition with exchange the dielectrophoresis method that combines and between said first and second electrodes, form the one-dimensional metal nano wire that mid portion breaks off;
Put into the suspension that comprises semiconductor nanowires and said first and second electrodes are applied second alternating current of second scheduled time at the middle gap of said one-dimensional metal nano wire; Method through dielectrophoresis is connected semiconductor nanowires with said one-dimensional metal nano wire, the method assembling one dimension heterojunction that promptly utilizes electro-deposition and dielectrophoresis to combine;
Between said third and fourth electrode, put into said electroplate liquid and said third and fourth electrode applied the 3rd alternating current of the 3rd scheduled time, through said electro-deposition with exchange the dielectrophoresis method that combines and between said third and fourth electrode, form another one-dimensional metal nano wire.
3. preparation method according to claim 2 is characterized in that, before the middle gap of said one-dimensional metal nano wire is put into the suspension that comprises semiconductor nanowires, also comprises:
The suspension that will comprise semiconductor nanowires through the excusing from death process for dispersing disperseed 30-90 minute in the ultrasonic cleaning pond.
4. preparation method according to claim 2; It is characterized in that; Between said third and fourth electrode, form after another one-dimensional metal nano wire, the one-dimensional metal that obtains/semiconductor nano heterojunction transistor is cleaned and dries through semiconductor cleaning method.
5. preparation method according to claim 2 is characterized in that, it is that 1～20V, frequency are 10 that said first and second electrodes are applied peak value
3～10
7After first scheduled time of first alternating current of Hz, breaking off the alternating current that is applied to said first and second electrodes through automatic observation circuit is the breaking part of 10nm-10 μ m between said first and second electrodes, to form length.
6. preparation method according to claim 2-utilize the method that alternating current deposits and dielectrophoresis combines to assemble the one dimension heterojunction; It is characterized in that it is that 5～10 seconds peak value is that 1～20V, frequency are 10 that said first and second electrodes were applied for second scheduled time
3～10
7Second alternating current of Hz is to be connected semiconductor nanowires with said one-dimensional metal nano wire.
7. preparation method according to claim 2 is characterized in that, the concentration of the electroplate liquid of between said third and fourth electrode, putting into is 2 * 10
-8Mol/l～2 * 10
-3Mol/l, said the 3rd scheduled time is 4～6 seconds, the peak value of said the 3rd alternating current between 1～20V and frequency 10
3～10
7Between the Hz.
8. according to each described preparation method of claim 2-7, it is characterized in that said first electrode pair and said second electrode pair are Pt/Cr electrode pair or Cr/Au electrode pair.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110359848 CN102420244B (en) | 2011-11-14 | 2011-11-14 | One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110359848 CN102420244B (en) | 2011-11-14 | 2011-11-14 | One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102420244A true CN102420244A (en) | 2012-04-18 |
| CN102420244B CN102420244B (en) | 2013-10-09 |
Family
ID=45944555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110359848 Expired - Fee Related CN102420244B (en) | 2011-11-14 | 2011-11-14 | One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102420244B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564862A (en) * | 2016-07-01 | 2018-01-09 | 清华大学 | The preparation method of nano-heterogeneous structure |
| CN107564917A (en) * | 2016-07-01 | 2018-01-09 | 清华大学 | Nano-heterogeneous structure |
| CN110499489A (en) * | 2019-07-23 | 2019-11-26 | 电子科技大学 | A kind of preparation process of semiconductor/metal heterojunction nano-wire array material |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681975A (en) * | 2002-07-08 | 2005-10-12 | Btg国际有限公司 | Nanostructures and methods for manufacturing the same |
| CN1797723A (en) * | 2004-12-23 | 2006-07-05 | 北京大学 | Method for fabricating transistor of single electron based on Nano carbon tubes |
| CN1953231A (en) * | 2005-10-17 | 2007-04-25 | 中国科学院化学研究所 | An organic field effect transistor and its manufacture method |
| CN102244002A (en) * | 2011-07-14 | 2011-11-16 | 合肥工业大学 | Preparation method of heterojunction with metal/semiconductor nanometer wire crossing structure |
-
2011
- 2011-11-14 CN CN 201110359848 patent/CN102420244B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681975A (en) * | 2002-07-08 | 2005-10-12 | Btg国际有限公司 | Nanostructures and methods for manufacturing the same |
| CN1797723A (en) * | 2004-12-23 | 2006-07-05 | 北京大学 | Method for fabricating transistor of single electron based on Nano carbon tubes |
| CN1953231A (en) * | 2005-10-17 | 2007-04-25 | 中国科学院化学研究所 | An organic field effect transistor and its manufacture method |
| CN102244002A (en) * | 2011-07-14 | 2011-11-16 | 合肥工业大学 | Preparation method of heterojunction with metal/semiconductor nanometer wire crossing structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564862A (en) * | 2016-07-01 | 2018-01-09 | 清华大学 | The preparation method of nano-heterogeneous structure |
| CN107564917A (en) * | 2016-07-01 | 2018-01-09 | 清华大学 | Nano-heterogeneous structure |
| CN107564917B (en) * | 2016-07-01 | 2020-06-09 | 清华大学 | Nano-heterostructure |
| CN107564862B (en) * | 2016-07-01 | 2020-09-25 | 清华大学 | Preparation method of nano heterostructure |
| CN110499489A (en) * | 2019-07-23 | 2019-11-26 | 电子科技大学 | A kind of preparation process of semiconductor/metal heterojunction nano-wire array material |
| CN110499489B (en) * | 2019-07-23 | 2021-06-01 | 电子科技大学 | Preparation process of semiconductor/metal heterojunction nanowire array material |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102420244B (en) | 2013-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Martinez et al. | Silicon nanowire transistors with a channel width of 4 nm fabricated by atomic force microscope nanolithography | |
| Jiang et al. | Kinked p–n junction nanowire probes for high spatial resolution sensing and intracellular recording | |
| Long et al. | Recent advances in large-scale assembly of semiconducting inorganic nanowires and nanofibers for electronics, sensors and photovoltaics | |
| Lin et al. | The impact of nanocontact on nanowire based nanoelectronics | |
| Dong et al. | Dielectrophoretically controlled fabrication of single-crystal nickel silicide nanowire interconnects | |
| Cepak et al. | Chemical strategies for template syntheses of composite micro-and nanostructures | |
| CN101667611B (en) | Preparation method of solar micro battery on basis of directional carbon nano tube | |
| US7964143B2 (en) | Nanotube device and method of fabrication | |
| Zhang et al. | In situ fabrication of inorganic nanowire arrays grown from and aligned on metal substrates | |
| EP3028993A1 (en) | A deposit and electrical devices comprising the same | |
| JP2007258172A (en) | Electron emitting element using carbon nanotube and its manufacturing method | |
| Forticaux et al. | Three-dimensional mesoscale heterostructures of ZnO nanowire arrays epitaxially grown on CuGaO2 nanoplates as individual diodes | |
| CN102420244B (en) | One-dimensional metal/semiconductor nanometer heterojunction transistor and preparation method thereof | |
| JP2006247832A (en) | Method for assembling carbon nano-tube and carbon nano-tube element | |
| CN104867876B (en) | The preparation method of thin film transistor (TFT) array | |
| Javey | The 2008 Kavli prize in nanoscience: carbon nanotubes | |
| Ma et al. | Cylindrical line-feeding growth of free-standing silicon nanohelices as elastic springs and resonators | |
| CN101497428A (en) | Method for arranging nano-wire array using electrostatic filature | |
| Toko et al. | Vertically aligned Ge nanowires on flexible plastic films synthesized by (111)-oriented Ge seeded vapor–liquid–solid growth | |
| CN105493256A (en) | Thin film transistor, preparation method and display apparatus | |
| CN103586590A (en) | Nanometer welding method based on joule heat | |
| CN101870454B (en) | Assembly method for conductive polymer crossed nanowire device | |
| Bradley et al. | Contactless tip‐selective electrodeposition of palladium onto carbon nanotubes and nanofibers | |
| Umeta et al. | Stable Resistance Switching in Lu3N@ C80 Nanowires Promoted by the Endohedral Effect: Implications for Single-Fullerene Motion Resistance Switching | |
| Chen et al. | Electronic logic gates from three-segment nanowires featuring two p–n heterojunctions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131009 Termination date: 20141114 |
|
| EXPY | Termination of patent right or utility model |