CN102412841A - High-precision band-limited signal digital-to-analog converter and using method thereof - Google Patents

High-precision band-limited signal digital-to-analog converter and using method thereof Download PDF

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Publication number
CN102412841A
CN102412841A CN2011104246204A CN201110424620A CN102412841A CN 102412841 A CN102412841 A CN 102412841A CN 2011104246204 A CN2011104246204 A CN 2011104246204A CN 201110424620 A CN201110424620 A CN 201110424620A CN 102412841 A CN102412841 A CN 102412841A
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digital
module
analog
gate array
field programmable
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许霄龙
袁浩
危峰
任全利
袁松
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CSIC (WUHAN) LINCOM ELECTRONICS Co Ltd
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Abstract

The invention provides a high-precision band-limited signal digital-to-analog converter and a using method thereof. The convertor comprises a digital signal processor, a field programmable logic gate array, a digital-to-analog conversion module, which are connected successively. The using method comprises the following steps that: firstly, the digital signal processor inputs numeric codes to the field programmable logic gate array; then the field programmable logic gate array improves the sampling rate of the numeric codes through equivalent interpolation and digital filtering, filters out mirror of frequency spectrum of the numeric codes, and finally inputs the numeric codes into the digital-to- analog conversion module for conversion into simulating signals. The high-precision band-limited signal digital-to-analog converter provided by the invention can effectively simplify the design of a mirror-resistant filter and improve the precision of output signals and has relatively strong generality.

Description

A kind of high precision digital-to-analog converter of band-limited signal and method for using thereof
Technical field
The present invention relates to simulation and digital processing field, the method for a kind of high precision digital-to-analog converter of band-limited signal (DAC) generation specifically.
Background technology
Digital-analog convertor spare (DAC) is the interface between digital signal and the analog signal; DAC converts the digital code of input into analog level, then through zero-order holding circuit output, because the zeroth order inhibit signal is stepped; The steep edge of this stairstep signal has been introduced higher frequency component in transfer process; According to nyquist sampling theorem, these frequency components are called as the spectral image in the sampling process, and spectral image appears at the multiple place of sample frequency.Therefore after zero-order holding circuit, must introduce low pass filter; See from frequency domain, low pass filter filters out unwanted spectral image, see from time domain; Low pass filter makes the steep edge smoothed of stairstep signal, this low pass filter anti-mirror filter that is otherwise known as.
Traditional anti-mirror filter mainly adopts Analog Circuit Design; Indexs such as the cut-off frequecy of passband of analog circuit engineer through signal, passband gain, transition band width are selected suitable low pass filter model, adopt active device (like operational amplifier), passive device (like resistance, electric capacity) to build analogue filter circuit.Because analog filter receives many-sided influence such as hardware cost, PCB (printed circuit board (PCB)) the plate width of cloth, temperature drift, components and parts precision; Often can only be between performance and other factors balance; Can't with the precision of filter do very high, it is optimum that performance also often can't reach.
The sampling rate of universal DA C has reached very high level at present; Sample rate such as 16bit precision DAC can surpass 1MSPS easily; How to simplify Design of Simulating Circuits with the method for numeral; Improve the precision that DAC generates signal, on the DAC of band-limited signal generation method, be of great immediate significance.
Summary of the invention
High precision digital-to-analog converter (DAC) the generation method that the purpose of this invention is to provide a kind of band-limited signal; The present invention utilizes FPGA that digital signal is waited value interpolation; Increase the interval between the spectral image through increasing sample frequency, and carry out digital filtering, can effectively simplify the design of the anti-mirror filter of simulation through FPGA; Improve the precision of output signal, have stronger versatility.
A kind of digital to analog converter of band-limited signal comprises digital signal processor, field programmable gate array, D/A converter module, and they link to each other successively, and are connected to power module.
Described digital to analog converter, the output of D/A converter module also are connected to the anti-mirror filter of simulation.
Described digital to analog converter; Power module comprises digital signal part power supply and analog signal part power supply; Digital signal processor, field programmable gate array all link to each other with digital signal part power supply, and D/A converter module, the anti-mirror filter of simulation all link to each other with analog signal part power supply; Also be connected to the synchronous DRAM and first flash memory on the digital signal processor, also be connected to second flash memory on the field programmable gate array, also be connected to photoisolator between field programmable gate array, the D/A converter module.
Described digital to analog converter is provided with digital interpolation module and digital filtering module in the field programmable gate array, the output of digital interpolation module is connected to the input of digital filtering module.
Described digital to analog converter, the digital interpolation module links to each other with digital signal processor through the digital signal processor interface module, and digital filtering module links to each other with D/A converter module through the digital-to-analogue conversion interface module.
Described digital to analog converter is provided with the reception cache module between digital signal processor interface module and the digital interpolation module, is provided with the transmission cache module between digital filtering module and the D/A converter module.
Described digital to analog converter, digital filtering module adopts has limit for length's unit impulse response filter.
A kind of method for using of high precision digital-to-analog converter of band-limited signal comprises: digital signal processor is imported field programmable gate array with digital code; Field programmable gate array improves the sample rate of digital code through waiting value interpolation and digital filtering; And, be input to D/A converter module then and convert analog signal to the spectral image filtering of digital code.
Described method for using specifically may further comprise the steps:
S1) according to the characteristic of signal and the requirement of filter, obtain the coefficient on each rank of digital filter transfer function, and this coefficient is write as parameter in the FILTER IP kernel of field programmable gate array, generate digital filtering module;
S2) digital code in the digital signal processor is carried out buffer memory through its external bus, digital signal processor interface module entering reception cache module successively;
S3) the digital interpolation module is collected the data that receive in the cache module, and carries out inserting in the equivalence;
S4) digital code after inserting in gets into the digital filtering module that step S1 generates, and carries out Filtering Processing;
S5) filtered digital code deposits the buffer memory that sends before cache module sends in;
S6) digital code behind the buffer memory gets into D/A converter module through the digital-to-analogue conversion interface module, and D/A converter module is transformed into analog level with digital code, and carries out the zeroth order maintenance and handle;
S7) the stepped zeroth order inhibit signal of the anti-mirror filter logarithmic mode modular converter output of simulation carries out smoothing processing, and back output signal disposes.
Described method for using, the method for value interpolations such as step S3 is: establishing the sampling frequency is L, when first numerical value of raw digital code is A 0The time, the digital interpolation module is inserted (L-1) individual A continuously 0, when second numerical value of raw digital code is A 1The time, the digital interpolation module is inserted (L-1) individual A continuously 1, all raw digital code are all carried out the identical value interpolation that waits operate.
Beneficial effect of the present invention: the present invention utilizes FPGA that raw digital code is waited value interpolation and digital filtering; The outside anti-mirror filter of simulation only need be accomplished the level and smooth of the steep edge of ladder, has greatly simplified the design of the anti-mirror filter of simulation in the DAC generation method of traditional band-limited signal; Factors such as the device error of being brought by analog circuit originally, temperature drift significantly reduce, and the stability of a system and precision are further improved.The mode that value interpolations such as employing of the present invention raising sample frequency and digital filtering combine, because the digital filter exponent number of FPGA inside is high, performance is strong, the band-limited signal precision that DAC is generated is higher, and has flexible, configurable characteristics.
Description of drawings
Fig. 1 is a main functional modules sketch map of the present invention.
Fig. 2 is a signal conversion process sketch map of the present invention.
Fig. 3 is a FPGA Digital Signal Processing flow chart of the present invention.
Embodiment
This programme hardware platform is realized the value interpolation that waits of digital signal based on FPGA (field programmable gate array); And in interior slotting back with digital filter with unwanted spectral image filtering; The anti-mirror filter of last simulation only is used for realizing the level and smooth of the steep edge of ladder that its main functional modules comprises: digital signal processor (DSP) external bus interface module, reception cache module, digital interpolation module, digital filtering module, transmission cache module, DAC interface module, DAC modular converter, analog filter block.
Wherein, The external bus of digital signal processor (DSP) links to each other with inner external bus interface module and the reception cache module of FPGA respectively; Inner transmission cache module and the DAC interface module of FPGA links to each other with the DAC modular converter of outside, and the DAC modular converter then links to each other with the analog filter block of rear end.Calculate the parameter of digital filter through the MATLAB instrument, that utilizes raw digital code that FPGA realizes DSP is sent waits operations such as value interpolation, digital filtering, and the digital code after will handling sends to outside DAC and generates corresponding band-limited signal.
Its main functional modules constitutes as shown in Figure 1.
At first, according to the characteristic of signal and the requirement of filter, like the highest frequency f of band-limited signal C, the actual samples frequency f after the interpolation S, the cut-off frequecy of passband of filter, passband gain, transition band width etc. through MATLAB instrument Digital Filter Design, are obtained the coefficient on each rank of digital filter, and this coefficient are write in the FILTER IP kernel of FPGA as parameter.
Then, realize the external bus of DSP and the interface module of FPGA inner buffer, DSP can write FPGA inside through the digital code of DAC output; Inner at FPGA, according to the crude sampling frequency f O, in conjunction with the maximum sample frequency of the real work of DAC, confirm the number of the value interpolations such as digital code of input, if the number of interpolate value is (L-1), actual samples frequency f then S=L * f ODigital code after interior the inserting is carried out digital filtering through the inner FILTER IP kernel of FPGA, will appear at f SThe spectral image filtering at multiple place; Send into outside DAC modular converter through interpolation, filtered digital signal through the DAC interface module.
At last, the DAC modular converter converts digital signal into analog signal output, because zero-order holding circuit output is stairstep signal, also need carry out smoothly through simulation low-pass filter.
In sum, the present invention mainly is divided into three parts, and first is the Digital Filter Design that requires according to the characteristic of signal and filter, and writes each rank coefficient of filter in FILTER IP (filter intellectual property) nuclear of FPGA as parameter; Second portion is the exchanges data of DSP and FPGA, and FPGA is transferred to DAC with digital code after initial data is waited value interpolation, filtering; Third part is the output that DAC realizes analog signal, and through the level and smooth stairstep signal of analog filter.Below combine chart to be elaborated to the embodiment of this three part.
Under normal conditions, the digital code of sending through DSP has comprised the complete information of a band-limited signal, comprises highest frequency f C, the crude sampling frequency f O, the relation between the highest frequency of crude sampling frequency and band-limited signal must satisfy nyquist sampling theorem, i.e. f O>=2 * f C, only in this way, DAC could generate the wave beam that meets this band-limited signal characteristic, but in engineering practice, the crude sampling frequency often is higher than Nyquist sampling frequency, general f O>=5 * f C
First is according to the highest frequency f of band-limited signal C, the actual samples frequency f after the interpolation SReach the Filter Design requirement, confirm the cut-off frequecy of passband f of digital filter P, passband gain A VP, major parameter such as transition band width; Adopt the MATLAB instrument to calculate then; Call " kaiserord window " function among the MATLAB; Parameters such as input cut-off frequency, stop-band frequency, bandpass flatness, stopband attenuation degree, its result of calculation is one group of numerical matrix, each rank coefficient that this numerical matrix is exactly a digital filter.Utilize the FPGA of Xilinx company to design and develop external member ISE13.0; Call IP LogiCORE FIR Compiler v5.0 instrument; Each rank coefficient that MATLAB is calculated writes in this instrument; Parameters such as port number, clock, data type are accomplished in configuration simultaneously, can realize the digital filter that meets design requirement, and use as the digital filtering module of FPGA inside.
Second portion; The dsp interface module is through carrying out operations such as synchronised clock latchs, address decoding, the management that resets to signals such as the data on the outside DSP external bus of FPGA, address, read/write; Realize digital code and the interface between the reception cache module among the FPGA (sequence number is 1～8 signal in the table 1, is the external hardware interface of this module) among the DSP; Receiving cache module utilizes the FPGA of Xilinx company to design and develop external member ISE13.0; Call FIFO Generator v5.2 instrument; Width, the degree of depth of inputoutput data accomplished in configuration, and parameters such as working method can realize the caching function of digital code that FPGA receives; The triggering degree of depth of buffer memory can be provided with by DSP, makes FPGA can not take the external bus bandwidth of DSP for a long time; The digital interpolation module is used for the data that receive cache module are waited value interpolation, when first numerical value of initial data is A 0The time, the digital interpolation module is then inserted (L-1) individual A continuously 0, when second numerical value of initial data is A 1The time, the digital interpolation module is then inserted (L-1) individual A continuously 1, all initial data are all carried out the identical value interpolation that waits operate, then the sample frequency when initial data is f OThe time, be f through the data actual samples frequency after the interpolation S=L * f OOwing to increased sample frequency, the frequency spectrum of original data mirror image is also by f OThe multiple place move f SThe multiple place, increased the interval between spectral image and the signal itself; The digital filtering module that digital code after interior the inserting realizes in describing through first carries out digital filtering, and filtered digital code deposits in the transmission cache module; Sending cache module utilizes the FPGA of Xilinx company to design and develop external member ISE13.0 equally; Call FIFOGenerator v5.2 instrument; Width, the degree of depth of inputoutput data accomplished in configuration, and parameters such as working method realize the caching function of data code that FPGA sends; The triggering degree of depth of buffer memory can be provided with by DSP, but must guarantee that the band-limited signal that the DAC modular converter generates is continuous; The DAC interface module is controlled the outside DAC modular converter of FPGA; Make it can be according to normal sequential working; Accomplish the transmission of sending data code in the cache module simultaneously; If the outside is serial data conversion hysteria DAC, also must realize the translation function (sequence number is 10～17 signal in the table 1, is the external hardware interface of this module) of parallel data-serial data.
Third part, DAC modular converter have realized the conversion of digital code to analog level, and the complete information of the band-limited signal that digital code comprised is no longer by the crude sampling frequency f at this moment OEmbody, but by the actual samples frequency f after the interpolation SEmbody and since digital filter filtering unnecessary spectral image, analog filter block only needs the stepped zeroth order inhibit signal of level and smooth DAC modular converter output to get final product, a simple RC low pass filter can be accomplished this task.
The present invention in the specific implementation, the model of each chip is:
Digital signal processor (DSP): Analog Devices company, ADSP-TS101;
Field programmable gate array (FPGA): Xilinx company, XC5VLX30;
Digital-analog convertor (DAC): Analog Devices company, AD5542;
SDRAM memory (synchronous DRAM): Micron company, MT48LC32M16;
FLASH (flash memory) memory 1 (being said first flash memory of summary of the invention): AMD, AM29LV065D;
FLASH (flash memory) memory 2 (being said second flash memory of summary of the invention): Xilinx company, XCF08PV;
Photoisolator: Analog Devices company, ADUM1400.
The SDRAM memory directly is connected with the data/address bus of DSP, the SDRAM Controller (controller) that is carried by the DSP inside control that conducts interviews, the metadata cache when being used to realize dsp operation; FLASH memory 1 directly is connected with the data/address bus of DSP, and by DSP it is conducted interviews, the program when loading code when being used to store the DSP startup and operation; FLASH memory 2 is connected with the loading interface of FPGA, is used for the good logical code of store compiled, and FPGA must at first read this logical code when powering on, could press the function operation of appointment; One end of photoisolator is connected with FPGA, and the other end is connected with the DAC modular converter, is used to realize digital signal part and analog signal electrical isolation partly, and the analog signal that DAC is exported is not vulnerable to the interference of digital signal, improves the output quality of signals.
Table 1FPGA IP kernel external interface table
Sequence number Signal Type Functional description The clock synchronization relation
1 reset_i in Reset signal, high level is effective; Asynchronous reset
2 sys_clk in The external bus interface clock; sys_clk
3 data_i[31:0] in The input of external bus data; sys_clk
4 data_o[31:0] out The output of external bus data; sys_clk
5 addr_i[5:0] in The input of external bus address; sys_clk
6 wrn in Write and enable, low level is effective; sys_clk
7 rdn in Read to enable, low level is effective; sys_clk
8 cen in Module enables, and low level is effective; sys_clk
9 fir_clk in The work clock of fir filter segment logic module; fir_clk
10 da_clk in The work clock of DA control logic assembly; da_clk
11 da_en in Da work enables, and high level is effective; sys_clk
12 da_out_dis out DA exports switch; sys_clk
13 dac_irqn out Interrupt output, low level is effective; sys_clk
14 da_sck out The SPI clock connects the SCK pin (Pin8) of AD5542; With daclk frequency together
15 da_din out The SPI data connect the DIN pin (Pin10) of AD5542; da_clk
16 da_cs out The SPI sheet selects, and connects the CS pin (Pin7) of AD5542; da_clk
17 da_ldacn out DA changes startup, connects the LDAC pin (Pin11) of AD5542; da_clk
18 test[1:0] out Test signal;
Table 2FPGA address space and operating function table
Figure BDA0000121427430000061

Claims (10)

1. the digital to analog converter of a band-limited signal is characterized in that: comprise digital signal processor, field programmable gate array, D/A converter module, they link to each other successively, and are connected to power module.
2. digital to analog converter according to claim 1 is characterized in that: the output of D/A converter module also is connected to the anti-mirror filter of simulation.
3. digital to analog converter according to claim 2; It is characterized in that: power module comprises digital signal part power supply and analog signal part power supply; Digital signal processor, field programmable gate array all link to each other with digital signal part power supply, and D/A converter module, the anti-mirror filter of simulation all link to each other with analog signal part power supply; Also be connected to the synchronous DRAM and first flash memory on the digital signal processor, also be connected to second flash memory on the field programmable gate array, also be connected to photoisolator between field programmable gate array, the D/A converter module.
4. digital to analog converter according to claim 1 is characterized in that: be provided with digital interpolation module and digital filtering module in the field programmable gate array, the output of digital interpolation module is connected to the input of digital filtering module.
5. digital to analog converter according to claim 4 is characterized in that: the digital interpolation module links to each other with digital signal processor through the digital signal processor interface module, and digital filtering module links to each other with D/A converter module through the digital-to-analogue conversion interface module.
6. digital to analog converter according to claim 5 is characterized in that: be provided with the reception cache module between digital signal processor interface module and the digital interpolation module, be provided with the transmission cache module between digital filtering module and the D/A converter module.
7. digital to analog converter according to claim 4 is characterized in that: digital filtering module adopts has limit for length's unit impulse response filter.
8. the method for using of the high precision digital-to-analog converter of a band-limited signal; It is characterized in that comprising: digital signal processor is imported field programmable gate array with digital code; Field programmable gate array improves the sample rate of digital code through waiting value interpolation and digital filtering; And, be input to D/A converter module then and convert analog signal to the spectral image filtering of digital code.
9. method for using according to claim 8 is characterized in that, specifically may further comprise the steps:
S1) according to the characteristic of signal and the requirement of filter, obtain the coefficient on each rank of digital filter transfer function, and this coefficient is write as parameter in the FILTER IP kernel of field programmable gate array, generate digital filtering module;
S2) digital code in the digital signal processor is carried out buffer memory through its external bus, digital signal processor interface module entering reception cache module successively;
S3) the digital interpolation module is collected the data that receive in the cache module, and carries out inserting in the equivalence;
S4) digital code after inserting in gets into the digital filtering module that step S1 generates, and carries out Filtering Processing;
S5) filtered digital code deposits the buffer memory that sends before cache module sends in;
S6) digital code behind the buffer memory gets into D/A converter module through the digital-to-analogue conversion interface module, and D/A converter module is transformed into analog level with digital code, and carries out the zeroth order maintenance and handle;
S7) the stepped zeroth order inhibit signal of the anti-mirror filter logarithmic mode modular converter output of simulation carries out smoothing processing, and back output signal disposes.
10. method for using according to claim 9 is characterized in that the method for value interpolations such as step S3 is: establishing the sampling frequency is L, when first numerical value of raw digital code is A 0The time, the digital interpolation module is inserted (L-1) individual A continuously 0, when second numerical value of raw digital code is A 1The time, the digital interpolation module is inserted (L-1) individual A continuously 1, all raw digital code are all carried out the identical value interpolation that waits operate.
CN2011104246204A 2011-12-16 2011-12-16 High-precision band-limited signal digital-to-analog converter and using method thereof Pending CN102412841A (en)

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CN103543334A (en) * 2013-10-24 2014-01-29 北京理工大学 Phase difference measurement device and method based on FFT

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Application publication date: 20120411