CN102412702B - load point assembly - Google Patents
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- CN102412702B CN102412702B CN201110354556.7A CN201110354556A CN102412702B CN 102412702 B CN102412702 B CN 102412702B CN 201110354556 A CN201110354556 A CN 201110354556A CN 102412702 B CN102412702 B CN 102412702B
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Abstract
The invention discloses a combined circuit and an electronic element. The invention discloses a load point component. The load point component comprises an inductor, at least one input capacitor and at least one switching element. The inductor is provided with a first surface and a second surface which is opposite to the first surface; a plurality of conductors are arranged on the first surface and the second surface; the plurality of conductors positioned on the first surface of the inductor serve as an output end of the load point component; the at least one switching element is stacked on the inductor and is electrically connected with the inductor through the plurality of conductors on the second surface of the inductor, wherein the at least one input capacitor and the at least one switching element are electrically connected to a carrier through the plurality of conductors; and the carrier is used for carrying the load point component.
Description
The application be applicant on January 7th, 2008 submit to, the divisional application of application for a patent for invention that application number is " 200810003217.2 ", that denomination of invention is " combined circuit and electronic component ".
Technical field
The present invention is about a kind of POL assembly and apply the combined circuit of this POL assembly, more specifically, about a kind of reduce overall dimensions with promote overall power supply power density POL assembly and apply the combined circuit of this POL assembly.
Background technology
General electrical equipment adopts AC power, and this AC power is converted to after array DC power supply via DC-AC converter (AC to DC converter), just can supply with each electronic component of electrical equipment inside, to meet its different electricity needs.But, while conversion due to power supply, having part loss, the conversion efficiency that converts the output of many group DC power supply to is not high.Therefore, first convert one group of DC power supply to if make into, then convert this group DC power supply to array required DC power supply, can significantly raise the efficiency.Except this, portable electronic product uses DC power supply (that is battery) to supply with electric power to internal circuit.Similarly, for coordinating the different direct voltage demand of internal circuit, just needing the voltage transitions that uses direct current transducer (DC to DC converter) that battery is provided is array direct voltage, and direct current transducer comprises step-down (Buck) transducer, (Boost) transducer that boosts, buck (Buck-Boost) transducer.
Along with developing rapidly of power technology, electric pressure converter is also more and more higher to the requirement of power density and transducer size.The method that improves power density has a variety of, conventional method is the power density that the characteristic by changing power sourced electric aspect improves power supply, for example, improve the operating frequency of transducer and for example, improve power density significantly to reduce the size of some passive devices (inductance).But in fact affect the factor that the power density of direct current transducer and the factor of efficiency also comprise a lot of mechanisms aspect, such as the size of each element itself and structural design of whole electric pressure converter etc.Below, as an example of the POL in the direct current transducer of electric pressure converter (Point Of Load, POL) direct current transducer example, this problem is described.
Fig. 1 is the circuit diagram of a POL direct current transducer, and it is a step-down controller (Buck converter).This POL direct current transducer 1 comprises an inductance 11, two switch elements 12,15 (such as mos field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET)), an output capacitance 13 and a control chip 14.Control chip 14 is by receiving an output feedback signal and relevant voltage adjustment control signal Vadj, with the running of control load point direct current transducer 1.
Fig. 2 A and Fig. 2 B are respectively overlooking and upward view of a kind of traditional POL direct current transducer.This traditional POL direct current transducer 2 encapsulates with a kind of combined circuit, and the pin of its input and output is traditional plug-in mounting pin (Through hole pin).As shown in the figure, POL direct current transducer 2 comprises a control chip 21, a circuit board 22, four input and output electric capacity 23, several plug-in mounting pin 24, a magnetic element (being inductance in this example) 25 and two switch elements 27.Control chip 21 is arranged at carrier 22 with output capacitance 23 and (is generally a printed circuit board (PCB) (Printed Circuit Board, PCB) one side), is provided with magnetic element 25 and two switch elements 27 at the another side of circuit board 22.
POL direct current transducer 2 is by several plug-in mounting pin 24 plug-in mounting to main circuit boards (scheming not shown).But plug-in mounting pin 24 can occupy a part of area on circuit board 22 surfaces; In addition, pin 24 has supporting role, therefore circuit board 22 need to have certain thickness, has consequently increased the volume of POL direct current transducer 2, more reduces its overall power density.
Overlooking with upward view as Fig. 3 A and Fig. 3 B disclose of another kind of conventional negative loading point direct current transducer.This kind of traditional POL direct current transducer 3 encapsulates with another kind of combined circuit, and the pin of its input and output is waveform pin (Wave pin), and pin is attached to the surface of circuit board.As shown in the figure, POL direct current transducer 3 comprises three electric capacity 31 (comprising output capacitance and/or input capacitance), a switch element 32, multiple waveform pin 33, a carrier 34, a magnetic element 35 and a control chip 36.Electric capacity 31, switch element 32 and magnetic element 35 are arranged at the one side of carrier 34 (being generally a printed circuit board (PCB)), are provided with control chip 36 in the other one side of carrier 34.POL direct current transducer 3 sees through waveform pin 33 and is connected with main circuit board (scheming not shown).
But this waveform pin 33 is except meeting occupies the certain space of circuit board 34, waveform pin 33 itself has certain height, and these all can increase the volume of POL direct current transducer 3, and reduces its power density.
In sum, in existing packaged type, POL direct current transducer is all limited to pin, makes that overall volume is large and power density is lower.Hereat, for solving these problems, propose a kind of novel combined circuit, in order to promote the power density of electronic installation (especially electric pressure converter), and dwindle overall dimensions, just field is needed badly for this reason.
Summary of the invention
An object of the present invention provides a kind of POL assembly.Comprise an inductance, at least one input capacitance and at least one switch element for reaching this object POL assembly of the present invention.Inductance has a first surface and a second surface relative with first surface, has a plurality of conductors on first surface and second surface, is positioned at a plurality of conductors of first surface of inductance as an output of POL assembly; At least one switch element stacks on inductance, and is electrically connected by a plurality of conductors on the second surface of inductance and inductance.Wherein, at least one input capacitance and at least one switch element are electrically connected to a carrier by a plurality of conductors, and carrier is put assembly in order to carry load.
After the execution mode of consulting accompanying drawing and describe subsequently, persond having ordinary knowledge in the technical field of the present invention just can understand object of the present invention, and technological means of the present invention and enforcement aspect.
Brief description of the drawings
Fig. 1 is the circuit diagram of conventional negative loading point module power supply;
Fig. 2 A is the vertical view that tradition adopts the POL direct current transducer of plug-in mounting pin;
Fig. 2 B is the upward view that tradition adopts the POL direct current transducer of plug-in mounting pin;
Fig. 3 A is the vertical view that tradition adopts the POL direct current transducer of waveform pin;
Fig. 3 B is the upward view that tradition adopts the POL direct current transducer of waveform pin;
Fig. 4 A is according in the direct current transducer of first embodiment of the invention, is coated with the vertical view of the first electronic component of the first conductor layer;
Fig. 4 B is according in the direct current transducer of first embodiment of the invention, is coated with the upward view of the first electronic component of the first conductor layer;
Fig. 4 C is according in the direct current transducer of first embodiment of the invention, is coated with another vertical view of the first electronic component of the first conductor layer;
Fig. 4 D is according in the direct current transducer of first embodiment of the invention, is coated with another upward view of the first electronic component of the first conductor layer;
Fig. 5 A to Fig. 5 E is according in the direct current transducer of first embodiment of the invention, and each step of coated the first electronic component of the first conductor layer is made result;
Fig. 6 A is the direct current transducer upward view according to first embodiment of the invention;
Fig. 6 B is the direct current transducer vertical view according to first embodiment of the invention;
Fig. 6 C is the combined circuit vertical view of the direct current transducer that comprises first embodiment of the invention;
Fig. 7 A is according in the direct current transducer of second embodiment of the invention, the vertical view that the second electronic component is connected with the first conductor layer;
Fig. 7 B is by according to the vertical view of the direct current transducer of second embodiment of the invention;
Fig. 8 A is according in the direct current transducer of sixth embodiment of the invention, is coated with the vertical view of the second electronic component of the first conductor layer;
Fig. 8 B is according to the vertical view of the direct current transducer of sixth embodiment of the invention;
Fig. 9 A is according in the direct current transducer of seventh embodiment of the invention, is coated with the vertical view of the quadrielectron element of the first conductor layer;
Fig. 9 B is according to the vertical view of the direct current transducer of seventh embodiment of the invention;
Figure 10 is according to the vertical view of the direct current transducer of eighth embodiment of the invention;
Figure 11 A is the POL direct current transducer vertical view according to third embodiment of the invention;
Figure 11 B is the POL direct current transducer vertical view upward view according to third embodiment of the invention;
Figure 11 C is according to the schematic diagram of common burning magnetic material substrate, the first conductor layer and the conductor of third embodiment of the invention;
Figure 11 D removes the schematic diagram after ground floor magnetic material base material according to the common burning magnetic material substrate of third embodiment of the invention;
Figure 11 E is the internal structure perspective view of Figure 11 C;
Figure 11 F is other internal layer circuit schematic diagrames except ground floor, the second layer and last one deck according to the common burning magnetic material substrate of third embodiment of the invention;
Figure 11 G is according to last sandwich circuit schematic diagram of the common burning magnetic material substrate of third embodiment of the invention;
Figure 12 A is the POL direct current transducer vertical view according to fourth embodiment of the invention;
Figure 12 B is the POL direct current transducer vertical view upward view according to fourth embodiment of the invention;
Figure 12 C is according to the schematic diagram of the magnetic material substrate of fourth embodiment of the invention, the first conductor layer and conductor;
Figure 12 D is the internal structure perspective view of Figure 12 C;
Figure 13 A is the POL direct current transducer vertical view according to fifth embodiment of the invention;
Figure 13 B is the POL direct current transducer vertical view upward view according to fifth embodiment of the invention;
Figure 13 C is according to the schematic diagram of the magnetic material substrate of fifth embodiment of the invention, the first conductor layer, insulating barrier and conductor;
Figure 13 D is the end view of Figure 13 C;
Figure 13 E is according to the schematic diagram of the magnetic material substrate that does not cover insulating barrier of fifth embodiment of the invention;
Figure 13 F is the internal structure perspective view of Figure 13 E;
Figure 14 A is the vertical view of the inductance made with ferrocart core pressing;
Figure 14 B is the upward view of the inductance made with ferrocart core pressing;
Figure 14 C is the schematic diagram of inductance coil pin; And
Figure 14 D is the structural representation of inductance interior loop.
Embodiment
For effectively promoting the power density of electronic installation (especially electric pressure converter), and dwindle overall dimensions, the present invention proposes a kind of Novel pin design, is widely used at present common multiple electronic installation.Refer to shown in Fig. 4 A, 4C and Fig. 4 B, 4D, it shows respectively upward view and the vertical view of the inductive element 62 in first embodiment of the invention.More specifically, inductive element 62 can be an inductance, and in the time of practical application, inductive element 62 can be and burns altogether magnetic material inductance or a coiling laminated type inductance.Should be noted that, be only the use of explanation in the inductive element 62 of the present embodiment, in fact, can apply the disclosed technology of the present invention in general electronic component main body, such as field-effect transistor etc.
One of feature of the present invention is in coated one first conductor layer 61 of outer surface of inductive element 62, the first conductor layer 61 has a bonding conductor 40 and a pin conductor 40 ', a wherein first surface of bonding conductor 40 coated inductive element 62 outer surfaces, pin conductor 40 ' is a second surface of coated inductive element 62 outer surfaces, pin conductor 40 ' is the pin of inductive element 62, the pin of for example inductance.In the time that application the present invention is in other electronic component main bodys, for example, while being applied to field-effect transistor, this pin can be grid, source electrode and the drain electrode etc. of field-effect transistor.Inductive element 62 is connected with external circuitry by pin conductor 40 ' itself.In the present embodiment, several regions such as a part of side that first surface comprises inductive element 62 outer surfaces, a part of end face and a part of bottom surface; Second surface comprises several regions such as the end face of other a part of sides of inductive element 62 outer surfaces and other parts, wherein in 4B figure, surface is upward defined as the end face of inductive element 62, and in Fig. 4 A, surface upward is defined as the bottom surface of inductive element 62.
Aforementioned first surface and second surface are contained aspect that the scope of inductive element 62 outer surfaces and relevant drawings show only for illustrating, not, in order to limit the present invention, the area that in fact first surface and second surface are contained can be adjusted it according to actual demand.In addition, what must emphasize is, isolation mutually between at least a portion and pin conductor 40 ' in bonding conductor 40 on inductive element 62 outer surfaces of the present embodiment, that is at least a portion of bonding conductor 40 and pin conductor 40 ' there is no direct entity and electric connection between the two on outer surface.More specifically, inductive element 62 is only in the time being connected with other electron component or circuit board, and its bonding conductor 40 begins to have part indirectly to see through other electron component or circuit board and pin conductor 40 ' is electrically connected.Implement in aspect in other, bonding conductor 40 on inductive element 62 outer surfaces, also can all and between pin conductor 40 ' mutually isolate, that is all bonding conductor 40 all there is no direct entity and electric connection between the two with pin conductor 40 ' on outer surface.More specifically, inductive element 62 is only in the time being connected with other electron component or circuit board, and its bonding conductor 40 all indirectly sees through other electron component or circuit board and pin conductor 40 ' is electrically connected.
Please refer to Fig. 4 A, Fig. 4 B, Fig. 4 C and Fig. 4 D.In the present embodiment, pin conductor 40 ' has two pins 41,45, be arranged at the two ends of inductive element 62 outer surfaces, as the pin of inductive element 62, for example, to be electrically connected inductive element 62 and other arbitrary elements or carrier (circuit board).In addition, bonding conductor 40 can coordinate actual demand, and has different designs, and in the present embodiment, bonding conductor 40 has several different conductive regions 42,43,44,47,48, is coated and is attached at the first surface on inductive element 62 bodies.For example, conductive region 42,43,44 is as power pin, in order to be connected to a field-effect transistor; Conductive region 47,48 is as being signal pins, in order to be connected to a control chip.Wherein there is larger area as the conductive region 43 of power pin, and and spacing between other conductive regions 42,44,47,48 of bonding conductor 40 is less, therefore 42,43,44,47 and 48 of the conductive regions that can make the end face (in 4B figure this face) upward of inductive element 62 almost be connected conductor 40 completely cover.As aforementioned, due to isolation mutually between bonding conductor 40 at least a portion on inductive element 62 outer surfaces and pin conductor 40 ', that is bonding conductor 40 at least a portion and pin conductor 40 ' there is no direct entity and electric connection between the two on inductive element 62 outer surfaces.More specifically, inductive element 62 is only in the time being connected with other electron component or circuit board, and its pin conductor 40 ' begins indirectly to see through other electron component or circuit board with at least part of bonding conductor 40 surfaces and is electrically connected.Therefore, on inductive element 62 outer surfaces, the segment conductor region 42,43,44,47,48 of bonding conductor 40 and the pin 41,45 of pin conductor 40 ' there is no direct electric connection.This large-area pin design not only contributes to essence to increase the area of dissipation of the first electronic component (being inductance) 62, for example, also can effectively promote for the overall heat dispersion of electronic installation (: electric pressure converter) of application inductive element 62.
Typically, in Fig. 4 A and Fig. 4 B, the pin conductor 40 ' of the first conductor layer 61 is to make complete before in bonding conductor 40 formation.Taking aforementioned inductive element 62 be a coiling laminated type inductance 140 as example, inductance 140 and manufacture the schematic flow sheet of pin conductor 40 ' of inductance 140, as shown in Figure 14 A to 14D.Wherein, Figure 14 A and Figure 14 B are respectively inductance vertical view and the upward view that the pressing of common iron powder core institute is made, and Figure 14 C is depicted as the shape before coil pin bending, are the structure of magnetic material part coil shown in Figure 14 D.In detail, this inductance 140 comprises a magnetic material part 141 and an interior metal coil 142, and the two ends of interior metal coil 142 are connected with pin conductor 143 respectively.By coated ferrocart core interior metal coil 142 and carry out pressing, outside just can obtain magnetic material part 141, and the pin conductor 143 at interior metal coil 142 two ends bending is attached at a second surface of inductance 140.
On the other hand, in the present embodiment, the bonding conductor 40 of the first conductor layer 61 mainly can be formed at by two kinds of modes the outer surface of inductive element 62.A kind of method is on the surface of inductive element 62 bodies, directly to form bonding conductor 40, and another kind of method is after complete independently bonding conductor 40, then secures it to the first surface place of inductive element 62 bodies, and the details will be described later.
Wherein, the specific implementation method that forms bonding conductor 40 on inductive element 62 body surfaces comprises the following step: first, on inductive element 62 body surfaces, form layer of conductive material, for example copper, the method that wherein forms electric conducting material comprises with chemical vapour deposition (CVD) or physical vaporous deposition, for example: evaporation, sputter (sputtering), or the deposition manufacture process of surface metalation such as spraying electric conducting material etc. is formed at a conductive material layer on inductive element 62 body surfaces.Next, then with exposure, developing manufacture process, patterning conductive material layer, to form on the first surface of bonding conductor 40 in inductive element 62 body surfaces.
Secondly,, as Fig. 5 A to Fig. 5 E shows, the another kind of method that forms the first conductor layer 61 on inductive element 62 body surfaces can be reached by following two kinds of modes.First, the framework 51 that comprises the first conductor layer 61 in outside complete independently one, as shown in Figure 5A; Secondly, as shown in Figure 5 B, in the time making inductive element 62, in the mould of inductive element 62, add this framework 51 of having the first conductor layer 61, and in the pressure programming of inductive element 62, this framework 51 is merged to the outer surface that is pressed into inductive element 62; After pressing completes, as shown in Figure 5 C, unnecessary framework 51 is excised, then bend the first remaining conductor layer 61, make the first conductor layer 61 must be coated the first surface of inductive element 62, so can form a coated complete integrated morphology 53.
In the second way, as shown in Figure 5 B, brush one deck adhesive glue (in this embodiment, this adhesive glue thermal curable) in a side of framework 51 contiguous inductive element 62 first surfaces with the first conductor layer 61; Secondly, framework 51 is bonded to the outer surface of inductive element 62, then bending framework 51 makes the first conductor layer 61 must be coated the first surface of inductive element 62; Finally with a hot processing procedure with hot curing adhesive glue after, the first conductor layer 61 fixed packet can be overlying on to the first surface of inductive element 62, to obtain this integrated morphology 53.
From the above, in the integrated morphology 53 being obtained with the present embodiment preceding method, the maximal clearance between the first conductor layer 61 and inductive element 62 is less than 0.3mm.By framework 51 bendings, to be coated the integrated morphology 53 of inductive element 62, its upward view and vertical view are respectively as shown in Fig. 5 D and Fig. 5 E.
Refer to Fig. 6 A, Fig. 6 B and Fig. 6 C, it shows the concrete application that the present invention first implements, and wherein Fig. 6 A and Fig. 6 B show respectively the top and bottom perspective views of a direct current transducer, the vertical view that Fig. 6 C those shown comprises this direct current transducer combined circuit.Direct current transducer 60 application of aforementioned that Fig. 6 A and Fig. 6 B show have the inductive element 62 of large area pin, and direct current transducer 60 can be applicable to the step-down controller of load end, that is can be applicable to a POL direct current transducer.Combined circuit 4 shown in Fig. 6 C, a circuit structure of application direct current transducer 60, the details will be described later.
As figure, in this embodiment, combined circuit 4 comprises two in order to carry the first carrier and second carrier of electronic component, for example be respectively a first circuit board 69, a second circuit board 63, combined circuit 4 more comprises one first conductor layer 61, an inductive element 62, one first electronic component 66,2 second electronic components 64,65 and 2 the 3rd electronic components 67,68.Wherein, except first circuit board 69, all the other elements can form aforesaid direct current transducer 60 jointly.In this embodiment, inductive element 62, the first electronic component 66, the second electronic component 64,65 and the 3rd electronic component 67,68 are respectively inductance, control chip, electric capacity and field-effect transistor; And implement in aspect in other, each electronic component can be an inductance, a resistance, an electric capacity, a field-effect transistor, a control chip and an integrated circuit one of them, integrated circuit is with at least wherein two integrated and obtain of an inductance, a resistance, an electric capacity, a field-effect transistor and a control chip.Wherein, also can be described as a switch element or a power component as the field-effect transistor of the 3rd electronic component 67,68, and this field-effect transistor is a mos field effect transistor (MOSFET).
Refer to shown in Fig. 6 A, Fig. 6 B and Fig. 6 C, first circuit board 69 is electrically connected with the bonding conductor 40 of coated inductive element 62 first surfaces.The first electronic component 66 is also electrically connected with the bonding conductor 40 of coated inductive element 62 first surfaces, and more specifically, the first electronic component 66 sees through second circuit board 63 and is electrically connected with bonding conductor 40.
As shown in Fig. 6 A and Fig. 6 B, inductive element 62, the first electronic component 66, the second electronic component 64,65, the 3rd electronic component 67,68 are installed up to second circuit board 63, to form direct current transducer 60.More specifically, second circuit board 63 is generally a printed circuit board (PCB) (Printed Circuit Board, PCB), it has two opposite flanks, and wherein inductive element 62 and second electronic component 64,65 of coated the first conductor layer 61 installed in a side; On the other hand, the first electronic component 66 and the 3rd electronic component 67,68 are installed in the another side of second circuit board 63, as shown in Figure 6B.Fig. 6 C is mounted on first circuit board 69 direct current transducer 60 with aforementioned integrated morphology 53 to form the structural perspective of combined circuit 4.As shown in the figure, direct current transducer 60 by be coated on inductive element 62 bonding conductors 40 and mount to first circuit board 69 as the conductive region 42,43,44,47,48 of pin.
Because the conductive region 42,43,44,47,48 of inductive element 62 bonding conductors 40 is distributed in the outer surface of inductive element 62, the conductive region 42,43,44,47,48 and the first circuit board 69 that make the suitable foot of direct current transducer 60 see through bonding conductor 40 in inductive element 62 are electrically connected, so when direct current transducer 60 is installed up to first circuit board 69, occupied first circuit board 69 spaces are minimum.On the other hand, while being installed to first circuit board 69 due to direct current transducer 60, mechanical support by inductive element 62 bodies as whole direct current transducer 60, thereby can thinning second circuit board 63 when practical application, significantly to reduce the required thickness of second circuit board 63, save the even certain space of combined circuit 4 of direct current transducer 60, so use the power density that effectively improves direct current transducer 60.
In addition, cause the first electronic component 66 and the 3rd electronic component 67,68 are main heater element, and pin 67a, the 68a of the pin 66a of the first electronic component 66 and the 3rd electronic component 67,68 can strengthen through the first conductive layer 61 the integral heat sink ability of direct current transducer 60.Due to the essence thinning of second circuit board 63 thickness, there is the splendid characteristic of thermal conductivity, thereby the heat of first electronic component 66 and the 3rd electronic component 67,68 is easy to just can spread, and by the first electronic component 66 and the auxiliary of the 3rd electronic component 67,68 that are connected with the first conductor layer 61, the heat of direct current transducer 60 is passed to first circuit board 69 in second circuit board 63.
The above practical application of the present invention, it can change according to actual demand.For example, the following stated second embodiment of the present invention feature that also application of aforementioned is identical is in the combined circuit of a direct current transducer 70, as shown in Fig. 7 A and Fig. 7 B.The second embodiment is first electrically connected to second circuit board 63 from different being in the second electronic component 64,65 of the first embodiment of the first embodiment, is electrically connected with the bonding conductor 40 of the first conductor layer 61 by second circuit board 63; The second electronic component 72,73 of the second embodiment directly carries out entity and electric connection with the bonding conductor 71 of inductive element 74 outer surfaces, more specifically, the second electronic component 72,73 is directly installed on bonding conductor 71, as shown in Figure 7 A, adopt aforementioned connected mode direct current transducer 70 three-dimensional structure diagram as shown in Figure 7 B.
Should be noted, the present embodiment adopts the structure that the first conductor layer 71 is coated on to the first electronic component (being inductance) 74 surfaces, in other enforcement aspects of the present embodiment, the first conductor layer 71 also can be coated on the surface of aforementioned the first electronic component (scheming not shown) or the 3rd electronic component (scheming not shown) instead, again the second electronic component (being electric capacity) 72,73 is directly pasted on the first conductor layer 71 that is coated on the first electronic component or the 3rd electronical elements surface, to reach the same effect of aforementioned bring to power density and reduced volume.
The third embodiment of the present invention is also a kind of combined circuit that is applied to a direct current transducer, especially a POL direct current transducer, and its correlative type is as shown in Figure 11 A to 11G.Figure 11 A and Figure 11 B are respectively the top and bottom perspective views of POL direct current transducer 110, and wherein POL direct current transducer 110 is taking common burning magnetic material (Co-fired ferrite material) inductance as substrate.POL direct current transducer 110 has comprised an inductive element, one first conductor layer 112,2 second electronic components, a quadrielectron element and an inductance coil 116.In this embodiment, inductive element burns the overlapped formation of magnetic material substrate 111 altogether by several layers, the second electronic component is electric capacity 114, quadrielectron element is the integrated circuit 115 of an integrated field-effect transistor (especially for metal oxide semiconductor field effect is answered transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET)) and a control chip.As previously mentioned, the first conductor layer 112 comprises a bonding conductor and a pin conductor, in this embodiment bonding conductor have four pins 118 and with the conductor being connected 113, pin conductor have two pins 117 and with the conductor being connected 113.
The first conductor layer 112 is coated on a first surface of common burning magnetic material substrate 111 outer surfaces after overlapped, and this first surface comprises upper surface, lower surface and side, and more specifically, side is coated by conductor 113.The first conductor layer 112 of upper surface provides the electric connection of electric capacity 114 and integrated circuit 115 etc.; And in the time that combined circuit is installed to a carrier (be a main circuit board and scheme not shown in this), can be electrically connected with carrier by the first conductor layer 112 of lower surface; 113 of conductors that are coated in the first conductor layer 112 of side have been electrically connected the first conductor layer 112 that is positioned at upper surface and lower surface.
Say in detail, burn altogether magnetic material inductance 111 and formed by multi-layered magnetic material base material sintering, the practice of its production method and LTCC (Low Temperature Co-fired Ceramic, LTCC) is similar.As shown in Figure 11 E, 116 of inductance coils comprise multiple connection conducting elements 119, its practice is to make multiple through holes on the magnetic material base material of each layer of centre, after the magnetic material base material parallel stacks of each layer is happened frequently, the corresponding through hole on each layer of upper base material is that the projection in the parallel plane of magnetic material layer overlaps substantially.Equally make multiple half-round cross holes on the both sides of the magnetic material of each layer, then will in every layer of through hole, insert metal, for example silver (Ag), palladium (Pd), gold (Au) or copper (Cu), to produce connection conducting element 119 and the pin 117,118 of inductance coil 116.Make many strip conductors at the upper surface of the superiors' magnetic material and the lower surface of orlop magnetic material, every strip conductor connects two through holes on this layer of magnetic material.Finally, then by multi-layered magnetic material base material pressing, just can form the first conductor layer 113 of inductance coil 116 and part, wherein inductance coil 116 is electrically connected to the pin 117 of pin conductor.
At the inductance upper and lower surface the completing material that respectively repeatedly one deck magnetic material or painting one deck insulate again, and on this layer of magnetic material or insulating material, make corresponding semi-circular through hole and insert metal, forming and burn altogether magnetic material substrate 111.The first conductor layer 112 is formed on the surface of common burning magnetic material substrate 111, with installing electronic elements, the for example integrated circuit 115 of electric capacity 114 and integrated field-effect transistor and control chip, to be electrically connected the first conductor layer 112, and form whole POL direct current transducer 110 as shown in FIG. Figure 11 A and 11 B in substrate 111.Figure 11 C is the schematic diagram of common burning magnetic material substrate 111, the first conductor layer 112.Figure 11 D is that common burning magnetic material substrate 111 is removed the schematic diagram after ground floor magnetic material base material, to show the inductance coil 116 of common burning magnetic material substrate 111 inside and the electric connection of pin.Figure 11 E is the internal structure perspective view of Figure 11 D, in figure, just can find out the direction that inductance coil 116 is wound around thus, and can know that demonstration pin 117 has connected inductance coil 116.Figure 11 F is common burning magnetic material substrate 111 other internal layer circuit schematic diagrames except ground floor, the second layer and last one deck.Figure 11 G is for burning altogether last sandwich circuit schematic diagram of magnetic material substrate 111.Burn altogether as we can see from the figure at least a portion of the bonding conductor on magnetic material substrate 111 outer surfaces or isolation mutually all and between pin conductor, that is bonding conductor at least a portion or all there is no direct entity and electric connection between the two with pin conductor on outer surface.More specifically, at least a portion of bonding conductor or all with pin conductor between the two for to be indirectly connected, in the time burning altogether the electronic component that has stacked other on magnetic material substrate 111 as electric capacity 114 and integrated circuit 115 etc., the pin 117 that the pin 118 of its bonding conductor begins indirectly to see through other electron component and pin conductor is electrically connected.
The fourth embodiment of the present invention is similarly a kind of combined circuit that is applied to a direct current transducer, an especially POL direct current transducer 120, and its correlative type is as shown in Figure 12 A to 12D.Figure 12 A and Figure 12 B are respectively inductance coil 127 and are pressed on vertical view and the upward view of the POL direct current transducer 120 in magnetic material substrate 125.POL direct current transducer 120 comprises a quadrielectron element, 2 second electronic components, one first conductor layer 123 and an inductive element.Quadrielectron element is an integrated field-effect transistor (being especially MOSFET) and the integrated circuit 121 of control chip, 2 second electronic components are electric capacity 122, and inductive element has comprised aforesaid magnetic material substrate 125 and inductance coil 127.As previously mentioned, the first conductor layer 123 comprises and has the bonding conductor of four pins 124 and have the pin conductor of two pins 126, and each pin 124 and each pin 126 of pin conductor of bonding conductor all comprise a conductor 129.
The first conductor layer 123 is coated on a first surface of magnetic material substrate 125 outer surfaces, and this first surface comprises upper surface, lower surface and side, and more specifically, side is coated by the conductor 129 in the first conductor layer 123.And integrated circuit 121 is directly mounted on the first conductor layer 123 on magnetic material substrate 125 with electric capacity 122, and with direct contact to form be electrically connected.More specifically, conductor 129 passes the upper and lower surface of magnetic material substrate 125 with the form of through hole, form and be electrically connected with the upper and lower surface in magnetic material substrate 125.And be installed to a carrier (be a main circuit board and scheme not shown in this) when combined circuit)) time, can be electrically connected by the first conductor layer 123 and carrier.Meanwhile, the conductor 129 in two pins 126 of pin conductor is connected to form electric connection with the flat coil pin 128 of inductance coil 127 2 ends of magnetic material substrate 125 inside.Figure 12 C is the schematic diagram of magnetic material substrate 125, the first conductor layer 123 and conductor 129, Figure 12 D is the internal structure perspective view of Figure 12 C, in figure, just can find out that the coil pin 128 at two ends of inductance coil 127 and the conductor 129 of the pin 126 of pin conductor are connected thus.
Described in the 3rd embodiment, inductance coil 127 has been pressed on wherein in the time making magnetic material substrate 125.And as previously mentioned, as we can see from the figure at least a portion of the pin 124 of bonding conductor or all and the pin 126 of pin conductor between isolation mutually, that is at least a portion of the pin 124 of bonding conductor or all and the pin 126 of pin conductor both between on outer surface, there is no direct entity and electric connection.
The fifth embodiment of the present invention is still a kind of combined circuit that is applied to a direct current transducer, especially a POL direct current transducer, and its correlative type is as shown in Figure 13 A to 13F.Wherein Figure 13 A and Figure 13 B are respectively vertical view and the upward view at the POL direct current transducer 13 of magnetic material substrate 136 internal production inductance coils 138 by through hole.POL direct current transducer 13 comprises a quadrielectron element, 2 second electronic components, an insulating barrier 133, one first conductor layer 134 and an inductive element.Quadrielectron element is an integrated field-effect transistor (being especially MOSFET) and the integrated circuit 131 of control chip, 2 second electronic components are electric capacity 132, and inductive element comprises foregoing magnetic material substrate 136 and inductance coil 138.The first conductor layer 134 comprises and has the bonding conductor of four pins 135 and have the pin conductor of two pins 137, and each pin 135 and each pin 137 of pin conductor of bonding conductor all comprise a conductor 139.
The first conductor layer 134 is coated on a first surface of magnetic material substrate 136 outer surfaces, and this first surface comprises lower surface and side, and more specifically, side is coated by the conductor 139 in the first conductor layer 134; In addition, the first conductor layer 134 has more been coated the insulating barrier 133 of the upper surface that is positioned at magnetic material substrate 136 outer surfaces.And integrated circuit 131 is directly mounted on the upper surface of the first conductor layer 134 of magnetic material substrate 136 with electric capacity 132, and directly contacts and form electric connection with it.More specifically, conductor 139 passes the upper and lower surface of magnetic material substrate 136 with the form of through hole, form and be electrically connected with the upper and lower surface in magnetic material substrate 136.As previously mentioned, insulating barrier 133 is folded between the first conductor layer 134 and magnetic material substrate 136, uses so that both insulation.
And be installed to a carrier (be a main circuit board and scheme not shown in this) when combined circuit))))) time, can be electrically connected by the first conductor layer 134 and carrier.Figure 13 C is the schematic diagram of magnetic material substrate 136, the first conductor layer 134, insulating barrier 133 and conductor 139, and Figure 13 D is the end view of Figure 13 C, those graphic structures that show respectively each layer.In Figure 13 E, its signal does not cover the schematic diagram of the magnetic material substrate 136 of insulating barrier 133, and in this figure, two of two pins 137 connect conducting element 139 ' all in order to connect inductance coil 138 and conductor 139.Figure 13 F is the internal structure perspective view of Figure 13 E, can find out by this coiling direction of inductance coil 138.
The concrete methods of realizing of the present embodiment can be as follows, and inductance coil 138 is to make by drilling through the mode such as hole and the electroplates in hole on magnetic material substrate 136.And then in the insulating barrier 133 of magnetic material substrate 136 upper surface coating viscosity, then the first conductor layer 134 is pressed on to the surface of magnetic material substrate 136, the mode of the plating by drilling through hole and through hole obtains conductor 139 again, this measure just and the manufacturing process of PCB similar.
And, as previously mentioned, at least a portion of the pin 135 of bonding conductor or isolation mutually all and between the pin 137 of pin conductor as we can see from the figure, that is at least a portion of the pin 135 of bonding conductor or all there is no direct entity and electric connection between the two with the pin 137 of pin conductor on outer surface, it is connected to through circuit board or other electronic components, and such as the indirect mode such as integrated circuit 131, electric capacity 132 connects.
Generally speaking, all substrates using the magnetic material of inductance as whole POL direct current transducer of the 3rd embodiment to the five embodiment.Upper surface as the inductance magnetic material substrate of inductive element body is coated with one first conductor layer, in order to connect the electric signal of each electronic component, electronic component comprises an inductance, one resistance, one electric capacity, one field-effect transistor, one control chip and an integrated circuit one of them, integrated circuit is with an inductance, one resistance, one electric capacity, at least wherein two integrated and obtain of one field-effect transistor and a control chip, and this electronic component can engage by surface mount or routing connected modes such as (wire bond) and realize with the electric connection of the first conductor layer.The lower surface of inductance is output and the input of the electric signal of POL direct current transducer, that is the pin of POL direct current transducer, in order to be welded on a circuit board (being the first carrier of aforementioned each embodiment).The upper and lower surface of inductance connects by the conductor in the first conductor layer.What need emphasize is, if by the electronic component integration such as electric capacity, resistance in POL direct current transducer, the impact that the parasitic parameter that is more conducive to reduce POL direct current transducer inside is brought, thus better electric property can be obtained, especially for the POL direct current transducer of small-sized high frequency.
The sixth embodiment of the present invention be also by the feature application described in the first embodiment in a direct current transducer, its correlative type is as shown in Figure 8 A and 8 B.In this embodiment, a direct current transducer 80 also can be connected to the first carrier (be a circuit board in this, and scheme not shown).The direct current transducer 80 of this embodiment comprises one second carrier, an inductive element 89a, one first electronic component 85,2 second electronic component 89b and 2 the 3rd electronic component 89c, and the second carrier for example can be a second circuit board 88.Similar as described in the first embodiment, the first electronic component 85 surfaces are also coated one first conductor layer so that the electric connection of direct current transducer and the first carrier to be provided, wherein the first conductor layer comprises a bonding conductor and a pin conductor 84, and wherein bonding conductor has several pins 81,82,83,86,87.In this embodiment, inductive element 89a, the first electronic component 85, the second electronic component 89b and the 3rd electronic component 89c are respectively inductance, control chip, electric capacity and field-effect transistor.
The seventh embodiment of the present invention is applied to a direct current transducer 90 with aforementioned same characteristic features equally.As Fig. 9 A, shown in Fig. 9 B, in this embodiment, direct current transducer 90 also can be connected to one first carrier (be a circuit board and scheme not shown in this), direct current transducer 90 comprises one second carrier, one inductive element 98a, one first electronic component 98b, 2 second electronic component 98c and 2 the 3rd electronic components 93, the second carrier is a second circuit board 97, with similar described in the 6th embodiment, the 3rd electronic component 93 surfaces have been coated one first conductor layer so that the electric connection of direct current transducer and the first carrier to be provided, wherein the first conductor layer comprises a bonding conductor and a pin conductor 94, bonding conductor has several pins 91, 92, 95, 96.In this embodiment, inductive element 98a, the first electronic component 98b, the second electronic component 98c and the 3rd electronic component 93 are respectively inductance, control chip, electric capacity and field-effect transistor.
The eighth embodiment of the present invention as shown in figure 10.In this embodiment, direct current transducer 100 comprises one second carrier, an inductive element 106, one first electronic component 101,2 second electronic components 107 and 2 the 3rd electronic components 103,104 equally.In this embodiment, the second carrier is a second circuit board 102; Similar with previous embodiment, 2 first conductor layer 105a, 105b are coated on electronic component 101,103,104 surfaces so that the electric connection of direct current transducer 100 and one first carrier (in this as a circuit board and scheme not shown) to be provided; Wherein inductive element 106, the first electronic component 101, the second electronic component 107 and the 3rd electronic component 103,104 are respectively inductance, control chip, electric capacity and field-effect transistor.
Above-described direct current transducer is all made up of several independently electronic components, and only along with the development of encapsulation technology, more and more electronic components can be packaged into an independent element jointly, and then forms an integrated circuit, further dwindles the volume of electronic component.Therefore, the aforementioned electronic component that is coated with bonding conductor can be also an integrated circuit.Though aforementioned each embodiment is all applied to combined circuit in direct current transducer, it is noted that, combined circuit of the present invention more applicable in the transducer of other types so that being connected between transducer and circuit board to be provided.
The present invention adopts large-area conductor layer as pin configuration, not only can help strengthen the heat dispersion of each electronic component, more the improvement of the integral heat sink performance to direct current transducer brings greatest help, hereat, adopt syndeton of the present invention, can make direct current transducer element integration degree improve, and can dwindle direct current transducer overall dimensions, promote its power density.
The above embodiments are only in order to exemplify enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not used for limiting category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of isotropism all belong to the scope that the present invention advocates, interest field of the present invention should be as the criterion with claim.
Claims (13)
1. a POL assembly, comprises:
One inductance, there is a upper surface, a lower surface relative with this upper surface and connect multiple sides of this upper surface and this lower surface, on this upper surface, have multiple conductors, wherein each conductor of at least a portion in the plurality of conductor is extended on this lower surface via a side of the plurality of side by this upper surface;
At least one input capacitance, is electrically connected to the plurality of conductor; And
At least one switch element, is arranged at the top of this upper surface of this inductance, and is electrically connected by the plurality of conductor on this upper surface of this inductance and this inductance;
Wherein, on this lower surface of this inductance, there are the multiple pins that are connected to the plurality of conductor to be electrically connected to a carrier.
2. POL assembly as claimed in claim 1, it is characterized in that, also comprise an intermediary circuit plate, this intermediary circuit plate is arranged between this inductance and this at least one switch element, and being electrically connected to this inductance and this at least one switch element, this intermediary circuit plate has a first surface and a second surface.
3. POL assembly as claimed in claim 2, is characterized in that, this at least one switch element is arranged on this intermediary circuit plate and by this intermediary circuit plate and is electrically connected to this inductance.
4. POL assembly as claimed in claim 2, is characterized in that, this at least one input capacitance is arranged on the second surface adjacent with this inductance of this intermediary circuit plate, and is electrically connected to this inductance by this intermediary circuit plate.
5. POL assembly as claimed in claim 2, is characterized in that, this at least one input capacitance is arranged on this first surface relative with this inductance of this intermediary circuit plate, and is electrically connected on this inductance by this intermediary circuit plate.
6. POL assembly as claimed in claim 1, is characterized in that, this at least one input capacitance is arranged at a side of this inductance, and is electrically connected to this inductance by the plurality of conductor on this side.
7. POL assembly as claimed in claim 1, is characterized in that, also comprises an integrated circuit (IC) controller, in order to control this at least one switch element, and is arranged on this upper surface of this inductance.
8. POL assembly as claimed in claim 7, is characterized in that, this integrated circuit controller and this at least one switch element are integrated in an integrated circuit package body.
9. POL assembly as claimed in claim 2, is characterized in that, also comprises an integrated circuit controller, in order to control this at least one switch element, and is arranged on this intermediary circuit plate.
10. POL assembly as claimed in claim 2, is characterized in that, also comprises an output capacitance, is arranged on this second surface adjacent with this inductance of this intermediary circuit plate, and is electrically connected to this inductance by this intermediary circuit plate.
11. POL assemblies as claimed in claim 2, is characterized in that, also comprise an output capacitance, are arranged on this second surface relative with this inductance of this intermediary circuit plate, and are electrically connected to this inductance by this intermediary circuit plate.
12. POL assemblies as claimed in claim 1, is characterized in that, have also comprised an output capacitance, are arranged at a side of this inductance, and are electrically connected to this inductance by the plurality of conductor on this side.
13. POL assemblies as claimed in claim 1, is characterized in that, also comprise a connection conducting element and run through this inductance, and be electrically connected the plurality of conductor on this upper surface and this lower surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110354556.7A CN102412702B (en) | 2008-01-07 | 2008-01-07 | load point assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110354556.7A CN102412702B (en) | 2008-01-07 | 2008-01-07 | load point assembly |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810003217 Division CN101483381B (en) | 2008-01-07 | 2008-01-07 | Combined structure |
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| CN102412702A CN102412702A (en) | 2012-04-11 |
| CN102412702B true CN102412702B (en) | 2014-10-22 |
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| CN201110354556.7A Active CN102412702B (en) | 2008-01-07 | 2008-01-07 | load point assembly |
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| CN114334381A (en) * | 2022-01-30 | 2022-04-12 | 联想(北京)有限公司 | Inductance device, circuit board and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355603A (en) * | 2000-10-17 | 2002-06-26 | 株式会社村田制作所 | Subassembly electronic component |
| CN1674276A (en) * | 2004-03-26 | 2005-09-28 | 乾坤科技股份有限公司 | Multilayer substrate stack packaging structure |
| CN101004965A (en) * | 2006-01-16 | 2007-07-25 | 台达电子工业股份有限公司 | Internal embedded type inductive structure and its producing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3649214B2 (en) * | 2002-08-01 | 2005-05-18 | 富士電機デバイステクノロジー株式会社 | Ultra-compact power converter and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355603A (en) * | 2000-10-17 | 2002-06-26 | 株式会社村田制作所 | Subassembly electronic component |
| CN1674276A (en) * | 2004-03-26 | 2005-09-28 | 乾坤科技股份有限公司 | Multilayer substrate stack packaging structure |
| CN101004965A (en) * | 2006-01-16 | 2007-07-25 | 台达电子工业股份有限公司 | Internal embedded type inductive structure and its producing method |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2004-72815A 2004.03.04 |
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