CN102412181A - Forming method of shallow trench isolation structure - Google Patents
Forming method of shallow trench isolation structure Download PDFInfo
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- CN102412181A CN102412181A CN201010292403XA CN201010292403A CN102412181A CN 102412181 A CN102412181 A CN 102412181A CN 201010292403X A CN201010292403X A CN 201010292403XA CN 201010292403 A CN201010292403 A CN 201010292403A CN 102412181 A CN102412181 A CN 102412181A
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- oxide layer
- cushion oxide
- isolation structure
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Abstract
The invention provides a forming method of a shallow trench isolation structure, and is characterized by comprising providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the surface of the substrate; forming a trench on the hard mask layer, on the liner oxide layer and in the substrate; forming a filling dialectic layer which fills the trench; removing the hard mask layer and exposing the liner oxide layer; carrying out doped ion implantation on the exposed liner oxide layer, so as to form a doped liner oxide layer; and removing the doped liner oxide layer to expose the substrate. The invention can prevent punch-through or short circuit from happening to adjacent polysilicon gate structures which are formed at both sides of the shallow trench isolation structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly fleet plough groove isolation structure formation method.
Background technology
Along with semiconductor technology gets into the deep-submicron epoch; 0.18 the element below the micron for example adopts fleet plough groove isolation structure to carry out lateral isolation mostly between the active area of CMOS integrated circuit, in the patent No. is the United States Patent (USP) of US7112513, can also find more relevant informations about the shallow trench isolation technology.
Fleet plough groove isolation structure is as a kind of device separation, and its concrete technology comprises: the substrate that is formed with cushion oxide layer and hard mask layer successively is provided; The said hard mask layer of etching, cushion oxide layer and substrate form shallow trench successively; In shallow trench, insert medium, and form dielectric layer at substrate surface, said dielectric material can be silica; Said medium is annealed; (ChemicalMechanical Polishing CMP) handles said dielectric layer with chemical mechanical polishing method; Remove said hard mask layer and cushion oxide layer.
Adopt above-mentioned technology, form, comprising: substrate 100 like the described fleet plough groove isolation structure of Fig. 1; Be formed in the substrate 100 and a little more than the fleet plough groove isolation structure 101 on substrate 100 surfaces.With reference to figure 2, in subsequent technique, can be between fleet plough groove isolation structure 101, the surface of substrate 100 forms the grid structure of polysilicon.But, be formed between the polysilicon gate construction on surface of substrate 100 and break-through or short circuit phenomenon can occur usually.
Summary of the invention
The problem that the present invention solves is to avoid the polysilicon gate construction between the fleet plough groove isolation structure break-through or short circuit phenomenon to occur.
For addressing the above problem, the present invention provides a kind of fleet plough groove isolation structure formation method, comprising: provide the surface to be formed with the substrate of cushion oxide layer and hard mask layer successively; In said hard mask layer, cushion oxide layer and substrate, form groove; Form the filling dielectric layer of filling said groove; Remove said hard mask layer and expose cushion oxide layer; The said cushion oxide layer that exposes is carried out dopant ion inject, form the doping cushion oxide layer; Remove said doping cushion oxide layer and expose substrate.
Compared with prior art; The present invention has the following advantages: the present invention injects through the said cushion oxide layer that exposes being carried out dopant ion; Form the doping cushion oxide layer, increase the wet etching rate of cushion oxide layer, thereby expose in the substrate step in the said doping cushion oxide layer of removal; Reduce the wet etching time; Cause bigger loss to filling dielectric layer when avoiding removing the doping cushion oxide layer, thereby can not make that the filling dielectric layer on the surface that is higher than substrate is too narrow, when follow-up formation polysilicon gate construction; Fill dielectric layer and can effectively isolate adjacent polysilicon gate construction, avoid adjacent polysilicon gate construction break-through or short circuit phenomenon to occur as the fleet plough groove isolation structure that is higher than the surface of substrate.
Description of drawings
Fig. 1 is the fleet plough groove isolation structure sketch map that prior art forms;
Fig. 2 is the sketch map that on the fleet plough groove isolation structure that prior art forms, forms grid structure;
Fig. 3 is that fleet plough groove isolation structure of the present invention forms the method flow sketch map;
Fig. 4 to Figure 10 is fleet plough groove isolation structure formation method one an embodiment process sketch map provided by the invention.
Embodiment
Can know by background technology, be formed between the polysilicon gate construction on surface of substrate 100 and break-through or short circuit phenomenon can occur usually.For this reason; Inventor of the present invention is through discovering; Said break-through or short circuit phenomenon owing between polysilicon gate construction, the fleet plough groove isolation structure 101 on surface that is higher than substrate 100 is too narrow; Effectively electricity is isolated adjacent polysilicon gate construction, thereby makes adjacent polysilicon gate construction break-through or short circuit phenomenon occur.
Further study through the inventor; Find that the said too narrow reason of fleet plough groove isolation structure that is higher than substrate surface is: removing the removal of hard mask layer and cushion oxide layer employing wet method; And the material that cushion oxide layer and fleet plough groove isolation structure adopt all is a silicon dioxide; When removing cushion oxide layer, can too much remove the fleet plough groove isolation structure that part is higher than substrate surface simultaneously, make that the fleet plough groove isolation structure that is higher than substrate surface is too narrow.
For this reason, inventor of the present invention provides a kind of fleet plough groove isolation structure formation method of optimization, please refer to Fig. 3, comprises the steps:
Step S101 provides the surface to be formed with the substrate of cushion oxide layer and hard mask layer successively;
Step S102 forms groove in said hard mask layer, cushion oxide layer and substrate;
Step S103 forms the filling dielectric layer of filling said groove;
Step S104 removes said hard mask layer, exposes cushion oxide layer;
Step S105 carries out dopant ion to the said cushion oxide layer that exposes and injects, and forms the doping cushion oxide layer;
Step S106 removes said doping cushion oxide layer and exposes substrate.
The present invention injects through the said cushion oxide layer that exposes being carried out dopant ion; Form the doping cushion oxide layer; Increase the wet etching rate of cushion oxide layer, thereby expose in the substrate step, reduce the wet etching time in the said doping cushion oxide layer of removal; Thereby expose in the substrate step in the said doping cushion oxide layer of follow-up removal; Cause bigger loss to filling dielectric layer when avoiding removing the doping cushion oxide layer, thereby can not make that the filling dielectric layer on the surface that is higher than substrate is too narrow, when follow-up formation polysilicon gate construction; Fill dielectric layer and can effectively isolate adjacent polysilicon gate construction, avoid adjacent polysilicon gate construction break-through or short circuit phenomenon to occur as the fleet plough groove isolation structure that is higher than the surface of substrate.
Below in conjunction with a specific embodiment fleet plough groove isolation structure formation method of the present invention is elaborated.Fig. 4 to Figure 10 is fleet plough groove isolation structure formation method one an embodiment process sketch map provided by the invention.
Please refer to Fig. 4, provide the surface to be formed with the substrate 200 of cushion oxide layer 201 and hard mask layer 202 successively.Said substrate 200 can be selected from the silicon substrates such as (SOI) on N type silicon substrate, P type silicon substrate, the insulating barrier.
Said cushion oxide layer 201 materials are selected from silica; The thickness of said cushion oxide layer 201 is 70 dust to 120 dusts; Said hard mask layer 202 materials are selected from silicon nitride; The thickness of said hard mask layer 202 is 700 dust to 1200 dusts, and said cushion oxide layer 201 is for the hard mask layer 202 of follow-up formation provides resilient coating, and cushion oxide layer 201 can also be as the layer that stops in follow-up removal hard mask layer 202 steps.
Said cushion oxide layer 201 can form for selecting thermal oxidation technology for use.Said thermal oxidation technology can select for use oxidation furnace to carry out.
Said hard mask layer 202 is used for the hard mask of subsequent etching groove and stops layer as the planarization of subsequent planarization filling groove medium, and said hard mask layer 202 forms technologies and can be existing chemical vapor deposition method.
With reference to figure 5, in said hard mask layer 202, cushion oxide layer 201 and substrate 200, form groove 210.
Said groove 210 is packed into spacer medium in subsequent technique, form fleet plough groove isolation structure.The formation technology of said groove 210 is plasma etch process.
Particularly, form the photoresist figure (not shown) corresponding on said hard mask layer 202 surfaces with groove 210; With said photoresist figure is mask, and the said hard mask layer 202 of etching is until exposing cushion oxide layer 201; With the hard mask layer after the said etching 202 is mask, and etching cushion oxide layer 201 and substrate 200 form groove 210 successively.
With reference to figure 6, form the filling dielectric layer 203 of filling said groove 210.
Said filling dielectric layer 203 materials are silica, and the formation technology of said filling dielectric layer 203 is high density plasma CVD (HDP CVD), inferior aumospheric pressure cvd depositing operations such as (SACVD).
The step that the filling dielectric layer 203 of said groove 210 is filled in said formation comprises: adopt depositing operations such as high density plasma CVD or inferior aumospheric pressure cvd in hard mask layer 202 surfaces and said groove 210, to form silicon oxide layer (not shown); Adopt flatening process such as chemico-mechanical polishing that said silicon oxide layer is carried out planarization until exposing hard mask layer 202 then, form the filling dielectric layer 203 of filling said groove 210.
With reference to figure 7, remove said hard mask layer 202 and expose cushion oxide layer 201.
The technology of removing said hard mask layer 202 is that wet method is removed technology; In the present embodiment, said hard mask layer 202 materials are silicon nitride, and correspondingly wet method is removed technology and selected phosphoric acid removal technology for use; Concrete removal technology can here repeat no more with reference to existing silicon nitride removal method.
Need to prove, after the said hard mask layer 202 of removal exposes cushion oxide layer 201, fill dielectric layer 203 surfaces and be higher than about 700 dust to 1200 dusts in cushion oxide layer 201 surfaces greater than meeting.
With reference to figure 8, the said cushion oxide layer that exposes 201 is carried out dopant ion inject, form doping cushion oxide layer 204.
Said doping cushion oxide layer 204 thickness are 70 dust to 120 dusts.
Said dopant ion injects can select ion implantation device for use, and particularly, said dopant ion is the nitrogen ion, and the dosage of said doping is 3 * 10
14/ cm
2To 4 * 10
15/ cm
2, said ion implantation energy is 200ev to 10kev.
In other embodiments; Injecting nitrogen ion also can adopt dopant ions such as boron, phosphorus, fluorine, but preferred injection ion is the nitrogen ion, because can not change the doping content in the substrate; Semiconductor device influence to follow-up formation is less; And nitrogen ion atoms radius is less, and cushion oxide layer 201 has only 70 dust to 120 dusts usually, and adopting the dosage that mixes is 2 * 10
15/ cm
2To 4 * 10
15/ cm
2, said ion implantation energy is that the process conditions of 4kev to 10kev can not damaged substrate 200.
The inventor finds, adopts above-mentioned technology to form doping cushion oxide layer 204 after, said doping cushion oxide layer 204 has higher selective etching ratio with filling dielectric layer 203.And before not carrying out the dopant ion injection; Because it is thermal oxidation technology that said cushion oxide layer 201 forms technology; The formation technology of said filling dielectric layer 203 is high density plasma CVD or inferior aumospheric pressure cvd technology, and said cushion oxide layer 201 can be than filling dielectric layer 203 densifications.For with a kind of etching solution; The etch rate of cushion oxide layer 201 is lower than the etch rate of filling dielectric layer 203; Be higher than substrate 200 surfaces and can preferentially be etched away and fill dielectric layer 203; Thereby in the process of removing substrate oxide layer 201, filling dielectric layer 203, to be higher than the part on substrate 200 surfaces too narrow.
After adopting this step to form doping cushion oxide layer 204, said doping cushion oxide layer 204 has higher selective etching ratio with the cushion oxide layer of not mixing.To this, inventor of the present invention has done a series of contrast test, and concrete test data sees table:
In above-mentioned test, inventor of the present invention adopts 5 kinds of different dopant ion injection technology conditions: said ion implantation energy is that the dosage of 4kev, said doping is 2 * 10
15/ cm
2Said ion implantation energy is that the dosage of 4kev, said doping is 3 * 10
15/ cm
2Said ion implantation energy is that the dosage of 4kev, said doping is 4 * 10
15/ cm
2Said ion implantation energy is 8kev, and the dosage of said doping is 2 * 10
15/ cm
2Said ion implantation energy is that the dosage of 10kev, said doping is 2 * 10
15/ cm
2Form 5 kinds of doping cushion oxide layer, adopt same DHF etching solution to carry out etching, find that the doping cushion oxide layer and the etching ratio of the cushion oxide layer of not mixing are 4: 1 with the cushion oxide layer of not mixing.Can reduce the wet etching time thus, fill the especially loss on sidewall of dielectric layer thereby reduce.
With reference to figure 9, remove said doping cushion oxide layer 204 and expose substrate 200.
Said removal technology is that wet method is removed, and adopts the DHF etching solution, and being preferably composition is that concentration 30%～49% hydrofluoric acid (HF) is removed said doping cushion oxide layer 204, exposes substrate 200.
Also need to prove;, removal also can remove partially filled dielectric layer 203 when stating doping cushion oxide layer 204; But because said doping cushion oxide layer 204 has higher selective etching ratio with filling dielectric layer 203; Adopting preferred etching solution to remove said doping cushion oxide layer 204, avoid removing too much filling dielectric layer 203, make the filling dielectric layer 203 that is higher than substrate 200 surfaces have more excellent isolation effect.
With reference to Figure 10, in follow-up processing step, can form grid structure on the substrate that exposes 200 surfaces, said grid structure comprises gate dielectric layer and gate electrode layer.Because it is more excellent to be higher than filling dielectric layer 203 isolation effects on cushion oxide layer 201 surfaces, adjacent grid structure break-through or short circuit phenomenon can not occur.
In sum; The present invention injects through the said cushion oxide layer that exposes being carried out dopant ion; Form the doping cushion oxide layer, increase the DHF rate of etch of cushion oxide layer, and then can reduce the wet etching time; Thereby expose in the substrate step in the said doping cushion oxide layer of removal; Cause bigger loss to filling dielectric layer when avoiding removing the doping cushion oxide layer, thereby expose in the substrate step, cause bigger loss to filling dielectric layer when avoiding removing the doping cushion oxide layer in the said doping cushion oxide layer of follow-up removal; Thereby can not make that the filling dielectric layer on the surface that is higher than substrate is too narrow; When follow-up formation polysilicon gate construction, fill dielectric layer and can effectively isolate adjacent polysilicon gate construction as the fleet plough groove isolation structure that is higher than the surface of substrate, avoid adjacent polysilicon gate construction break-through or short circuit phenomenon to occur.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. fleet plough groove isolation structure formation method comprises:
Provide the surface to be formed with the substrate of cushion oxide layer and hard mask layer successively;
In said hard mask layer, cushion oxide layer and substrate, form groove;
Form the filling dielectric layer of filling said groove;
Remove said hard mask layer, expose cushion oxide layer;
It is characterized in that, also comprise:
The said cushion oxide layer that exposes is carried out dopant ion inject, form the doping cushion oxide layer;
Remove said doping cushion oxide layer and expose substrate.
2. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, said dopant ion is boron ion, phosphonium ion or fluorine ion.
3. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, said dopant ion is the nitrogen ion.
4. fleet plough groove isolation structure formation method as claimed in claim 3 is characterized in that, the concrete process conditions that form the doping cushion oxide layer are: the dosage of said doping is 3 * 10
14/ cm
2To 4 * 10
15/ cm
2, said ion implantation energy is 200ev to 10kev.
5. fleet plough groove isolation structure formation method as claimed in claim 3 is characterized in that, the concrete process conditions that form the doping cushion oxide layer are: the dosage of said doping is 2 * 10
15/ cm
2To 4 * 10
15/ cm
2, said ion implantation energy is 4kev to 10kev.
6. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, the doping cushion oxide layer is 4: 1 with the etching ratio of filling dielectric layer.
7. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, said liner oxidation layer thickness is 70 dust to 120 dusts.
8. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, said hard mask layer thickness is 700 dust to 1200 dusts.
9. fleet plough groove isolation structure formation method as claimed in claim 1 is characterized in that, the technology of removing said doping cushion oxide layer is that wet method is removed technology.
10. fleet plough groove isolation structure formation method as claimed in claim 9 is characterized in that, it is that 30%～49% hydrofluoric acid solution is removed technology for adopting concentration that said wet method is removed technology.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425354A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench isolation structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010029083A1 (en) * | 1999-09-15 | 2001-10-11 | Shu-Ya Chuang | Method for forming shallow trench isolation structure |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN101266948A (en) * | 2008-04-16 | 2008-09-17 | 苏州硅能半导体科技股份有限公司 | Method for making MOS field effect tube with increased source pole metal contact area |
| US20090130820A1 (en) * | 2007-11-16 | 2009-05-21 | Dae-Young Kim | Method for manufacturing a semiconductor device |
-
2010
- 2010-09-19 CN CN201010292403.XA patent/CN102412181B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010029083A1 (en) * | 1999-09-15 | 2001-10-11 | Shu-Ya Chuang | Method for forming shallow trench isolation structure |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| US20090130820A1 (en) * | 2007-11-16 | 2009-05-21 | Dae-Young Kim | Method for manufacturing a semiconductor device |
| CN101266948A (en) * | 2008-04-16 | 2008-09-17 | 苏州硅能半导体科技股份有限公司 | Method for making MOS field effect tube with increased source pole metal contact area |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425354A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench isolation structure |
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