CN102412148A

CN102412148A - Preparation method of IGBT device

Info

Publication number: CN102412148A
Application number: CN201110183356XA
Authority: CN
Inventors: 张帅; 王海军
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-07-01
Filing date: 2011-07-01
Publication date: 2012-04-11
Anticipated expiration: 2031-07-01
Also published as: CN102412148B

Abstract

The invention discloses a preparation method of an IGBT device. The method comprises the following steps: 1) using a lithography process to define patterns arranged with regular intervals on a back side of a substrate; 2) etching the back side of the substrate till a predetermined depth so as to form a groove or a hole and forming the hole or groove patterns arrange with the regular intervals on the back side of the substrate; 3) using a deposition technology to fill silicon materials in the hole or groove patterns on the back side of the substrate, wherein a bulk concentration of a doping impurity in the silicon material is from 1x10<13> atom per cubic centimeter to 1x10<20> atom per cubic centimeter; 4) annealing processing is performed to the substrate so as to diffuse the doping impurity, and then forming a field barrier layer on which the doping impurity distributed uniformly on the back side of the substrate. By using the method of the invention, the thick field barrier layer can be formed on the back side of the substrate.

Description

IGBT preparation of devices method

Technical field

The present invention relates to a kind of IGBT preparation of devices method.

Background technology

IGBT (insulated gate bipolar transistor) is a kind of powerful power electronic device.For greater than 1200 volts of above IGBT devices, need to increase the back surface field barrier layer usually to improve device withstand voltage, reduce the emission effciency in hole, reduce the risk of fastening the lock effect.

Now industry mainly is a preparation IGBT device on the silicon chip of 4 inches or 6 inches, because the own thickness of silicon chip of 4 inches or 6 inches is just very thin, does not have big technology risk.And for 8 inches silicon chip, because the silicon chip that process equipment allowed is thicker, and the IGBT preparation of devices on a band barrier layer requires silicon chip thinner.Like preparation IGBT device on 8 inches, the degree of depth on barrier layer, field that requires the back side is at more than 100 microns, and present high temperature pushes away trap technology and do not reach this degree of depth.Therefore, this is a very big challenge.

Summary of the invention

The technical problem that the present invention will solve provides a kind of IGBT preparation of devices method, and it can form junction depth greater than the barrier layer, field more than 100 microns at substrate back.

For solving the problems of the technologies described above, IGBT preparation of devices method of the present invention comprises the steps:

Step 1 adopts photoetching process, defines spaced figure at substrate back;

Step 2, the said substrate back of etching to desired depth forms groove or hole, forms spaced hole or groove figure at substrate back;

Step 3 adopts depositing technics, in the hole of substrate back or groove figure, fills silicon materials, and the bulk concentration of the impurity in the said silicon materials is 1 * 10 ¹³Every cubic centimetre in individual atom is to 1 * 10 ²⁰Between every cubic centimetre in the individual atom, and the conductivity type opposite of the conduction type of said impurity and said substrate;

Step 4 is carried out annealing in process to said substrate, makes said impurity thermal diffusion, thereby forms the barrier layer, field that impurity is evenly distributed at said substrate back.

Further, the silicon materials in the above-mentioned steps three are monocrystalline silicon, polysilicon or amorphous silicon.

Further, what etching formed in the above-mentioned steps two is groove, and wherein the angle of the sidewall of groove and horizontal plane is 87 °～90 °.

Further, desired depth is greater than 100 microns in the above-mentioned steps two.

Further, the temperature of treatment process is greater than 1100 degree in the annealing in process in the above-mentioned steps four, and annealing time was greater than 5 hours.

IGBT preparation of devices method of the present invention can reach hole or groove more than 100 microns deeply at the silicon chip back-etching, is used in then to fill silicon materials in hole or the groove, and carries out high temperature and push away trap for a long time, forms thicker back surface field barrier layer.As adopt 8 inches silicon chips to prepare the IGBT device; Can keep the original thickness of silicon chip earlier; So also can make preceding road technology by maintenance, after finishing preceding road device, be turned to the silicon chip back side again and carry out silicon chip and grind the thickness of cutting to required; Then the deposit backplate has formed a new IGBT device architecture like this.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is an IGBT preparation of devices method flow diagram of the present invention;

Fig. 2 is the pictorial diagram in the hole of substrate back in the method for the present invention;

Fig. 3 is the cross section structure sketch map after adopting substrate back in the method preparation flow of the present invention groove etched;

Fig. 4 fills the cross section structure sketch map behind the substrate back for silicon materials;

Fig. 5 is the cross section structure sketch map of the substrate back after the annealing in process;

Fig. 6 is the SEM figure of silicon section after the substrate back annealing in process;

Fig. 7 characterizes the annealing junction depth sketch map of substrate back afterwards for adopting the SRP method.

Embodiment

The IGBT device preparing process that provides of the present invention promptly forms the big barrier layer, field more than 100 microns of junction depth at substrate back.

Embodiment 1

In this embodiment, the IGBT device preparing process comprises the steps (referring to Fig. 1):

1, adopts photoetching process, define regularly arranged hole pattern at substrate back.Be specially and design regularly arranged hole pattern earlier, making then has the lithography mask version (see figure 2) of this figure; Then, then adopt above-mentioned lithography mask version to make public, form the hole pattern of photoresist at substrate back at substrate back spin coating photoresist.The preparation technology of above-mentioned photoetching process and lithography mask version in the industry cycle is mature technology.In the present embodiment, can use any existing photoetching technique.

2, the said substrate back of etching is to desired depth, in the hole pattern (see figure 3) of substrate back formation rule arrangement.In the etching process, photoresist is an etching barrier layer.Desired depth depends on the thickness of substrate usually, and is thicker like 8 inches substrate, and etching depth is corresponding just dark, to form the device of entire I GBT.

3, in the hole of substrate back, fill the silicon materials (see figure 4), the bulk concentration of the impurity in the silicon materials is 1 * 10 ¹⁴Every cubic centimetre in individual atom, and the conductivity type opposite of the conduction type of impurity and substrate.The depositing technics of silicon materials generally adopts epitaxial growth method, and available while doped epitaxial technology specifically can be progressively highly doped epitaxy technique, and above-mentioned silicon materials can be polysilicons, also can be monocrystalline silicon or amorphous silicon.

4, substrate is carried out annealing in process, make the impurity diffusion in the silicon materials, thereby form barrier layer, the field (see figure 5) that impurity is evenly distributed at substrate back.Annealing in process can adopt the conventional trap technological parameter that pushes away, and forms equally distributed barrier layer of impurity to reach.A concrete setting can be: the temperature of anneal chamber is greater than 1100 degree, and annealing time was greater than 5 hours.

Embodiment 2

In this embodiment, the IGBT preparation of devices comprises the steps:

1, earlier preparing etching barrier layer at substrate (silicon chip) back side, can be thickness greater than 0.5 micron silicon dioxide or silicon nitride.The preparation method of silicon dioxide can be high temperature oxidation process.

2, adopt photoetching process, the groove figure that formation rule is arranged on the photoresist on the etching barrier layer.Concrete process is identical with step 1 in the foregoing description.

3, etching barrier layer is carried out etching, form the groove figure.

4, then from silicon chip back-etching silicon chip to desired depth, form groove.The degree of depth of groove is by the thickness decision of silicon chip, and in the instantiation, groove depth can be more than 100 microns, and the sidewall of groove and the angle of horizontal plane can be 87 °～90 °.

5, remove the etching barrier layer at the silicon chip back side.When etching barrier layer is silicon dioxide, can adopt wet etching to remove, promptly adopt chemical liquid that the silicon dioxide etching at the back side is fallen.

6, follow the deposit silicon material, to fill the groove at the silicon chip back side.Epitaxial growth technology is generally adopted in the deposit of silicon materials, in extension, carries out autodoping, the conductivity type opposite of the conduction type of impurity and substrate wherein, and the bulk concentration of impurity is 1 * 10 in silicon materials ¹⁸Every cubic centimetre in individual atom.Epitaxial growth is carried out in epitaxial chamber, and relevant processing step and parameter setting are that one of ordinary skill in the art is understood, and no longer describe in detail here.

7, then silicon chip is carried out annealing in process, make impurity diffusion and be evenly distributed, form a barrier layer.This step annealing handle with the injection of common ion after annealing in process similar, especially with semiconductor technology in to push away trap technology similar.Concrete technological parameter is the same.

Fig. 6 is the silicon section SEM figure after the annealing in process of the silicon chip back side, 30 microns of the degree of depth of groove wherein, and final annealing can to form the degree of depth after handling be 32 microns barrier layer, field.SRP shown in Figure 7 (spreading resistance probe test method) collection of illustrative plates shows that the PN junction at the silicon chip back side is deeply greater than 30 microns.

Claims

1. an IGBT preparation of devices method is characterized in that, comprises the steps:

Step 1 adopts photoetching process, defines spaced figure at substrate back;

Step 3 adopts depositing technics, in the hole of said substrate back or groove figure, fills silicon materials, and the bulk concentration of impurity is 1 * 10 in the said silicon materials ¹³Every cubic centimetre in individual atom is to 1 * 10 ²⁰Between every cubic centimetre in the individual atom;

Step 4 is carried out annealing in process to said substrate, makes said impurity diffusion, thereby forms the barrier layer, field that impurity is evenly distributed at said substrate back.

2. preparation method as claimed in claim 1 is characterized in that: the silicon materials in the said step 3 are monocrystalline silicon, polysilicon or amorphous silicon.

3. preparation method as claimed in claim 1 is characterized in that: what etching formed in the said step 2 is groove, and the sidewall of said groove and the angle of horizontal plane are 87 °～90 °.

4. preparation method as claimed in claim 1 is characterized in that: desired depth is greater than 100 microns in the said step 2.

5. preparation method as claimed in claim 1 is characterized in that: the temperature of treatment process is greater than 1100 degree in the annealing in process in the said step 4, and annealing time was greater than 5 hours.