CN102412121B - Fabrication method for silicon nanotubes - Google Patents
Fabrication method for silicon nanotubes Download PDFInfo
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- CN102412121B CN102412121B CN 201110328166 CN201110328166A CN102412121B CN 102412121 B CN102412121 B CN 102412121B CN 201110328166 CN201110328166 CN 201110328166 CN 201110328166 A CN201110328166 A CN 201110328166A CN 102412121 B CN102412121 B CN 102412121B
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Abstract
The invention relates to a fabrication method for silicon nanotubes. The method includes the following steps: a silicon dioxide layer is grown on a silicon wafer by way of thermal oxidation, and polycrystalline silicon and silicon nitride are sequentially deposited on the silicon dioxide layer; the polycrystalline silicon and the silicon nitride are etched, so that polycrystalline silicon lines covered by the silicon nitride at the top are formed; ions are injected at a first angle in one side of each polycrystalline silicon line; the silicon nitride on each polycrystalline silicon line is removed; ions are injected at a second angle in the other side of each polycrystalline silicon line; and silicon dioxide films are grown on the polycrystalline silicon lines by way of thermal oxidation, so that a silicon nanotube is formed. Since the fabrication method adopts the silicon nitride as injection barrier layers, doping on the surfaces of the polycrystalline silicon lines is uniform, meanwhile, the thicknesses of the silicon dioxide films grown on the polycrystalline silicon lines by way of thermal oxidation are uniform, and thereby the performance of the silicon nanotube is enhanced.
Description
Technical field
The present invention relates to a kind of biochip, particularly a kind of manufacture method of nano-tube.
Background technology
Utilize microRNA (miRNA) to obtain sufficient research and development as the diagnosis biomarker over nearly 5 years, market is huge.The main means that detect microRNA are genetic chips at present, and wherein nano-tube (Si nanowire) is exactly wherein the most popular person.Have the high detection sensitivity, simple to operate, but absolute quantitation detects advantage multinomial and that detecting instrument is conventional simultaneously.
The basic structure of nano-tube be superfine length polysilicon lines outsourcing uniform thickness oxide-film and expose under external environment, shown in Fig. 1 a and Fig. 1 b, thermal oxide growth silicon dioxide layer 7 on silicon chip 6 normally, deposit spathic silicon on silicon dioxide layer 7, and adopt photoetching, etching technics, form polysilicon lines 8 at silicon dioxide layer 7, wherein the sidewall of polysilicon lines and top need evenly to mix, and the oxide-film (not shown) thickness of polysilicon lines 8 outsourcings also needs to keep the consistent of sidewall and top.
Owing to present ion implantor platform all is for 2 graphics devices of tieing up design, directly use the nano-tube in the 3D structure can have the vertical problem different with the inclination implant angle, cause the left and right sides injection rate big-difference to occur.Not only influence polysilicon surface and mix inhomogeneously, and inhomogeneous doping surfaces can cause the subsequent oxidation membrane thickness unevenness, influences device performance.
Fig. 1 a is the inclination injection mode of band angle, if silicon chip is not done rotate (rotation) action, the injection rate in the left side of polysilicon lines is obviously than the lacking of right side and top, if utilize rotate (rotation), the left and right sides has been balance, but total injection rate lacking than the top of the left and right sides.
Fig. 1 b is vertical injection, and clearly, the injection rate of the sidewall of polysilicon lines will be far fewer than the top.
In a word, the injection mode of above-mentioned prior art all can not realize even 3Dization doping.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of nano-tube is mixed to realize the polysilicon lines homogenizing in the nano-tube structure, improves the performance of nano-tube.
Technical solution of the present invention is a kind of manufacture method of nano-tube, may further comprise the steps:
Thermal oxide growth silicon dioxide layer on silicon chip, deposit spathic silicon and silicon nitride successively on silicon dioxide layer;
Etch silicon nitride and polysilicon form the polysilicon lines that the top is coated with silicon nitride;
In polysilicon lines one side, carry out ion with first angle and inject;
Remove the silicon nitride on the polysilicon lines;
At the polysilicon lines opposite side, carry out ion with second angle and inject;
The thermal oxide growth silicon dioxide film forms nano-tube on polysilicon lines.
As preferably: described first angle and second angle be mirror image angle each other.
As preferably: described first angle or second angle are 20-30 °.
As preferably: the thickness of described silicon nitride is the 100-600 dust.
As preferably: described silicon nitride is removed with hot phosphoric acid.
Compared with prior art, the present invention adopts silicon nitride as injecting the barrier layer, makes the polysilicon lines surface evenly mix, make simultaneously follow-up on polysilicon lines the silicon dioxide film thickness of thermal oxide growth even, the performance of nano-tube improves.
Description of drawings
Fig. 1 a, 1b are the schematic diagrames that the prior art nano-tube mixes.
Fig. 2 is the making flow chart of nano-tube of the present invention.
Fig. 3 a-3f is the profile that nano-tube of the present invention is made each processing step in the flow process.
Embodiment
The present invention is further detailed in conjunction with the accompanying drawings below:
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
See also the making flow chart of nano-tube shown in Figure 2, in the present embodiment, the manufacturing process of described nano-tube is as follows,
In step 101, shown in Fig. 3 a, thermal oxide growth silicon dioxide layer 2 on silicon chip 1, deposit spathic silicon 3 and silicon nitride 4 successively on silicon dioxide layer 2, the thickness of described silicon nitride 4 need satisfy the thickness requirement that injects the barrier layer, but can not be too thick, too thick increase etching difficulty, can occur injecting shadow effect simultaneously, the thickness of described silicon nitride 4 is the 100-600 dust;
In step 102, shown in Fig. 3 b, etch silicon nitride 4 and polysilicon 3 form the polysilicon lines 31 that the top is coated with silicon nitride 41;
In step 103, shown in Fig. 3 c, in polysilicon lines 31 1 sides, carry out ion with first angle and inject, form light dope 32 in a side;
In step 104, shown in Fig. 3 d, remove the silicon nitride 41 on the polysilicon lines 31; The hot phosphoric acid of described silicon nitride 41 usefulness is removed.
In step 105, shown in Fig. 3 e, at the opposite side of polysilicon lines 31, carry out ion with second angle and inject, form light dope 32 at top and opposite side; Described first angle and second angle be mirror image angle each other.Described first angle or second angle are 20-30 °.
In step 106, shown in Fig. 3 f, thermal oxide growth silicon dioxide film 33 forms nano-tube 5 on polysilicon lines 31.The present invention adopts silicon nitride 41 as injecting barrier layers, makes polysilicon lines 31 surfaces evenly mix, make simultaneously follow-up on polysilicon lines 31 silicon dioxide film 33 thickness of thermal oxide growth even, thereby improve the performance of nano-tube.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (3)
1. the manufacture method of a nano-tube is characterized in that, may further comprise the steps:
Thermal oxide growth silicon dioxide layer on silicon chip, deposit spathic silicon and silicon nitride successively on silicon dioxide layer;
Etch silicon nitride and polysilicon form the polysilicon lines that the top is coated with silicon nitride;
In polysilicon lines one side, carry out ion with first angle and inject;
Remove the silicon nitride on the polysilicon lines;
At the polysilicon lines opposite side, carry out ion with second angle and inject;
The thermal oxide growth silicon dioxide film forms nano-tube on polysilicon lines;
Wherein, described first angle and second angle be mirror image angle each other, and described first angle or second angle are 20 °～30 °.
2. the manufacture method of nano-tube according to claim 1, it is characterized in that: the thickness of described silicon nitride is the 100-600 dust.
3. the manufacture method of nano-tube according to claim 1, it is characterized in that: described silicon nitride is removed with hot phosphoric acid.
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| CN 201110328166 CN102412121B (en) | 2011-10-25 | 2011-10-25 | Fabrication method for silicon nanotubes |
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| CN 201110328166 CN102412121B (en) | 2011-10-25 | 2011-10-25 | Fabrication method for silicon nanotubes |
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| CN102412121A CN102412121A (en) | 2012-04-11 |
| CN102412121B true CN102412121B (en) | 2013-08-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231944A (en) * | 2007-01-25 | 2008-07-30 | 友达光电股份有限公司 | Multiple layer structure including silicon nanometer die and manufacturing method thereof |
| CN101903289A (en) * | 2007-12-20 | 2010-12-01 | 拜尔技术服务有限责任公司 | Method for producing nitrogen-doped carbon nanotubes |
| CN102214586A (en) * | 2011-06-13 | 2011-10-12 | 西安交通大学 | Preparation method of silicon nano-wire field-effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000048929A (en) * | 1998-07-28 | 2000-02-18 | Mitsubishi Materials Corp | Surge absorber and its manufacture |
| WO2006057464A2 (en) * | 2004-11-29 | 2006-06-01 | Univ Tokyo Nat Univ Corp | Process for producing silicon nanofilamentous form |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231944A (en) * | 2007-01-25 | 2008-07-30 | 友达光电股份有限公司 | Multiple layer structure including silicon nanometer die and manufacturing method thereof |
| CN101903289A (en) * | 2007-12-20 | 2010-12-01 | 拜尔技术服务有限责任公司 | Method for producing nitrogen-doped carbon nanotubes |
| CN102214586A (en) * | 2011-06-13 | 2011-10-12 | 西安交通大学 | Preparation method of silicon nano-wire field-effect transistor |
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| JP特开2000-48929A 2000.02.18 |
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