CN102403345A - Film structure and method for isolation of SiGeHBT (silicon germanium heterojunction bipolar transistor) emitter from base - Google Patents
Film structure and method for isolation of SiGeHBT (silicon germanium heterojunction bipolar transistor) emitter from base Download PDFInfo
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- CN102403345A CN102403345A CN2010102807534A CN201010280753A CN102403345A CN 102403345 A CN102403345 A CN 102403345A CN 2010102807534 A CN2010102807534 A CN 2010102807534A CN 201010280753 A CN201010280753 A CN 201010280753A CN 102403345 A CN102403345 A CN 102403345A
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Abstract
The invention discloses a film structure and a method for isolation of a SiGeHBT (silicon germanium heterojunction bipolar transistor) emitter from a base. The SiGeHBT emitter and the base are in a composite film structure comprising silicon dioxide, polycrystalline silicon and silicon nitride from bottom to top. The novel film structure is used for isolation of the triode emitter from the base, and the over-etching quantity is reduced by decreasing the thickness of a silicon oxide dielectric layer so that increase of the lateral dimension is decreased. Simultaneously, generation and accumulation of repeatedly produced polymer are avoided by partial dry etching of the silicon dioxide, and the quantity of the silicon dioxide in dry etching is further decreased, so that increase of the lateral dimension is decreased. By the aid of the intrinsic polycrystalline silicon, thinning of the silicon oxide dielectric layer is realized, and small enough capacitance is maintained. The silicon nitride covered on the surface of the intrinsic polycrystalline silicon is capable of avoiding subsequent polycrystal of the emitter from doping and diffusing into the intrinsic polycrystal.
Description
Technical field
The present invention relates to a kind of semiconductor device structure and method, be specifically related to a kind of silicon-germanium heterojunction double-pole transistor and method.
Background technology
At present; In radio frequency applications; Need increasingly high device feature frequency, radio frequency complementary metal oxide semiconductors (CMOS) (RFCMOS) but is difficult to satisfy fully radio frequency requirement though in advanced person's technology, can realize upper frequency; Realize the characteristic frequency more than the 40GHz as being difficult to, and the R&D costs of advanced technologies also are very high; Compound semiconductor can be realized very high characteristic frequency device, but because the shortcoming that material cost is high, size is little adds that the most compounds semiconductor is poisonous, has limited its application.Silicon germanium hetero bipolar transistor (SiGe HBT) then is the fine selection of hyperfrequency device, and what at first it utilized SiGe and Si can be with difference, improves the charge carrier injection efficiency of emitter region, increases the current amplification factor of device; Next utilizes the highly doped of SiGe base, reduces base resistance, improves characteristic frequency; SiGe technology is compatible mutually with silicon technology basically in addition, so SiGe HBT has become the main force of hyperfrequency device.
In order to maximize device performance, requirement is as far as possible little the characteristic size of device work, and especially emitter-window has determined the maximum capacity that device can reach to a great extent.More little emitter window open area and lateral dimension reduce electric capacity more easily, and edge-crowding effect of current, improve device performance.As shown in Figure 1 because the technology opened of emitter-window normally realizes through wet etching, therefore normally layer of silicon dioxide as the isolation between emitter and the base stage.Open the amount at quarter of crossing that employing is bigger usually in order to guarantee window.Simultaneously because this layer silicon dioxide has carried out a part of dry method silicon dioxide etching earlier; Cause very heavy attaching the polymer buildup of producing on the surface; The normal etching that has stopped soup, therefore needing again further increases extra soup processing events, has further increased the over etching amount of wet method.So just cause emitter-window by horizontal expansion, can reduce device performance.
Summary of the invention
Technical problem to be solved by this invention provides the film layer structure of isolating between a kind of SiGe HBT emitter and the base stage; It can be used for the isolation between transistor emitter and the base stage, and reduction emitter-window that simultaneously can be as far as possible little is opened required over etching and suppressed emitter-window and enlarges.
In order to solve above technical problem, the invention provides the film layer structure of isolating between a kind of SiGe HBT emitter and the base stage; Between said silicon germanium hetero bipolar emitter and the base stage is the composite film structure, is respectively from bottom to top: silicon dioxide, polysilicon and silicon nitride.
Beneficial effect of the present invention is: propose a kind of new film layer structure; Be used for the isolation between transistor emitter and the base stage; Realize reducing the amount of over etching through the thickness that reduces the silica medium layer, reduce the increase of lateral dimension, heavily attach the generation and the accumulation of producing polymer through avoiding silicon dioxide part dry etching to avoid simultaneously; The amount of the silicon dioxide wet etching that further reduces reduces the increase of lateral dimension.Through intrinsic polysilicon, realize the attenuate of silica dioxide medium layer and keep enough little electric capacity.The silicon nitride of intrinsic polysilicon surface coverage can be avoided follow-up emitter polycrystalline to mix and diffuse into the intrinsic polycrystalline.
The present invention also provides the manufacture method of the film layer structure of isolating between a kind of SiGe HBT emitter and the base stage, comprises,
Said emitter-window etching realizes that through two step etchings after the lithographic definition emitter-window, the first step, dry etching are removed silicon nitride and polysilicon, are parked in silica surface;
Second the step, remove nethermost layer of silicon dioxide through wet etching.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is the traditional emitter and the sketch map of insulating barrier between the base stage and emitter-window;
Fig. 2 is insulating barrier and the emitter-window sketch map between described emitter of the embodiment of the invention and the base stage;
Fig. 3 is the flow chart of the said method of the embodiment of the invention.
Embodiment
The present invention proposes a kind of new film layer structure, is used for the isolation between transistor emitter and the base stage, and reduction emitter-window that simultaneously can be as far as possible little is opened required over etching and suppressed emitter-window and enlarges.
As shown in Figure 2, the present invention replaces traditional single-layer membrane structure with stacked structure, and the rete of composite stack structure is silicon dioxide, intrinsic polysilicon and silicon nitride from bottom to top.The thickness of said silicon dioxide is 50 to 200 dusts; The thickness of said polysilicon is 50 to 200 dusts.The thickness of said silicon nitride is 50 to 200 dusts.
As shown in Figure 3; The manufacture method of the film layer structure of isolating between SiGe HBT emitter of the present invention and the base stage; Comprise that said emitter-window etching realizes through two step etchings, after the lithographic definition emitter-window; First step dry etching is removed silicon nitride and polysilicon, is parked in silica surface; Second step was removed nethermost layer of silicon dioxide through wet etching.Said silicon dioxide deposit adopts low-pressure growth mode or normal pressure deposit to realize; Said polysilicon is with epitaxially grown mode deposit.
The present invention reduces over etching through the thickness that minimizes silicon dioxide, avoids lateral device dimensions to be enlarged.Through introducing the thickness that plain intrinsic polysilicon substitutes the original silicon dioxide of part.Because the dielectric coefficient of intrinsic silicon is also lower than silicon dioxide, can reduce electric capacity under the therefore same thickness.The present invention covers the thin silicon nitride of one deck through polysilicon surface, when avoiding back emitter polycrystalline deposition to the doping effect of intrinsic polysilicon layer.The technology that emitter-window of the present invention is opened changes into from original pure wet-etching technology and opens silicon nitride and polycrystalline through dry etching earlier; Because the etching polycrystalline has very high selection ratio to etching silicon dioxide, so the thickness of silicon dioxide can be accomplished extremely thin.
Film layer structure of the present invention; Be used for the isolation between transistor emitter and the base stage; Realize reducing the amount of over etching through the thickness that reduces the silica medium layer, reduce the increase of lateral dimension, heavily attach the generation and the accumulation of producing polymer through avoiding silicon dioxide part dry etching to avoid simultaneously; The amount of the silicon dioxide wet etching that further reduces reduces the increase of lateral dimension.Through intrinsic polysilicon, realize the attenuate of silica dioxide medium layer and keep enough little electric capacity.The silicon nitride of intrinsic polysilicon surface coverage can be avoided follow-up emitter polycrystalline to mix and diffuse into the intrinsic polycrystalline.
With an existing product is example, and the lateral dimension of product design emitter-window is 0.4um, adopts original film layer structure, and the lateral dimension of final emitter-window is 0.5um, enlarges 20%.Through adopting new film layer structure, the reduced thickness of silicon dioxide is to original 1/5, and the horizontal size of emitter-window only is 0.42 micron, only enlarges 5%.Satisfy the product design demand fully.
The present invention is not limited to the execution mode that preceding text are discussed.More than the description of embodiment is intended in order to describe and explain the technical scheme that the present invention relates to.Based on the conspicuous conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches the object of the invention.
Claims (6)
1. the film layer structure of isolating between SiGeHBT emitter and the base stage; It is characterized in that, be the composite film structure between said silicon germanium hetero bipolar emitter and the base stage, is respectively from bottom to top: silicon dioxide, polysilicon and silicon nitride.
2. the film layer structure of isolating between SiGeHBT emitter as claimed in claim 1 and the base stage is characterized in that, the thickness of said silicon dioxide is 50 to 200 dusts.
3. the film layer structure of isolating between SiGeHBT emitter as claimed in claim 1 and the base stage is characterized in that, the thickness of said polysilicon is 50 to 200 dusts.
4. the film layer structure of isolating between SiGeHBT emitter as claimed in claim 1 and the base stage is characterized in that, the thickness of said silicon nitride is 50 to 200 dusts.
5. the manufacture method of the film layer structure of isolating between SiGeHBT emitter as claimed in claim 1 and the base stage is characterized in that, comprising:
Said emitter-window etching realizes that through two step etchings after the lithographic definition emitter-window, the first step, dry etching are removed silicon nitride and polysilicon, are parked in silica surface;
Second the step, remove nethermost layer of silicon dioxide through wet etching.
6. the manufacture method of the film layer structure of isolating between SiGeHBT emitter as claimed in claim 5 and the base stage is characterized in that, said polysilicon is with epitaxially grown mode deposit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11355585B2 (en) | 2019-10-01 | 2022-06-07 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a charge control structure for a bipolar junction transistor |
| US11404540B2 (en) | 2019-10-01 | 2022-08-02 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a collector for a bipolar junction transistor |
| US11563084B2 (en) | 2019-10-01 | 2023-01-24 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming an emitter for a bipolar junction transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5106767A (en) * | 1990-12-07 | 1992-04-21 | International Business Machines Corporation | Process for fabricating low capacitance bipolar junction transistor |
| US5731617A (en) * | 1993-12-09 | 1998-03-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having bipolar transistor and field effect transistor |
| CN102104065A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Parasitic lateral PNP triode in SiGe heterojunction bipolar transistor process |
-
2010
- 2010-09-14 CN CN2010102807534A patent/CN102403345A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5106767A (en) * | 1990-12-07 | 1992-04-21 | International Business Machines Corporation | Process for fabricating low capacitance bipolar junction transistor |
| US5731617A (en) * | 1993-12-09 | 1998-03-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having bipolar transistor and field effect transistor |
| CN102104065A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Parasitic lateral PNP triode in SiGe heterojunction bipolar transistor process |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11355585B2 (en) | 2019-10-01 | 2022-06-07 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a charge control structure for a bipolar junction transistor |
| US11404540B2 (en) | 2019-10-01 | 2022-08-02 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a collector for a bipolar junction transistor |
| US11563084B2 (en) | 2019-10-01 | 2023-01-24 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming an emitter for a bipolar junction transistor |
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