CN102403295B - Metal bonded semiconductor package and method thereof - Google Patents
Metal bonded semiconductor package and method thereof Download PDFInfo
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- CN102403295B CN102403295B CN201010282198.9A CN201010282198A CN102403295B CN 102403295 B CN102403295 B CN 102403295B CN 201010282198 A CN201010282198 A CN 201010282198A CN 102403295 B CN102403295 B CN 102403295B
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- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
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Abstract
Description
技术领域 technical field
本发明涉及一种半导体封装及其方法,尤其涉及一种金属键接的半导体封装及其方法。The invention relates to a semiconductor package and a method thereof, in particular to a metal bonded semiconductor package and a method thereof.
背景技术 Background technique
封装对于芯片来说至关重要,它不仅起保护芯片和增强导热性能的作用,而且还是沟通芯片内部世界与外部电路的桥梁。目前,芯片制造规模的不断扩大以及巨大且快速成长的终端电子应用市场极大的推动了整个半导体封装产业的成长。为满足产品轻、薄、短、小与系统初步整合的需求,各样式的封装结构推陈出新。其中能符合轻薄短小与高密度要求的晶圆级封装渐渐受到重视。Packaging is very important to the chip. It not only protects the chip and enhances thermal conductivity, but also serves as a bridge between the internal world of the chip and the external circuit. At present, the continuous expansion of chip manufacturing scale and the huge and fast-growing terminal electronic application market have greatly promoted the growth of the entire semiconductor packaging industry. In order to meet the needs of light, thin, short, small products and initial system integration, various types of packaging structures have been introduced. Among them, wafer-level packaging that can meet the requirements of thin, light, short and high density has gradually attracted attention.
如图1所示,现有的封装包括引脚1、芯片基座2、粘合物3、芯片4、引线5及塑封体6。其中,在芯片封装的开始阶段,芯片基座2与引脚1为断开的,芯片基座2与引脚1之间留有空隙。在芯片的封装过程中,将芯片基座2及引脚1放置在芯片安装设备上,然后将粘合物3涂覆在芯片基座2上,接着将芯片4设置在粘合物3上。此时由于芯片4对粘合物3的挤压作用,加剧了粘合物3向芯片基座2四周的溢出,粘合物3甚至会从芯片基座3与引脚1之间的空隙中流入芯片安装设备上,造成芯片安装设备的污染。As shown in FIG. 1 , an existing package includes a lead 1 , a chip base 2 , an adhesive 3 , a chip 4 , leads 5 and a plastic package 6 . Wherein, at the initial stage of chip packaging, the chip base 2 and the pin 1 are disconnected, and there is a gap between the chip base 2 and the pin 1 . During the packaging process of the chip, the chip base 2 and the pins 1 are placed on the chip mounting equipment, then the adhesive 3 is coated on the chip base 2 , and then the chip 4 is arranged on the adhesive 3 . At this time, due to the extrusion effect of the chip 4 on the adhesive 3, the overflow of the adhesive 3 to the periphery of the chip base 2 is exacerbated, and the adhesive 3 will even flow from the gap between the chip base 3 and the pin 1. It flows into the chip mounting equipment, causing contamination of the chip mounting equipment.
现有技术中,芯片封装的开始阶段,除了芯片基座与引脚之间断开外,芯片基座与芯片基座之间也为断开状态,芯片基座与芯片基座之间也存有间隙,如图2所示,为现有技术中金属键接的半导体封装的截面示意图,该结构包括引脚1’、芯片基座2’、粘合物3’、芯片4’及连接片5’。如图2的第一行图形所示,芯片基座2’与芯片基座2’之间留有空隙d1,芯片基座2’与引脚1’之间也留有空隙d2。如图2的第二行图形所示,当在同样大小的芯片基座2’上增大芯片4’的面积时,会使芯片4’下面的粘合物3’向芯片基座2’的边缘溢出。如图2的第三行图形所示,粘合物3’甚至会流入芯片基座2’与芯片基座2’之间的空隙及芯片基座2’与引脚1’之间的空隙内,对芯片安装设备的污染。因而在实际的工艺制作中,为了避免上述粘合物的溢出对芯片安装设备造成的污染,基于不同的粘合物,规定了安装距离要求,即在规定了封装尺寸的前提下,减小芯片的面积,或者规定了芯片面积的前提下,增大封装尺寸。而该措施大大降低了半导体封装体内芯片的利用率。In the prior art, in the initial stage of chip packaging, in addition to the disconnection between the chip base and the pins, the chip base and the chip base are also in a disconnected state, and there is also a gap between the chip base and the chip base , as shown in FIG. 2 , is a schematic cross-sectional view of a metal-bonded semiconductor package in the prior art, and the structure includes a pin 1', a chip base 2', an adhesive 3', a chip 4' and a connecting piece 5' . As shown in the first row of figures in Fig. 2, there is a gap d1 between the chip base 2' and the chip base 2', and a gap d2 is also left between the chip base 2' and the pin 1'. As shown in the second row of figures of Figure 2, when increasing the area of the chip 4' on the chip base 2' of the same size, the bonding material 3' below the chip 4' will move toward the surface of the chip base 2'. The edges overflow. As shown in the third row of Figure 2, the adhesive 3' will even flow into the gap between the chip base 2' and the chip base 2' and the gap between the chip base 2' and the pin 1' , Contamination of chip mounting equipment. Therefore, in the actual process, in order to avoid the pollution caused by the overflow of the above-mentioned adhesives to the chip mounting equipment, based on different adhesives, the requirements for the installation distance are stipulated, that is, under the premise of specifying the package size, the size of the chip can be reduced. The area, or under the premise of specifying the chip area, increase the package size. This measure greatly reduces the utilization rate of chips in the semiconductor package.
发明内容 Contents of the invention
本发明的目的是提供一种金属片键接的封装方法,该封装方法能有效的防止芯片安装时粘合物的溢出所造成的对芯片安装设备的污染,并且大大增加了封装体内芯片的利用率,降低了封装成本,并且该封装方法简单,易操作。The purpose of the present invention is to provide a packaging method of metal sheet bonding, which can effectively prevent the pollution of the chip mounting equipment caused by the overflow of adhesives during chip mounting, and greatly increase the utilization of chips in the package. The efficiency reduces the packaging cost, and the packaging method is simple and easy to operate.
为了达到上述目的,本发明提出的一种金属键接的半导体封装,包括:In order to achieve the above object, a metal-bonded semiconductor package proposed by the present invention includes:
一引线框架,所述引线框架包括芯片基座及引脚,所述芯片基座上表面设置至少一个基座凹槽,所述基座凹槽将整个芯片基座区分为多个芯片安装区域,所述引脚设置在芯片基座附近;A lead frame, the lead frame includes a chip base and pins, at least one base groove is provided on the upper surface of the chip base, and the base groove divides the entire chip base into a plurality of chip mounting areas, The pins are arranged near the chip base;
多个芯片,所述多个芯片通过粘合物对应设置在芯片基座的各个芯片安装区域,所述芯片包括多个顶部电极;A plurality of chips, the plurality of chips are correspondingly arranged on each chip mounting area of the chip base through adhesives, and the chips include a plurality of top electrodes;
至少一个金属片,用于芯片之间的连接;At least one metal sheet for connection between chips;
一塑封体,塑封所述芯片基座、引脚、芯片及金属片。A plastic packaging body, which plastic-packages the chip base, pins, chips and metal sheets.
上述的一种金属键接的半导体封装,基座凹槽底部断开将芯片基座上的多个芯片安装区域分割为互不连接的芯片安装区域,凹槽底部断开宽度小于凹槽宽度。In the aforementioned metal-bonded semiconductor package, the disconnection at the bottom of the base groove divides multiple chip mounting areas on the chip base into chip mounting areas that are not connected to each other, and the disconnection width at the bottom of the groove is smaller than the width of the groove.
上述的一种金属键接的半导体封装,所述多个芯片包括第一芯片和第二芯片,所述多个芯片安装区域包括第一芯片安装区域和第二芯片安装区域,所述第一芯片设置在第一芯片安装区域上,所述第二芯片设置在第二芯片安装区域上,所述第二芯片包括底部电极并电连接至第二芯片安装区域。In the aforementioned metal bonded semiconductor package, the multiple chips include a first chip and a second chip, and the multiple chip mounting areas include a first chip mounting area and a second chip mounting area, and the first chip Disposed on the first chip mounting area, the second chip is disposed on the second chip mounting area, the second chip includes a bottom electrode and is electrically connected to the second chip mounting area.
上述的一种金属键接的半导体封装,所述金属片的一端电连接第一芯片的顶部电极,其另一端设置在基座凹槽内靠近第二芯片安装区域的位置。In the aforementioned metal-bonded semiconductor package, one end of the metal sheet is electrically connected to the top electrode of the first chip, and the other end is disposed in the groove of the base near the mounting area of the second chip.
上述的一种金属键接的半导体封装,所述基座凹槽底部断开将所述第一芯片安装区域和第二芯片安装区域分割为互不连接的芯片安装区域,凹槽底部断开宽度小于凹槽宽度。In the above-mentioned metal bonded semiconductor package, the bottom of the groove of the base is disconnected to divide the first chip mounting area and the second chip mounting area into chip mounting areas that are not connected to each other, and the width of the bottom of the groove is broken smaller than the groove width.
上述的一种金属键接的半导体封装,所述粘合物从第一芯片安装区域上溢出到靠近第一芯片安装区域的基座凹槽的底部角落。In the aforementioned metal-bonding semiconductor package, the adhesive overflows from the first chip mounting area to the bottom corner of the base recess near the first chip mounting area.
上述的一种金属键接的半导体封装,所述粘合物为导电粘合物。In the aforementioned metal bonded semiconductor package, the adhesive is a conductive adhesive.
本发明提供另外一种金属键接的半导体封装,包括:The present invention provides another metal-bonded semiconductor package, including:
一引线框架,所述引线框架包括芯片基座及引脚,所述引脚设置在芯片基座附近,且所述引脚与所述芯片基座之间设有基座与引脚间凹槽,所述基座与引脚间凹槽底部断开将芯片基座及引脚分割为互不连接的芯片基座及引脚,凹槽底部断开宽度小于凹槽宽度,所述芯片基座上设有芯片安装区域;A lead frame, the lead frame includes a chip base and pins, the pins are arranged near the chip base, and a groove between the base and the pins is provided between the pins and the chip base , the bottom of the groove between the base and the pins is disconnected to divide the chip base and the pins into chip bases and pins that are not connected to each other, the width of the bottom of the groove is less than the width of the groove, and the chip base There is a chip mounting area on it;
一通过粘合剂设置在芯片安装区域上的芯片,所述芯片包括数个顶部电极;a chip disposed on the chip mounting area by an adhesive, said chip comprising a plurality of top electrodes;
一金属连接用于连接芯片的顶部电极及引脚;A metal connection is used to connect the top electrodes and pins of the chip;
一塑封体,用以塑封芯片基座、引脚、芯片及金属连接。A plastic encapsulation body, used for plastic encapsulation of the chip base, pins, chip and metal connection.
上述的一种金属键接的半导体封装,所述金属连接包括一金属片,所述金属片的一端连接芯片的顶部电极,另一端设置在所述基座与引脚间凹槽内靠近引脚的位置,用于芯片的顶部电极与引脚的连接。In the aforementioned semiconductor package with metal bonding, the metal connection includes a metal sheet, one end of the metal sheet is connected to the top electrode of the chip, and the other end is arranged in the groove between the base and the pin close to the pin The position of the chip is used to connect the top electrodes of the chip to the pins.
上述的一种金属键接的半导体封装,所述粘合剂从芯片安装区域上溢出到靠近芯片安装区域的基座与引脚间凹槽的底部角落。In the aforementioned metal-bonded semiconductor package, the adhesive overflows from the chip mounting area to the bottom corner of the groove between the base and the pins near the chip mounting area.
本发明还提供一种金属键接的半导体封装,包括:The present invention also provides a metal bonded semiconductor package, comprising:
一引线框架,所述引线框架包括芯片基座及引脚,所述芯片基座上设有至少一个基座凹槽,所述基座凹槽将芯片基座区分为多个芯片安装区域,基座凹槽底部断开将芯片基座上的多个芯片安装区域分割为互不连接的芯片安装区域,所述引脚设置在芯片基座的附近,且所述引脚与所述芯片基座之间设有基座与引脚间凹槽,所述基座与引脚间凹槽底部断开将基座及引脚分割为互不连接的芯片基座及引脚,凹槽底部断开宽度小于凹槽宽度;A lead frame, the lead frame includes a chip base and pins, the chip base is provided with at least one base groove, the base groove divides the chip base into a plurality of chip mounting areas, the base The bottom of the seat groove is disconnected to divide the multiple chip mounting areas on the chip base into chip mounting areas that are not connected to each other, the pins are arranged near the chip base, and the pins are connected to the chip base There is a groove between the base and the pins, the bottom of the groove between the base and the pins is disconnected, the base and the pins are divided into chip bases and pins that are not connected to each other, and the bottom of the groove is disconnected the width is less than the groove width;
多个芯片,所述芯片通过粘合剂设置在其对应的芯片安装区域上;a plurality of chips disposed on their corresponding chip mounting areas via an adhesive;
多个金属连接用于芯片之间的连接及芯片与引脚之间的连接;Multiple metal connections for connections between chips and connections between chips and pins;
一塑封体,用以塑封芯片基座、引脚、芯片及金属连接。A plastic encapsulation body, used for plastic encapsulation of the chip base, pins, chip and metal connection.
上述的一种金属键接的半导体封装,所述粘合剂从芯片基座区上溢出到靠近芯片基座区的基座与引脚间凹槽的底部角落。In the aforementioned metal-bonded semiconductor package, the adhesive overflows from the chip base area to the bottom corner of the groove between the base and the pins near the chip base area.
上述的一种金属键接的半导体封装,所述金属连接包括一个金属片,所述的金属片一端设置在所述基座与引脚间凹槽内靠近引脚的位置,用于芯片的顶部电极与引脚的连接。In the above-mentioned semiconductor package with metal bonding, the metal connection includes a metal sheet, and one end of the metal sheet is arranged in the groove between the base and the pin near the pin for the top of the chip Connection of electrodes to pins.
本发明的一种金属键接的半导体封装方法,包括以下步骤:A metal-bonded semiconductor packaging method of the present invention comprises the following steps:
步骤1:提供一引线框架,所述引线框架包括芯片基座及引脚,在所述芯片基座上表面设置至少一个基座凹槽,所述基座凹槽将整个芯片基座区分为多个芯片安装区域,所述引脚设置在芯片基座的附近;Step 1: provide a lead frame, the lead frame includes a chip base and pins, at least one base groove is provided on the upper surface of the chip base, and the base groove divides the entire chip base into multiple parts. a chip mounting area, the pins are arranged near the chip base;
步骤2:提供多个芯片,通过粘合物将所述多个芯片安装在对应的芯片基座的各个芯片安装区域,所述芯片包括多个顶部电极;Step 2: providing a plurality of chips, mounting the plurality of chips on respective chip mounting areas of the corresponding chip base through an adhesive, the chips including a plurality of top electrodes;
步骤3:提供至少一个金属连接,用于连接芯片的顶部电极;Step 3: providing at least one metal connection for connecting the top electrode of the chip;
步骤4:提供一塑封体,塑封所述芯片基座、引脚、芯片及金属连接;Step 4: Provide a plastic package, and plastic seal the chip base, pins, chips and metal connections;
步骤5:将基座凹槽底部断开,从而将相互连接的芯片安装区域分割为互不连接的各个芯片安装区域,凹槽底部断开宽度小于凹槽宽度。Step 5: Disconnect the bottom of the groove of the base, so as to divide the interconnected chip mounting regions into individual chip mounting regions that are not connected to each other, and the disconnection width at the bottom of the groove is smaller than the width of the groove.
上述的一种金属键接的半导体封装方法,在步骤2中,通过第一粘合物安装第一芯片在第一芯片安装区域上,所述第一粘合物从第一芯片安装区域上溢出到靠近第一芯片安装区域的基座凹槽的底部角落,通过第二粘合物安装第二芯片在第二芯片安装区域上,第二芯片包括一底部电极与第二芯片安装区域电学连接,所述第二粘合物从第二芯片安装区域上溢出到靠近第二芯片安装区域的基座凹槽的底部角落。In the above semiconductor packaging method with metal bonding, in step 2, the first chip is installed on the first chip mounting area through the first adhesive, and the first adhesive overflows from the first chip mounting area to the bottom corner of the base recess close to the first chip mounting area, mounting a second chip on the second chip mounting area through a second adhesive, the second chip including a bottom electrode electrically connected to the second chip mounting area, The second adhesive overflows from the second chip mounting area to a bottom corner of the base groove near the second chip mounting area.
上述的一种金属键接的半导体封装方法,在步骤3中,所述提供至少一个金属连接包括提供第一金属片,其一端连接第一芯片的一个顶部电极,其另一端设置在基座凹槽内靠近第二芯片安装区的位置,与第二芯片的底部电极电学连接。In the above semiconductor packaging method with metal bonding, in step 3, the providing at least one metal connection includes providing a first metal sheet, one end of which is connected to a top electrode of the first chip, and the other end is arranged in the recess of the base. The position in the groove close to the second chip mounting area is electrically connected to the bottom electrode of the second chip.
上述的一种金属键接的半导体封装方法,在步骤1中,所述引脚与所述芯片基座之间设有基座与引脚间凹槽。In the above metal bonding semiconductor packaging method, in step 1, a groove between the base and the pin is provided between the pin and the chip base.
上述的一种金属键接的半导体封装方法,在步骤5中,还包括从塑封体底部将基座与引脚间凹槽的底部断开,以分割芯片基座及引脚。The above metal bonding semiconductor packaging method, in step 5, further includes breaking the base and the bottom of the groove between the pins from the bottom of the plastic package to separate the chip base and the pins.
上述的一种金属键接的半导体封装方法,在步骤3中,提供第二金属片一端连接第二芯片的一个顶部电极,其另一端设置在基座与引脚间凹槽内靠近引脚的位置与引脚电学连接。In the above semiconductor packaging method of metal bonding, in step 3, one end of the second metal sheet is provided to connect to a top electrode of the second chip, and the other end is arranged in the groove between the base and the pin near the pin. The location is electrically connected to the pin.
本发明的一种金属键接的半导体封装方法,包括以下步骤:A metal-bonded semiconductor packaging method of the present invention comprises the following steps:
步骤1:提供一引线框架,所述引线框架包括芯片基座及引脚,所述引脚设置在芯片基座的附近,所述引脚与所述芯片基座连接在一起,且所述引脚与所述芯片基座之间设有基座与引脚间凹槽,所述芯片基座上设有芯片安装区域;Step 1: provide a lead frame, the lead frame includes a chip base and pins, the pins are arranged near the chip base, the pins are connected to the chip base, and the lead A groove between the base and the pins is provided between the foot and the chip base, and a chip mounting area is provided on the chip base;
步骤2:提供至少一芯片,通过粘合剂将所述芯片设置在芯片安装区域上,所述芯片包括数个顶部电极;Step 2: providing at least one chip, disposing the chip on the chip mounting area through an adhesive, the chip including a plurality of top electrodes;
步骤3:提供金属连接以连接芯片的顶部电极与引脚;Step 3: Provide metal connections to connect the top electrodes of the chip to the pins;
步骤4:提供一塑封体,用以塑封芯片基座、引脚、芯片及金属连接;Step 4: Provide a plastic package for plastic packaging the chip base, pins, chips and metal connections;
步骤5:从塑封体底部将基座与引脚间凹槽的底部断开,以分割芯片基座及引脚。Step 5: Disconnect the base and the bottom of the groove between the pins from the bottom of the plastic package to separate the chip base and pins.
上述的一种金属键接的半导体封装方法,在步骤2中,通过粘合物安装所述芯片在芯片基座上,所述粘合物从基座上上溢出到靠近芯片基座的基座与引脚间凹槽的底部角落。In the above-mentioned semiconductor packaging method with metal bonding, in step 2, the chip is mounted on the chip base through an adhesive, and the adhesive overflows from the base to a base close to the chip base and the bottom corner of the notch between the pins.
上述的一种金属键接的半导体封装方法,在步骤3中,所述提供金属连接包括提供第一金属片一端连接第一芯片的一个顶部电极,其另一端设置在基座与引脚间凹槽内靠近引脚的位置,与引脚电学连接。In the above-mentioned metal bonding semiconductor packaging method, in step 3, the providing metal connection includes providing one end of the first metal sheet connected to a top electrode of the first chip, and the other end of which is arranged in the recess between the base and the pin. The position in the groove close to the pin is electrically connected with the pin.
上述的一种金属键接的半导体封装方法,在步骤1中,所述芯片基座上设有至少一个基座凹槽,所述基座凹槽将芯片基座区分为多个芯片安装区域。In the above metal bonding semiconductor packaging method, in step 1, at least one base groove is provided on the chip base, and the base groove divides the chip base into a plurality of chip mounting regions.
上述的一种金属键接的半导体封装方法,在步骤5中,还包括从塑封体底部将基座与引脚间凹槽的底部断开,以分割芯片基座及引脚。The above metal bonding semiconductor packaging method, in step 5, further includes breaking the base and the bottom of the groove between the pins from the bottom of the plastic package to separate the chip base and the pins.
本发明的一种金属键接的半导体封装方法,包括以下步骤:A metal-bonded semiconductor packaging method of the present invention comprises the following steps:
步骤1:提供一引线框架,所述引线框架包括芯片基座及引脚,所述芯片基座上设有至少一个基座凹槽,所述基座凹槽将芯片基座区分为多个芯片安装区域,所述引脚设置在芯片基座的周围,所述引脚与所述芯片基座连接在一起,且所述引脚与所述芯片基座之间设有基座与引脚间凹槽,所述基座与引脚间凹槽用以区分所述引脚与所述芯片基座;Step 1: Provide a lead frame, the lead frame includes a chip base and pins, the chip base is provided with at least one base groove, and the base groove divides the chip base into a plurality of chips In the installation area, the pins are arranged around the chip base, the pins are connected to the chip base, and there is a space between the base and the pins between the pins and the chip base. a groove, the groove between the base and the pin is used to distinguish the pin from the chip base;
步骤2:提供至少一个芯片,所述芯片通过粘合剂设置在其对应的芯片安装区域上,所述芯片包括底部电极及多个顶部电极;Step 2: providing at least one chip, the chip is disposed on its corresponding chip mounting area through an adhesive, and the chip includes a bottom electrode and a plurality of top electrodes;
步骤3:提供多个金属片,所述金属片一端与芯片顶部电极连接,其另一端设置在基座凹槽内,用于芯片之间的连接,所述金属片一端与芯片顶部电极连接,其另一端设置在基座与引脚间凹槽内,用于芯片与引脚之间的连接;Step 3: Provide a plurality of metal sheets, one end of the metal sheet is connected to the electrode on the top of the chip, and the other end is set in the groove of the base for connection between chips, one end of the metal sheet is connected to the electrode on the top of the chip, The other end is set in the groove between the base and the pin for connection between the chip and the pin;
步骤4:提供引线,所述引线连接芯片的顶部电极及引脚;Step 4: providing leads, which are connected to the top electrodes and pins of the chip;
步骤5:一塑封体,用以塑封芯片基座、引脚、多个芯片及金属片;Step 5: a plastic package, used to plastic chip base, pins, multiple chips and metal sheets;
步骤6:从塑封体底部将基座凹槽的底部切断,以将芯片基座分割为互不连接的芯片安装区域,从塑封体底部将基座与引脚间凹槽的底部切断,以分割芯片基座及引脚。Step 6: Cut off the bottom of the base groove from the bottom of the plastic package to divide the chip base into discrete chip mounting areas, cut off the bottom of the groove between the base and the pins from the bottom of the plastic package to divide Chip base and pins.
本发明金属片键接的封装方法由于采用上述技术方案,使之与现有技术相比,具有以下优点和积极效果:Compared with the prior art, the metal sheet bonding packaging method of the present invention has the following advantages and positive effects due to the adoption of the above-mentioned technical scheme:
1、本发明的金属片键接的封装方法由于在芯片封装的开始阶段,使芯片基座之间以及芯片基座与引脚之间连接在一起,芯片基座之间以及芯片基座与引脚之间没有空隙暴露在芯片安装设备上,因此避免了芯片安装时,粘合物的溢出对芯片安装设备的污染。1. The packaging method of the metal sheet bonding of the present invention connects between the chip bases and between the chip base and the pins at the initial stage of chip packaging, and between the chip bases and between the chip base and the leads. There is no gap between the feet exposed to the chip mounting equipment, thus avoiding the contamination of the chip mounting equipment by overflow of the adhesive during chip mounting.
2、本发明的金属片键接的封装方法由于在芯片基座之间以及芯片基座与引脚之间连接的部位设置凹槽,防止了粘合物过量溢出而堆积以污染芯片的表面。2. The packaging method of the metal sheet bonding of the present invention prevents adhesives from excessively overflowing and accumulating to pollute the surface of the chip due to the provision of grooves between the chip bases and the connection between the chip base and the pins.
3、本发明的金属片键接的封装方法简单易操作,制作成本低。3. The packaging method of metal sheet bonding of the present invention is simple and easy to operate, and has low production cost.
附图说明 Description of drawings
参考所附附图,以更加充分的描述本发明的实施例。然而,所附附图仅用于说明和阐述,并不构成对本发明范围的限制。Embodiments of the present invention are more fully described with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and do not limit the scope of the present invention.
图1为现有半导体封装结构的横截面视图。FIG. 1 is a cross-sectional view of a conventional semiconductor package structure.
图2为以三幅图说明粘合物溢出的现有半导体封装结构的横截面视图。2 is a cross-sectional view of a conventional semiconductor package structure illustrating adhesive overflow in three views.
图3为实施例一的金属键接的半导体封装方法流程图。FIG. 3 is a flow chart of the metal bonding semiconductor packaging method of the first embodiment.
图4为实施例一中所提供的引线框架的俯视图及横截面视图。FIG. 4 is a top view and a cross-sectional view of the lead frame provided in the first embodiment.
图5为实施例一中将芯片通过粘合物设置在引线框架上的俯视图及横截面视图。FIG. 5 is a top view and a cross-sectional view of setting the chip on the lead frame through the adhesive in the first embodiment.
图6为实施例一中用金属片键接芯片电极与引脚的俯视图及横截面视图。FIG. 6 is a top view and a cross-sectional view of bonding chip electrodes and pins with metal sheets in Embodiment 1. FIG.
图7为实施例一中用引线连接芯片电极及引脚的俯视图及横截面视图。FIG. 7 is a top view and a cross-sectional view of connecting chip electrodes and pins with wires in Embodiment 1. FIG.
图8为实施例一中用塑封体塑封的俯视图及横截面视图。Fig. 8 is a top view and a cross-sectional view of plastic sealing with a plastic sealing body in the first embodiment.
图9为实施例一中在塑封体底部切割基座凹槽底面的俯视图及横截面视图。FIG. 9 is a top view and a cross-sectional view of cutting the bottom surface of the base groove at the bottom of the plastic package in Embodiment 1. FIG.
图10为实施例二的金属键接的半导体封装方法流程图。FIG. 10 is a flow chart of the metal bonding semiconductor packaging method of the second embodiment.
图11为实施例二中所提供引线框架的俯视图及横截面视图。FIG. 11 is a top view and a cross-sectional view of the lead frame provided in the second embodiment.
图12为实施例二中将芯片设置在引线框架上的俯视图及横截面视图。FIG. 12 is a top view and a cross-sectional view of setting the chip on the lead frame in the second embodiment.
图13为实施例二中用金属片键接芯片电极及引脚的俯视图及横截面视图。13 is a top view and a cross-sectional view of bonding chip electrodes and pins with metal sheets in Embodiment 2.
图14为实施例二中用引线连接芯片电极与引脚的俯视图及横截面视图。Fig. 14 is a top view and a cross-sectional view of connecting chip electrodes and pins with wires in Embodiment 2.
图15为实施例二中塑封体塑封的俯视图及横截面视图。Fig. 15 is a top view and a cross-sectional view of the plastic package of the plastic package in the second embodiment.
图16为实施例二中切割塑封体底部的基座与引脚间凹槽底面的俯视图及横截面视图。FIG. 16 is a top view and a cross-sectional view of the base and the bottom surface of the groove between the pins in the second embodiment of cutting the bottom of the plastic package.
图17为实施例三的金属键接的半导体封装结构的横截面视图。FIG. 17 is a cross-sectional view of the metal-bonded semiconductor package structure of the third embodiment.
具体实施方式 Detailed ways
实施例一:本发明提供一种金属片键接的封装方法,该封装方法的封装结构包括引线框架110、粘合物120、芯片130、140、金属片150、引线160及塑封体170,该金属片键接的半导体封装流程图如图3所示,其具体的封装过程如下:Embodiment 1: The present invention provides a metal sheet bonding packaging method. The packaging structure of the packaging method includes a lead frame 110, an adhesive 120, chips 130, 140, a metal sheet 150, a lead 160, and a plastic package 170. The semiconductor packaging flow chart of metal sheet bonding is shown in Figure 3, and the specific packaging process is as follows:
如图4所示,首先提供一引线框架110,引线框架110包括芯片基座115及多个引脚。图4中上一幅图为引线框架的俯视图,其下一幅图为沿上一幅图形中虚线位置的截面图。芯片基座115包括第一芯片安装区域1151、第二芯片安装区域1152以及基座凹槽1153,基座凹槽1153设置在芯片安装区域之间,可以区分各个芯片安装区域。在实际的应用中,芯片基座上可以设置多个芯片安装区域,并可设置多个基座凹槽加以区分。本实施例仅以在引线框架上设置两个芯片安装区域及一个基座凹槽为例。如图4所示,多个引脚还包括引脚111、引脚112、引脚113及引脚114,其中引脚111与芯片基座1151连接,即引脚111与芯片底部电极导电连接;引脚112、113及144分别断开一个间距设置在芯片基座115的两边,这些引脚分别与芯片的电极对应。As shown in FIG. 4 , firstly, a lead frame 110 is provided, and the lead frame 110 includes a chip base 115 and a plurality of pins. The previous figure in FIG. 4 is a top view of the lead frame, and the next figure is a cross-sectional view along the dotted line in the previous figure. The chip base 115 includes a first chip mounting area 1151 , a second chip mounting area 1152 and a base groove 1153 . The base groove 1153 is disposed between the chip mounting areas and can distinguish each chip mounting area. In practical applications, multiple chip mounting regions can be set on the chip base, and multiple base grooves can be set to distinguish them. In this embodiment, two chip mounting regions and one base groove are provided on the lead frame as an example. As shown in Figure 4, the multiple pins also include pins 111, 112, 113 and 114, wherein the pin 111 is connected to the chip base 1151, that is, the pin 111 is conductively connected to the bottom electrode of the chip; The pins 112 , 113 and 144 are arranged on both sides of the chip base 115 separated by a distance, and these pins respectively correspond to the electrodes of the chip.
如图5所示,由于本实施例中引线框架上仅设置两个芯片安装区域,因此提供两个芯片。两个芯片分别为第一芯片130及第二芯片140,第一芯片130及第二芯片140分别以高端金属氧化物半导体场效应晶体管(HS MOSFET)及低端金属氧化物半导体场效应晶体管(LS MOSFET)为例。HS MOSFET及LS MOSFET分别包括顶部源极、栅极以及底部漏极。通过粘合物120将第一芯片130和第二芯片140分别设置在第一芯片安装区域1151及第二芯片安装区域1152上,粘合物120起导电粘结的作用。优选地,该粘合物120为导电银浆。在具体的工艺操作中,首先将导电银浆涂布在芯片安装区域上,然后将芯片设置在导电银浆上。通常情况下,导电银浆会在芯片安装区域上溢出,尤其是芯片放置在导电银浆上之后,芯片的重力会加剧导电银浆的溢出。在本实施例中,如图5所示,导电银浆将会慢慢溢出流向基座凹槽1153内。从第而一芯片安装区域1151溢出的粘合物累积在基座凹槽靠近第一芯片安装区域的底部角落,从第二芯片安装区域1152溢出的粘合物累积在基座凹槽靠近第二芯片安装区域的底部角落。现有技术中,由于芯片安装区域之间为断开的,导电银浆会从芯片安装区域溢出并通过安装区域之间的空隙,进而污染设置在引线框架下面的芯片安装设备,因此在进行芯片封装时,要考虑芯片与芯片安装区域边缘的间距,从而限制了芯片封装的尺寸。在本实施例中,芯片安装区域之间的基座凹槽结构收集了溢出的粘合物,防止其流入芯片安装设备,芯片边缘到芯片安装区域边缘的距离一般大于3mils即可,而传统的芯片边缘到芯片安装区域边缘的距离一般需要大于8~10mils。因此本发明中封装体内芯片的利用率有明显提高。As shown in FIG. 5 , since only two chip mounting regions are provided on the lead frame in this embodiment, two chips are provided. The two chips are respectively a first chip 130 and a second chip 140, and the first chip 130 and the second chip 140 are respectively made of a high-end metal oxide semiconductor field effect transistor (HS MOSFET) and a low-side metal oxide semiconductor field effect transistor (LS MOSFET). MOSFET) as an example. HS MOSFET and LS MOSFET include top source, gate and bottom drain respectively. The first chip 130 and the second chip 140 are respectively disposed on the first chip mounting area 1151 and the second chip mounting area 1152 through the adhesive 120 , and the adhesive 120 functions as a conductive bond. Preferably, the adhesive 120 is conductive silver paste. In a specific process operation, the conductive silver paste is first coated on the chip mounting area, and then the chip is placed on the conductive silver paste. Usually, the conductive silver paste will overflow on the chip mounting area, especially after the chip is placed on the conductive silver paste, the gravity of the chip will aggravate the overflow of the conductive silver paste. In this embodiment, as shown in FIG. 5 , the conductive silver paste will slowly overflow into the groove 1153 of the base. Adhesive overflowing from the first chip mounting area 1151 accumulates in the base groove near the bottom corner of the first chip mounting area, and adhesive overflowing from the second chip mounting area 1152 accumulates in the base groove adjacent to the second bottom corner of the chip mounting area. In the prior art, since the chip mounting areas are disconnected, the conductive silver paste will overflow from the chip mounting areas and pass through the gaps between the mounting areas, thereby contaminating the chip mounting equipment arranged under the lead frame. When packaging, the distance between the chip and the edge of the chip mounting area should be considered, thus limiting the size of the chip package. In this embodiment, the groove structure of the base between the chip mounting areas collects the overflowing adhesive and prevents it from flowing into the chip mounting equipment. The distance from the edge of the chip to the edge of the chip mounting area is generally greater than 3 mils, while the traditional The distance from the edge of the chip to the edge of the chip mounting area generally needs to be greater than 8-10 mils. Therefore, the utilization rate of the chip in the package in the present invention is obviously improved.
如图6所示,芯片设置在芯片安装区域上之后,提供一金属片150,金属片150的一端1501设置在第一芯片130的顶部源极上,其另一端1502设置在基座凹槽153内靠近第二芯片140的位置。在现有封装技术中,由于没有设置基座凹槽,金属片150的一端1502与第二芯片140共同设置在第二芯片安装区域1152上。为防止金属片150的一端1502下部的粘合物与第二芯片140下部的粘合物产生溢出而堆积,甚至造成粘合物的攀爬而影响芯片表面的电路性能,金属片150的一端1502与第二芯片140之间具有一定的设置距离的需要。而在本实施例中,金属片150的一端1502设置在基座凹槽1153内,基座凹槽1153具有一定的高度,再加上第二芯片140本身的厚度,金属片的一端1502下部及第二芯片140下部的粘合物的溢出产生攀爬至第二芯片140表面而影响电路性能的可能性降低。因此金属片的一端1502与第二芯片140之间的距离可缩短,第一芯片1501与第二芯片1502之间的距离也可缩短。在本实施例中,芯片边缘到芯片边缘的距离大于5mils即可适合封装,而在传统的封装中,芯片边缘到芯片边缘的距离需大于20mils,由此可见,本实施例中的凹槽结构提高了封装体中芯片的利用率,节约了成本。此外金属片150也可由引线或带状连接线替代。As shown in Figure 6, after the chip is placed on the chip mounting area, a metal sheet 150 is provided, one end 1501 of the metal sheet 150 is arranged on the top source of the first chip 130, and the other end 1502 is arranged on the base groove 153 The inner position is close to the second chip 140 . In the existing packaging technology, since the base groove is not provided, the one end 1502 of the metal sheet 150 and the second chip 140 are jointly arranged on the second chip mounting area 1152 . In order to prevent the adhesive at the lower part of one end 1502 of the metal sheet 150 from overflowing and accumulating with the adhesive at the lower part of the second chip 140, and even cause the adhesive to climb and affect the circuit performance of the chip surface, one end 1502 of the metal sheet 150 It is necessary to have a certain distance from the second chip 140 . And in this embodiment, one end 1502 of the metal sheet 150 is arranged in the base groove 1153, the base groove 1153 has a certain height, plus the thickness of the second chip 140 itself, the lower part of the one end 1502 of the metal sheet and The overflow of the adhesive on the lower part of the second chip 140 is less likely to climb to the surface of the second chip 140 and affect the performance of the circuit. Therefore, the distance between one end 1502 of the metal sheet and the second chip 140 can be shortened, and the distance between the first chip 1501 and the second chip 1502 can also be shortened. In this embodiment, the distance from the edge of the chip to the edge of the chip is greater than 5 mils to be suitable for packaging, while in traditional packaging, the distance from the edge of the chip to the edge of the chip needs to be greater than 20 mils. It can be seen that the groove structure in this embodiment The utilization rate of the chip in the package is improved, and the cost is saved. In addition, the metal sheet 150 can also be replaced by a lead wire or a ribbon connection wire.
如图7所示,提供引线160用于芯片电极的连接,第一芯片130与引脚111导电连接;第一芯片130的顶部栅极通过引线160与引脚113连接;第二芯片140的顶部源极通过引线160与引脚112连接;第二芯片140的顶部栅极通过引线160与引脚114连接。As shown in Figure 7, lead 160 is provided for the connection of chip electrode, and first chip 130 is electrically connected with pin 111; The top gate of first chip 130 is connected with pin 113 by lead 160; The source is connected to the pin 112 through the lead 160 ; the top gate of the second chip 140 is connected to the pin 114 through the lead 160 .
如图8所示,引线连接结束后,采用塑封体170对该封装结构进行封装。As shown in FIG. 8 , after the wire connection is completed, the package structure is packaged with a plastic package 170 .
如图9所示,塑封结束后,从塑封体170的底部切断基座凹槽1153的底部,从而分割第一芯片安装区域1151及第二芯片安装区域1152,以完成芯片的封装。凹槽底部断开宽度应小于凹槽宽度,以保留足够的底部接纳金属片150的一个终端。As shown in FIG. 9 , after the plastic packaging is completed, the bottom of the base groove 1153 is cut off from the bottom of the plastic packaging body 170 to divide the first chip mounting area 1151 and the second chip mounting area 1152 to complete chip packaging. The cut-off width at the bottom of the groove should be smaller than the width of the groove, so as to reserve enough bottom to receive one terminal of the metal sheet 150 .
在本实施例中,第一芯片130及第二芯片140分别为MOSFET芯片。第一芯片130及第二芯片140也可分别是一集成电路控制芯片和一MOSFET芯片,或其它集成电路芯片的组合。芯片的底部可设电极也可不设电极,同时根据不同的芯片可选用不同的导电或绝缘粘合物。第一芯片可选用第一粘合物,第二芯片可选用第二粘合物。第一粘合物和第二粘合物可以相同也可以不同。In this embodiment, the first chip 130 and the second chip 140 are MOSFET chips respectively. The first chip 130 and the second chip 140 can also be an integrated circuit control chip and a MOSFET chip respectively, or a combination of other integrated circuit chips. The bottom of the chip can be provided with electrodes or not, and different conductive or insulating adhesives can be selected according to different chips. A first adhesive can be selected for the first chip, and a second adhesive can be selected for the second chip. The first binder and the second binder may be the same or different.
实施例二、本发明提供一种金属片键接的封装方法,该封装结构包括引线框架210、粘合物220、芯片230、金属片240、引线250及塑封体260,本发明的半导体封装方法流程图如图10所示,其具体封装步骤如下:Embodiment 2. The present invention provides a packaging method for metal sheet bonding. The packaging structure includes a lead frame 210, an adhesive 220, a chip 230, a metal sheet 240, a lead 250, and a plastic package 260. The semiconductor packaging method of the present invention The flow chart is shown in Figure 10, and the specific packaging steps are as follows:
如图11所示,提供一引线框架210,引线框架210包括引脚及芯片基座211。引脚包括两组与芯片基座211连接在一起并分别设置在芯片基座211两边的引脚212、引脚213以及与芯片基座211断开设置的引脚214。如图1所示,在芯片基座211与引脚213之间还设有一个基座与引脚间凹槽215,基座与引脚间凹槽215将芯片基座211与引脚213之间区分开来。As shown in FIG. 11 , a lead frame 210 is provided, and the lead frame 210 includes pins and a chip base 211 . The pins include two groups of pins 212 , 213 connected to the chip base 211 and arranged on both sides of the chip base 211 , and pins 214 disconnected from the chip base 211 . As shown in Figure 1, between the chip base 211 and the pin 213, there is also a groove 215 between the base and the pin, and the groove 215 between the base and the pin connects the gap between the chip base 211 and the pin 213. distinguish between.
如图12所示,提供一芯片230,将芯片230通过粘合物220设置在芯片基座211上,溢出的粘合物220可流入基座与引脚间凹槽215,并累积在基座与引脚间凹槽靠近基座的底部角落,从而避免了对芯片安装设备的连接,芯片230的边缘亦可尽可能的靠近芯片基座211的边缘。同时根据不同的芯片可选用不同的导电或绝缘粘合物。As shown in FIG. 12 , a chip 230 is provided, and the chip 230 is placed on the chip base 211 through the adhesive 220. The overflowed adhesive 220 can flow into the groove 215 between the base and the pins, and accumulate on the base. The groove between the pins is close to the bottom corner of the base, so as to avoid the connection to the chip mounting equipment, and the edge of the chip 230 can be as close as possible to the edge of the chip base 211 . At the same time, different conductive or insulating adhesives can be selected according to different chips.
如图13所示,用金属片240连接芯片的顶部电极及引脚,芯片以功率金属氧化物半导体为例,该顶部电极为源极,金属片240的一端2401设置在芯片的顶部源极上,金属片240的另一端2401设置在凹槽内靠近引脚的部位,与引脚导电连接。此外金属片240也可由引线或带状连接线替代。As shown in Figure 13, the top electrode and pins of the chip are connected with a metal sheet 240. The chip is an example of a power metal oxide semiconductor, the top electrode is the source, and one end 2401 of the metal sheet 240 is arranged on the top source of the chip. , the other end 2401 of the metal sheet 240 is disposed in the groove close to the pin, and electrically connected to the pin. In addition, the metal sheet 240 can also be replaced by a lead wire or a ribbon connection wire.
如图14所示,用引线250连接芯片230的顶部栅极与引脚214。如图15所示,接着用塑封体260塑封引线框架、芯片、金属片及引脚。塑封完毕后,如图16所示,在塑封体底部,切断基座与引脚间凹槽215的底边,从而断开芯片基座211与引脚213之间的连接,以完成整个封装工艺。凹槽底部断开宽度应小于凹槽宽度,以保留足够的底部以接纳金属片240的终端2401。在本实施例中,塑封之前将芯片基座及引脚连接在一起,并通过基座与引脚间凹槽区分,基座与引脚间凹槽保护芯片安装设备不受粘合物的污染,从而允许减小芯片基座与引脚之间的距离,提高了封装中芯片的利用率。在本实施例中,芯片230可以是MOSFET芯片或其它任何集成电路芯片。芯片的底部可设电极也可不设电极,同时根据不同的芯片可选用不同的导电或绝缘粘合物。As shown in FIG. 14 , a wire 250 is used to connect the top gate of chip 230 to pin 214 . As shown in FIG. 15 , the lead frame, chips, metal sheets and pins are then plastic-encapsulated with a plastic package 260 . After the plastic sealing is completed, as shown in Figure 16, at the bottom of the plastic package, cut off the bottom edge of the groove 215 between the base and the pins, thereby disconnecting the connection between the chip base 211 and the pins 213 to complete the entire packaging process . The cut-off width of the bottom of the groove should be smaller than the width of the groove to leave enough bottom to receive the terminal 2401 of the metal sheet 240 . In this embodiment, the chip base and the pins are connected together before plastic packaging, and are distinguished by the groove between the base and the pins, and the groove between the base and the pins protects the chip mounting equipment from contamination by adhesives , thereby allowing the distance between the chip base and the pins to be reduced, improving the utilization of the chip in the package. In this embodiment, the chip 230 may be a MOSFET chip or any other integrated circuit chip. The bottom of the chip can be provided with electrodes or not, and different conductive or insulating adhesives can be selected according to different chips.
实施例三、上述实施例一是封装结构在塑封之前将芯片基座上的每个芯片安装区域连接在一起,以基座凹槽加以区分,塑封结束后,对基座凹槽进行切割以完成整个封装过程。实施例二是封装结构在塑封之前将芯片基座与引脚连接在一起,以基座与引脚间凹槽加以区分,塑封结束后,对基座与引脚间凹槽进行切割以完成整个封装过程。在具体的封装过程中,可将实施例一和实施例二结合起来。如图17所示,用金属片代替引线连接芯片电极与引脚,引线框架310中的芯片基座311之间以及芯片基座311与引脚312之间都连接在一起,并分别以基座凹槽313、基座与引脚间凹槽314区分,在芯片安装完毕以及塑封体塑封完毕后,再将基座凹槽313、基座与引脚间凹槽314切断以完成整个封装。凹槽底部断开宽度应小于凹槽宽度。Embodiment 3. The above embodiment 1 is that the packaging structure connects each chip mounting area on the chip base before plastic sealing, and distinguishes them by base grooves. After the plastic sealing is completed, the base grooves are cut to complete the entire encapsulation process. The second embodiment is that the package structure connects the chip base and the pins together before plastic sealing, and distinguishes them by the groove between the base and the pins. After the plastic sealing is completed, the groove between the base and the pins is cut to complete the whole Encapsulation process. In a specific packaging process, Embodiment 1 and Embodiment 2 can be combined. As shown in FIG. 17 , metal sheets are used instead of lead wires to connect the chip electrodes and pins, and the chip bases 311 in the lead frame 310 and between the chip bases 311 and the pins 312 are all connected together, and are connected with the bases respectively. The groove 313 and the groove 314 between the base and the pins are distinguished. After the chip is installed and the plastic package is molded, the groove 313 of the base and the groove 314 between the base and the pins are cut to complete the whole package. The groove bottom break width should be smaller than the groove width.
在该实施例的芯片安装过程中,同样避免由粘合物的溢出而引起芯片安装设备的污染,并且更大限度的提高了封装体内可封装的芯片的面积,或者更大限度的减小了芯片的封装尺寸,降低了封装成本。In the chip mounting process of this embodiment, the pollution of the chip mounting equipment caused by the overflow of the adhesive is also avoided, and the area of the chip that can be packaged in the package is increased to a greater extent, or the area of the chip that can be packaged is reduced to a greater extent. The packaging size of the chip reduces the packaging cost.
当然,必须认识到,上述介绍是有关本发明优选实施例的说明,只要不偏离随后所附权利要求所显示的精神和范围,本发明还存在着许多修改。It must, of course, be realized that the foregoing description is of preferred embodiments of the invention and that the invention is susceptible to many modifications without departing from the spirit and scope as shown in the appended claims.
本发明决不是仅局限于上述说明或附图所显示的细节和方法。本发明能够拥有其它的实施例,并可采用多种方式予以实施。另外,大家还必须认识到,这里所使用的措辞和术语以及文摘只是为了实现介绍的目的,决不是仅仅局限于此。In no way is the invention limited to the details and methods shown in the foregoing description or drawings. The invention is capable of other embodiments and of being carried out in various ways. In addition, everyone must also realize that the wording and terminology used here and the abstract are for the purpose of introduction only and by no means limited thereto.
正因为如此,本领域的技术人员将会理解,本发明所基于的观点可随时用来作为实施本发明的几种目标而设计其它结构、方法和系统。所以,至关重要的是,所附的权利要求将被视为包括了所有这些等价的建构,只要它们不偏离本发明的精神和范围。As such, those skilled in the art will appreciate that the insights upon which this invention is based may readily be employed in designing other structures, methods and systems for carrying out the several purposes of the invention. It is, therefore, of vital importance that the appended claims are to be regarded as including all such equivalent constructions insofar as they do not depart from the spirit and scope of the invention.
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| CN104716117B (en) * | 2013-12-17 | 2017-10-24 | 万国半导体股份有限公司 | Multichip device and its method for packing |
| CN104465423B (en) * | 2014-12-08 | 2017-08-22 | 杰群电子科技(东莞)有限公司 | A kind of Double-lead-frame overlaps designing semiconductor device method for packing |
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| CN111403296B (en) * | 2020-03-30 | 2022-03-25 | 捷捷微电(上海)科技有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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| US7235876B2 (en) * | 2005-09-12 | 2007-06-26 | Denso Corporation | Semiconductor device having metallic plate with groove |
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