CN102403018B - Matching detection method and circuit of content addressable memory cell - Google Patents

Abstract

The invention relates to a content addressable memory storage unit matching detection method and circuit. In the present invention, the charging circuit of the first matching signal line and the feedback control circuit of the second matching signal line are charged or controlled; or the content of the non-storage unit is matched, and a matching signal is output if there is a voltage difference between the matching signal lines; or If the content of the non-memory cells does not match, if there is no voltage difference between the matching signal lines, no matching signal will be output. The invention is simple and reliable; compared with the traditional storage unit matching detection method, the extra bias voltage and bias current are reduced, and the power consumption is further reduced.

Description

Content addressable memory storage unit matching detection method and circuit

technical field

The present invention relates to a content addressable memory, in particular to a matching detection method and circuit of a content addressable memory storage unit.

Background technique

Content-Addressable Memory (CAM) is a content-addressable memory for specific high-speed search applications. Its working principle is: when the user provides a piece of data, CAM will traverse the entire storage space to search whether the data exists in the storage, and if so, CAM will return one or more addresses where the hit data exists. CAM is a special memory that searches the entire memory in a single operation. Therefore, in search applications, CAM is much faster than ordinary memory. The fast search feature of CAM makes CAM especially suitable for applications such as network equipment, central processing unit, and video hard codec.

The storage unit structure of traditional content addressable memory is divided into NAND type storage unit and NOR type storage unit according to the similarities and differences of matching types. FIG. 1 is a NAND memory cell with a traditional 9T (Transistor, transistor) structure. The NAND-type memory cell matching signal line (Match Line) forms an overall match line by connecting with adjacent memory cells. That is, the source of the transistor T1 is connected to the drain of the previous memory cell, and the drain of T1 is connected to the source of the next memory cell. The structure of the NAND storage unit determines that as long as one of the searched content does not match the stored content, the entire matching signal line will not be discharged. The disadvantage of the NAND memory cell is that if the content is all matched, the matching signal line will discharge through the cascaded transistor T1, and the discharge speed will be very slow when the storage content is large.

FIG. 2 is a NOR type memory cell, and an overall matching signal line is formed by connecting the open drains of different memory cells. The method of parallel connection avoids the cascade connection with the internal transistors of the non-type memory cells, so that the NOR-type memory cells are very suitable for high-speed structures. If a certain bit in the search content does not match the content in the memory cell, the matching signal line of the non-type memory cell starts to discharge. The matching signal line will not discharge if and only if what it is looking for matches. The discharge speed of the NOR memory cell is fast, but the power consumption of the content addressable memory is very large due to frequent discharge and charge.

In order to reduce the power consumption of the matching signal line of the NOR type memory cell, various detection methods have appeared at present. Figure 3 is a schematic diagram of current race detection. As shown in Figure 3, the detection method based on the current race requires a set of virtual matching signal lines (Dummy ML) as a comparison signal. The DML is always in a matching state. When the method detects the state of the matching signal line, first the matching signal line reset signal (MLrst) is valid, and the matching signal line (ML) is initialized to a low level; then the matching line enable signal (MLen) changes from low to high, Open the charging path of the matching signal line. When the DML is charged to the threshold of the sensitive amplifier (SA), a matching signal line off signal (MLoff) is generated, which will turn off the charging path of all matching signal lines. Only the matched matching signal line will make the sensitive amplifier (SA) generate an output signal (MLout) within the charging time, and once there is a mismatched matching signal line, it will not be charged beyond the threshold of the sensitive amplifier (SA). The method reduces the power consumption of the overall matching signal line by reducing the charging swing of the matching signal line.

Figure 4 is a schematic diagram of the current saving detection. This scheme is similar to the current race detection method. It also uses the threshold voltage of the virtual matching signal line (DML) and the sensitive amplifier (SA) to control the charging time of the matching signal line and reduce the overall power consumption. The difference of this scheme is that the current The saving technique will reduce the charging current of the matching line in the case of loss of the matching signal line, thereby further reducing the overall power consumption.

Figure 5 is a schematic diagram of positive feedback detection. This scheme is similar to the current-saving matching line detection method, which uses positive feedback to reduce the charging current of the matching signal line in the state of missing matching, and reduces the overall power consumption.

From the above three traditional solutions, it can be seen that the initial discharge of the matching signal line still wastes a lot of power consumption; the use of current saving technology and positive feedback technology can reduce the charging current of the matching signal line in the state of content mismatch, but requires additional Offset voltage and additional quiescent current consumed in the control branch. Therefore, how to further reduce the power consumption of the or non-memory cell matching signal line is an important problem to be solved at present.

Contents of the invention

The present invention provides a content addressable memory storage unit matching detection method and circuit that can solve the above problems.

In a first aspect, the present invention provides a content addressable memory storage unit matching detection method, wherein several NOR storage units are connected in parallel to form a first matching signal line (MLA) and a second matching signal line (MLB), said The method includes: a charging circuit for charging the first matching signal line, a feedback control circuit connected to the second matching line; when the contents of the several or non-storage units all match, the first matching signal line and the There is a voltage difference between the second matching signal lines sufficient to cause an output matching signal; when at least one of the several or non-storage units does not match, the first matching signal line passes through the or non-storage unit whose content does not match charging the second matching signal line and causing the feedback control circuit to turn off the charging circuit, whereby the voltage difference between the first matching signal line and the second matching signal line is insufficient to output a matching Signal.

In a second aspect, the present invention provides a content-addressable memory storage unit matching detection circuit, including a pre-charging circuit, a charging circuit, a feedback control circuit, an equalization circuit and several NOR storage units, the pre-charging circuit and the The charging circuit and the feedback control circuit are connected, the first matching signal line and the second matching signal line are formed by the parallel connection of the several or non-storage units, the charging circuit is connected to the first matching signal line, and the feedback control circuit connected to the second matching signal line, and the equalization circuit is connected between the first matching signal line and the second matching signal line.

In a third aspect, the present invention provides a matching detection method for a complementary content addressable memory storage unit, wherein several NOR storage units are connected in parallel to form a first matching signal line (MLA) and a second matching signal line (MLB), The method includes: a feedback control circuit connected to the first matching signal line, a discharge circuit for discharging on the second matching signal line, when the contents of the several or non-memory cells all match, the first matching signal line There is a voltage difference between the second matching signal line and the second matching signal line enough to cause an output matching signal; when the content of at least one of the several or non-storage cells does not match, the non-storage cell whose content does not match is discharged through the discharge circuit , and prompt the feedback control circuit to turn off the discharge circuit, so that the voltage difference between the first matching signal line and the second matching signal line is insufficient to output a matching signal.

In a fourth aspect, the present invention provides a complementary content addressable memory storage unit matching detection circuit, including a pre-discharge circuit, a discharge circuit, a feedback control circuit, an equalization circuit and several NOR storage units, the pre-discharge circuit Connected with the discharge circuit and the feedback control circuit, the first matching signal line and the second matching signal line formed by the parallel connection of the several or non-storage units, the feedback control circuit is connected with the first matching signal line, so The discharge circuit is connected to the second matching signal line, and the equalization circuit is connected between the first matching signal line and the second matching signal line.

The invention utilizes the charging method of dynamically controlling the matching line to reduce the current consumption, and detects the result of the voltage difference signal generated by the matching line number line. The invention is simple and reliable; compared with the traditional matching signal line detection method, the current consumption is reduced, and the extra bias voltage and bias current are reduced.

Description of drawings

Fig. 1 is traditional structure and non-type storage unit;

Fig. 2 is NOR type storage unit;

Figure 3 is a schematic diagram of the current race detection;

Fig. 4 is a schematic diagram of saving current detection;

Fig. 5 is a schematic diagram of positive feedback detection;

Fig. 6 is a block diagram of a non-memory cell matching detection circuit;

Fig. 7 is a schematic diagram of a non-memory cell matching detection circuit;

Fig. 8 is a timing control diagram of the matching detection circuit of the NOR memory cell;

Fig. 9 is a complementary or non-memory cell matching detection circuit block diagram;

Fig. 10 is a schematic diagram of a complementary or non-memory cell matching detection circuit;

FIG. 11 is a timing control diagram of a complementary or non-memory cell matching detection circuit.

Detailed ways

The specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. FIG. 6 is a block diagram of an OR non-memory cell matching detection circuit according to an embodiment of the present invention, and FIG. 7 is a schematic diagram of an OR non-memory cell matching detection circuit. As shown in Figure 6, the non-storage unit matching detection circuit includes: pre-charging circuit, charging circuit, feedback control circuit, equalization circuit, or non-storage unit, sensitive amplifier (SA), power supply and ground, wherein, the non-storage unit The number is greater than 1, and the first matching signal line MLA and the second matching line signal MLB are formed by parallel connection of several NOR memory cells (hereinafter referred to as matching signal line MLA and matching line signal MLB).

As shown in FIG. 7 , the transistors N1 , N2 , N3 , N4 , N5 and the NOR memory cells of the circuit are all NMOS transistors inside; the transistors P1 and P2 are PMOS transistors. The pre-charging circuit includes a first P-type transistor P1. The charging circuit includes a second P-type transistor P2 and a fourth N-type transistor N4, the function of which is to dynamically control the charging of the matching signal line MLA according to the change of the feedback control circuit. The feedback control circuit comprises a second N-type transistor N2, a third N-type transistor N3 and a first N-type transistor N1, wherein the second N-type transistor N2 and the third N-type transistor N3 form a current mirror, and the function of the feedback control circuit is According to the change of the voltage of the matching signal line MLB, the charging circuit is feedback-controlled, and the function of discharging the matching line MLB is also realized. In this embodiment, the fifth N-type equalization circuit includes a transistor N5 whose function is to initialize the matching signal line MLA and the matching signal line MLB.

The source of the first P-type transistor P1 in the pre-charging circuit and the source of the second P-type transistor P2 in the charging circuit are connected to the power supply, and the gate of the first P-type transistor P1 is controlled by the pre-charging signal PRE (hereinafter referred to as PRE signal) control, its drain is connected to point A with the drain of the second N-type transistor N2; the gate of the second P-type transistor P2 is controlled by the non-evaluation signal NEVAL (hereinafter referred to as NEVAL signal), and its drain is connected to the charging circuit The drains of the fourth N-type transistor N4 are connected, the second N-type transistor N2 and the fourth N-type transistor N4 are connected in series; the gate of the fourth N-type transistor N4 is connected to point A; the matching signal line MLA is connected to the fourth Between the source of the N-type transistor N4 and the drain of the fifth N-type transistor N5 in the balance circuit; the gate and the drain of the third N-type transistor N3 in the feedback control circuit are all connected on the matching signal line MLB; One end of the signal line MLB is connected to the gates of the second N-type transistor N2 and the third N-type transistor N3, and the other end is connected to the source of the fifth N-type transistor N5. The gate of the fifth N-type transistor N5 is controlled by the reset signal RST (hereinafter referred to as RET signal) control; the gate of the second N-type transistor N2 and the third N-type transistor N3 are connected, and the sources of the two transistors are connected as the output branch of the current mirror; the first N-type transistor N1 in the feedback control circuit The drain is connected to the source of the second N-type transistor N2 and the third N-type transistor N3, and its grid is controlled by the evaluation signal EVAL (hereinafter referred to as the EVAL signal); the positive and negative input terminals of the sensitive amplifier are respectively connected to the matching signal On the line MLA and the matching signal line MLB, the output terminal of the sensitive amplifier is the matching signal line output signal MLSO (hereinafter referred to as the MLSO signal).

The working process of the detection circuit in FIG. 7 will be described in detail below in conjunction with FIG. 8 . FIG. 8 is a timing control diagram of the matching detection circuit of the NOR memory cell.

When comparing and matching for the first time, as shown in FIG. 8 , the system works under the clock signal CLK, and the RST signal is active at high level, which equalizes the matching signal line MLA and the matching signal line MLB. After equalization, the matching signal lines MLA and MLB are at low level. The PRE signal is active at low level, the first P-type transistor P1 is turned on, and point A is firstly precharged to the power supply voltage. The EVAL signal is at low level, and the NEval signal is at high level, so that the second P-type transistor P2 and the first N-type transistor N1 are turned off.

When the EVAL signal transitions to a high level, the NEval signal is at a low level, and the second P-type transistor P2 and the first N-type transistor N1 are turned on. Since the node A is pre-charged to the power supply first, the fourth N-type transistor N4 is turned on at this moment, and the second P-type transistor P2 will charge the matching line MLA through the fourth N-type transistor N4. At this time, if the content of the NOR memory cell does not match, the matching signal line does not match, and the matching signal line MLB will also be charged through the discharge path inside the NOR cell, and the voltage of the matching signal line MLB rises. When the voltage of the matching signal line MLB exceeds the threshold value of the third N-type transistor N3, the third N-type transistor N3 and the second N-type transistor N2 are turned on. Due to the conduction of the second N-type transistor N2, the node A will be discharged through the feedback control circuit, so that the voltage of the node A will drop, and the fourth N-type transistor N4 will be turned off. At this time, the feedback control circuit turns off the charging circuit, the charging circuit does not continue to charge the matching signal line MLA, the voltage of the matching signal line MLA does not continue to rise, and the entire charging process ends.

Because the contents of the NOR memory cells do not match, the voltages of the matching signal line MLA and the matching signal line MLB are basically consistent, so that the sensitive amplifier SA will not be reversed, and the matching MLSO signal will not be generated.

If the content of the NOR storage unit matches, the matching signal line MLB will not be charged by the internal discharge path of the NOR unit. At this time, the charging circuit continues to charge the matching signal line MLA to increase its voltage, while the voltage of the matching signal line MLB remains constant. The voltage difference between the matching signal line MLA and the matching signal line MLB will cause the sensitive amplifier SA to flip and generate a matching MLSO signal.

It should be noted that the equalization circuit can also realize its function by a transmission gate composed of a sixth N-type transistor and a third P-type transistor, and the drain of the sixth N-type transistor and the source of the third P-type transistor are connected to the first On the matching signal line, the source of the sixth N-type transistor and the drain of the third P-type transistor are connected to the second matching signal line, the gate of the sixth N-type transistor is connected to the reset signal, and the gate of the third P-type transistor is connected to the reset signal. The gate of the transistor is connected to a non-reset signal.

What has been described above is the charging method and matching comparison method when the comparison and matching are performed for the first time, and the subsequent charging method and matching comparison method reflect the characteristics of saving power consumption.

Specifically, when comparing and matching for the second time, the system works under the clock signal, and the RST signal is active at high level, which will equalize the matching signal line MLA and the matching signal line MLB. After the first comparison and matching, the voltage of the matching signal line appears in two situations according to the comparison result, or the voltage of the matching signal line is inconsistent when the content of the non-storage unit matches and the voltage of the matching signal line is basically the same when the content of the non-storage unit does not match. During the equalization process, the voltages of the two matching signal lines are basically kept the same, and the voltage of the matching signal line MLB after equalization is slightly higher than the threshold voltage of the third N-type transistor N3. The PRE signal is active at low level, the first P-type transistor P1 is turned on, and the node A is precharged to the power supply. The EVAL signal is at low level, and the NEval signal is at high level, so that the second P-type transistor P2 and the first N-type transistor N1 are turned off.

When the EVAL signal transitions to high level and the NEval signal is low level, the second P-type transistor P2 and the first N-type transistor N1 are turned on. Since the node A is pre-charged to the power supply, the fourth N-type transistor N4 is turned on at this moment, and the second P-type transistor P2 will charge the matching signal line MLA through the fourth N-type transistor N4. Since the voltage of the matching signal line MLB after equalization is slightly higher than the threshold voltage of the third N-type transistor N3, the matching signal line MLB is discharged to the threshold voltage of the third N-type transistor N3 through the third N-type transistor N3. The third N-type transistor N3 and the second N-type transistor N2 are turned on, so that the node A is discharged through the feedback control circuit, and the voltage of the node A drops, causing the fourth N-type transistor N4 to be turned off, and the feedback control circuit turns off the charging circuit, The charging circuit does not continue to charge the matching signal line MLA, the voltage of the matching signal line MLA does not continue to rise, and the charging process ends.

In this way, each charging process only has the time (ΔT) to discharge node A. During this period, if the content of the non-memory cell matches, the matching signal line MLA will be charged for ΔT time, so that the voltage rises, and the matching The signal line MLB is discharged to the threshold voltage of the third N-type transistor N3 through the feedback control circuit, and the voltage difference generated by the matching signal line MLA and the matching signal line MLB makes the sensitive amplifier SA flip; The matching signal line MLA and the matching signal line MLB are charged at the same time at all times, and the matching signal line MLA and the matching signal line MLB are also discharged through the feedback control circuit at the same time, so that the charge is basically balanced, so that the sensitive amplifier SA will not be reversed, and no matching will occur. MLSO signal.

Due to the extremely short ΔT time, this solution can effectively reduce the current consumption in the case of non-matching and matching of the content of the memory cell, and does not require additional bias voltage and bias current, and has no static power consumption. At the same time The initialization and control of the scheme are simple and easy to implement.

It should be pointed out that, in addition to the transistors constituting the schematic circuit diagram shown in FIG. 7 , other types of transistors can also be used.

In the complementary or non-storage unit matching detection circuit, as shown in Figure 9, the complementary detection circuit includes: a pre-discharge circuit, a discharge circuit, a feedback control circuit, an equalizing circuit, or a non-storage unit, a sensitive amplifier SA, a power supply and Wherein, the number of NOR storage units is greater than 1, the first matching signal line MLA and the second matching signal line MLB are formed by parallel connection of several NOR storage units (hereinafter referred to as matching signal line MLA and matching line signal MLB) .

As shown in FIG. 10 , the transistors P1 , P2 , P3 , P4 , P5 and the non-memory cells in the complementary or non-memory cell matching detection circuit are all PMOS transistors, and the transistors N1 and N2 are NMOS transistors. The pre-discharge circuit includes a first N-type transistor N1; the discharge circuit includes a fifth P-type transistor P5 and a second N-type transistor N2; the feedback control circuit includes a second P-type transistor P2, a third P-type transistor P3 and a fourth P-type transistor. Type transistor P4, the third P-type transistor P3 and the fourth P-type transistor P4 form a current mirror, its function is to control the discharge circuit according to the conduction state of the fifth P-type transistor P5 in the discharge circuit, and also realize the charging function of the matching line MLA ; In this embodiment, the equalization circuit includes a first P-type transistor P1 whose function is to initialize the matching signal line MLA and the matching signal line MLB.

The gate of the second P-type transistor P2 in the feedback control circuit is controlled by the NEVAL signal, and its source is connected to the power supply. The third P-type transistor P3 and the fourth P-type transistor P4 form a current mirror. The third P-type transistor P3 and the fourth P-type transistor P3 The sources of the four P-type transistors P4 are connected to the drain of the second P-type transistor P2, the drain of the third P-type transistor P3 is connected to the drain of the first N-type transistor N1 in the pre-discharge circuit at node A, and the drain of the third P-type transistor P3 is connected to node A. The gates of the three P-type transistors P3 and the fourth P-type transistor P4 are connected, and the matching signal line MLA is connected to the gates of the third P-type transistor P3 and the fourth P-type transistor P4, and serves as the positive input terminal of the sensitive amplifier SA, The drain of the fourth P-type transistor P4 is connected to the matching signal line MLA; one end of the matching signal line MLB is connected to the source of the fifth P-type transistor P5 in the discharge circuit, and the other end is used as the negative input terminal of the sensitive amplifier. The output terminal is the MLSO signal; the gate of the fifth P-type transistor P5 in the discharge circuit is connected to node A, and its drain is connected to the drain of the second N-type transistor N2; the gate of the second N-type transistor N2 is controlled by the EVAL signal Control, the gate of the first N-type transistor N1 in the pre-discharge circuit is controlled by the pre-discharge signal DIS (hereinafter referred to as DIS signal), the source of the second N-type transistor N2 and the source of the first N-type transistor N1 in the pre-discharge circuit Both poles are connected to ground; the gate of the first P-type transistor P1 in the equalization circuit is connected to the RST signal, and its source and drain are respectively connected to the first matching signal line MLA and the second matching signal line MLB.

When comparing and matching, as shown in Figure 11, the system works under the clock signal CLK, and the RST signal is active at low level, which will equalize the matching signal line MLA and the matching signal line MLB, and the voltage of the matching line MLA and the matching line MLB after equalization Keep consistent, the DIS signal is active high, the first N-type transistor N1 is turned on, the node A is first discharged through the first N-type transistor N1, and is initialized to the ground, and the fifth P-type transistor P5 connected to the node A is in the conduction state. pass status. The EVAL signal is at low level, and the NEval signal is at high level, so that the second N-type transistor N2 and the second P-type transistor P2 are turned off. When the EVAL signal jumps to a high level, the NEval signal is at a low level, the second N-type transistor N2 and the second P-type transistor P2 are in a conducting state, and since the second P-type transistor P2 is conducting, the current mirror is turned on , the node A is charged through the third P-type transistor P3, so that the voltage at point A rises, and the matching signal line MLA is charged through the current mirror in the feedback circuit.

It can be clearly seen in FIG. 10 that the matching signal line MLB is discharged through discharge. Since the node A is initialized to ground at the beginning of the matching detection, the fifth P-type transistor P5 is always in the conduction state, and the node A is passed through the current mirror. The third P-type transistor P3 is charged, and the voltage of node A starts to rise from 0. During the time (ΔT) when the voltage of node A rises from 0 to turning off the fifth P-type transistor P5, if the content of the or non-memory cell matches, Then the matching signal line is matched. At this time, the current mirror in the feedback control circuit continues to charge the matching signal line MLA to make its voltage rise, while the matching signal line MLB and the discharge circuit form a path to make its voltage drop, and the matching signal line MLA and the matching signal line There is a voltage difference between lines MLB which causes the sense amplifier SA to flip, producing a matching MLSO signal.

During the time (ΔT) when the voltage of node A rises from 0 to turning off the fifth P-type transistor P5, if the content of the non-memory cell does not match, the matching signal line does not match, or the non-memory cell will be discharged through the discharge circuit , so that the voltages of the matching signal line MLA and the matching signal line MLB drop, and the voltages between the matching signal lines are basically consistent, so that the sensitive amplifier SA will not be reversed, and the matching MLSO signal will not be generated.

After the voltage of node A rises to turn off the fifth P-type transistor P5, that is, the feedback control circuit turns off the discharge circuit, and the discharge circuit no longer forms a path with the matching signal line MLB, and the matching signal line MLB is in a hold state, if or not If the content of the storage unit matches, the matching signal line matches, and the current mirror in the feedback control circuit continues to charge the matching signal line MLA to increase its voltage, while the voltage of the matching signal line MLB remains, and there is a voltage between the matching line MLA and the matching line MLB Difference, the voltage difference makes the sense amplifier SA reverse, and produces a matching MLSO signal output. If the contents of the non-memory cells do not match, the matching signal lines do not match, or the non-memory cells are discharged, so that the voltages between the matching signal lines are basically consistent, so that the sensitive amplifier SA will not be reversed, and the matching MLSO signal will not be generated.

It should be noted that the equalization circuit can also realize its function by a transmission gate composed of a third N-type transistor and a sixth P-type transistor, and the drain of the third N-type transistor and the source of the sixth P-type transistor are connected to the first On the matching signal line, the source of the third N-type transistor and the drain of the sixth P-type transistor are connected to the second matching signal line, and the gate of the sixth P-type transistor is connected to the reset signal. The gate of the transistor is connected to a non-reset signal.

The present invention can use the charging method of dynamically controlling the matching signal line, reduce the current consumption in the matching comparison process, and use the voltage differential signal detection result generated at the time ΔT. The invention is simple and reliable; compared with the traditional matching line detection method, the current consumption is reduced, the extra bias voltage and bias current are reduced, and the invention can be applied to different or unstructured matching line detection occasions.

It will be apparent that many changes may be made to the invention described herein without departing from the true spirit and scope of the invention. Therefore, all changes obvious to those skilled in the art should be included within the scope of the claims. The claimed scope of the present invention is limited only by the claims set forth.

Claims (8)

1. Content Addressable Memory storage unit match detection circuit, comprise pre-charge circuit, charging circuit, feedback control circuit, equalizing circuit and some or non-storage unit, described pre-charge circuit is connected with described charging circuit and feedback control circuit, by described some or non-storage unit the first matched signal line and the second matched signal line of forming in parallel, described charging circuit is connected with described the first matched signal line, described feedback control circuit is connected with described the second matched signal line, described equalizing circuit is connected between described the first matched signal line and described the second matched signal line,

Described pre-charge circuit comprises a P transistor npn npn (P1);

Described feedback control circuit comprises the first N-type transistor (N1), the second N-type transistor (N2) and the 3rd N-type transistor (N3);

Described the second N-type transistor (N2) is connected with the grid of described the 3rd N-type transistor (N3), described the second N-type transistor (N2) is all connected in the drain electrode of described the first N-type transistor (N1) with the source electrode of described the 3rd N-type transistor (N3), the grid of described the first N-type transistor (N1) connects assessment signal, and the source electrode of described the first N-type transistor (N1) connects ground;

Described charging circuit comprises the 2nd P transistor npn npn (P2) and the 4th N-type transistor (N4);

The source electrode of a described P transistor npn npn (P1) is connected high level with the source electrode of described the 2nd P transistor npn npn (P2), the grid of a described P transistor npn npn (P1) connects precharging signal, and the drain electrode of the drain electrode of a described P transistor npn npn (P1) and described the second N-type transistor (N2) is connected to node (A); The grid of described the 2nd P transistor npn npn (P2) connects non-assessment signal, and the drain electrode of described the 2nd P transistor npn npn (P2) is connected with the drain electrode of described the 4th N-type transistor (N4); The grid of described the 4th N-type transistor (N4) is connected to node (A); The source electrode of described the 4th N-type transistor (N4) is connected with described the first matched signal line; Described the second matched signal line is connected on the grid of described the second N-type transistor (N2) and described the 3rd N-type transistor (N3), and the drain electrode of described the 3rd N-type transistor (N3) is connected on described the second matched signal line.

2. testing circuit as claimed in claim 1, is characterized in that described testing circuit also comprises sense amplifier, and described sense amplifier is connected with described the first matched signal line and described the second matched signal line, for amplifying and output matching or mismatch signal.

3. testing circuit as claimed in claim 1, is characterized in that described equalizing circuit comprises the 5th N-type transistor (N5); The grid of described the 5th N-type transistor (N5) connects reset signal, and the drain electrode of described the 5th N-type transistor (N5) is connected with described the first coupling wire size line, and the source electrode of described the 5th N-type transistor (N5) is connected with described the second coupling wire size line.

4. testing circuit as claimed in claim 1, is characterized in that described equalizing circuit comprises the transmission gate being comprised of the 6th N-type transistor and the 3rd P transistor npn npn;

The source electrode of the transistorized drain electrode of described the 6th N-type and described the 3rd P transistor npn npn is all connected on described the first matched signal line, the drain electrode of the transistorized source electrode of described the 6th N-type and described the 3rd P transistor npn npn is all connected on described the second matched signal line, the transistorized grid of described the 6th N-type connects reset signal, and the grid of described the 3rd P transistor npn npn connects non-reset signal.

5. complementary Content Addressable Memory storage unit match detection circuit, comprise pre-arcing circuit, discharge circuit, feedback control circuit, equalizing circuit and some or non-storage unit, described pre-arcing circuit is connected with described discharge circuit and feedback control circuit, by described some or non-storage unit the first matched signal line and the second matched signal line forming in parallel, described feedback control circuit is connected with described the first matched signal line, described discharge circuit is connected with described the second matched signal line, described equalizing circuit is connected between described the first matched signal line and described the second matched signal line,

Described pre-arcing circuit comprises the first N-type transistor (N1);

Described feedback control circuit comprises the 2nd P transistor npn npn (P2), the 3rd P transistor npn npn (P3) and the 4th P transistor npn npn (P4);

The grid of described the 2nd P transistor npn npn (P2) connects non-assessment signal, the source electrode of described the 2nd P transistor npn npn (P2) connects high level, described the 3rd P transistor npn npn (P3) is connected and is connected with the drain electrode of described the 2nd P transistor npn npn (P2) with described the 4th P transistor npn npn (P4) source electrode, and described the 3rd P transistor npn npn (P3) is connected with the grid of described the 4th P transistor npn npn (P4);

Described discharge circuit comprises the 5th P transistor npn npn (P5) and the second N-type transistor (N2);

The drain electrode of the drain electrode of described the 3rd P transistor npn npn (P3) and described the first N-type transistor (N1) is connected to node (A), described the first matched signal line is connected on the grid of described the 3rd P transistor npn npn (P3) and described the 4th P transistor npn npn (P4), and the drain electrode of described the 4th P transistor npn npn (P4) is connected with described the first matched signal line; Described the second matched signal line is connected with the source electrode of described the 5th P transistor npn npn (P5), the grid of described the 5th P transistor npn npn (P5) is connected to node (A), and the drain electrode of described the 5th P transistor npn npn (P5) is connected with the drain electrode of described the second N-type transistor (N2); The grid of described the second N-type transistor (N2) connects assessment signal, the grid of described the first N-type transistor (N1) connects pre-arcing signal, and the source electrode of described the second N-type transistor (N2) is all connected low level with the source electrode of described the first N-type transistor (N1).

6. complementary Content Addressable Memory storage unit match detection circuit as claimed in claim 5, it is characterized in that described testing circuit also comprises sense amplifier, described sense amplifier is connected with described the first matched signal line and described the second matched signal line, for amplifying and output matching or mismatch signal.

7. complementary Content Addressable Memory storage unit match detection circuit as claimed in claim 5, it is characterized in that described equalizing circuit comprises a P transistor npn npn, the grid of a described P transistor npn npn (P1) connects reset signal, the drain electrode of a described P transistor npn npn (P1) is connected on described the first coupling wire size line, and the source electrode of a described P transistor npn npn (P1) is connected on described the second coupling wire size line.

8. complementary Content Addressable Memory storage unit match detection circuit as claimed in claim 5, is characterized in that described equalizing circuit comprises the transmission gate being comprised of the 6th P transistor npn npn and the 3rd N-type transistor;

The source electrode of the transistorized drain electrode of described the 3rd N-type and described the 6th P transistor npn npn is all connected on described the first matched signal line, the drain electrode of the transistorized source electrode of described the 3rd N-type and described the 6th P transistor npn npn is all connected on described the second matched signal line, the grid of described the 6th P transistor npn npn connects reset signal, and the transistorized grid of described the 3rd N-type connects non-reset signal.

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