CN102385899A - Latching amplification circuit applied to memory and reading method - Google Patents
Latching amplification circuit applied to memory and reading method Download PDFInfo
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- CN102385899A CN102385899A CN2010102727258A CN201010272725A CN102385899A CN 102385899 A CN102385899 A CN 102385899A CN 2010102727258 A CN2010102727258 A CN 2010102727258A CN 201010272725 A CN201010272725 A CN 201010272725A CN 102385899 A CN102385899 A CN 102385899A
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Abstract
The invention discloses a latching amplification circuit applied to a memory and a reading method. The circuit comprises a plurality of latching modules for a local bit line and an amplification module for a global bit line, wherein the latching modules for the local bit line are used for charging storage units on the local bit line through the local bit line according to applied pre-charging pulse signals, and sending received level signals to the amplification module for the global bit line according to applied control signals until the level signals are fed back by the storage units on the local bit line through the local bit line; the fed-back level signals are used for indicating data which is stored in the storage units; the amplification module for the global bit line is used for receiving the level signals, which are sent by the latching modules for the local bit line, of the storage units through the global bit line, and outputting the level signals to external equipment after amplification and latching. When the data, which is stored in the storage units, is read by the latching amplification circuit, the electric energy consumption is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of being applied in latched amplifying circuit and read method in the storer.
Background technology
For the storer in the semiconductor devices, comprise peripheral circuit region and memory cell region, wherein; Have a plurality of storage unit in the memory cell region; A plurality of storage unit are arranged in parallel in Y direction and X-direction, are connected to peripheral circuit region in Y direction through local bitline, are connected to peripheral circuit region in X-direction through word line; Word line is used for selected memory cell, and local bitline is used to read the data that selected storage unit is stored.
Particularly, memory cell region, behind the local bitline extra current, the data that storage unit feedback levels signal indication is stored represent that such as high level signal the data of storing are " 1 ", low level signal representes that the data of storing are " 0 ".Data for each cell stores in the reading cells zone; In peripheral circuit region, comprise and latch amplifying circuit; After giving the storage unit charging to read the storage data through local bitline; The storage unit that reads the storage data latchs amplifying circuit with after this level signal amplification and latching through local bitline feedback levels signal, is read by external unit.
Fig. 1 latchs the amplifying circuit synoptic diagram for what prior art provided, and is as shown in the figure, comprises local bitline latch module and global bit line amplification module, wherein,
The local bitline latch module has a plurality of; Corresponding one by one with local bitline, and be connected with each local bitline respectively, be used for through after the storage unit charging of local bitline for this local bitline; Wait for receiving the level signal of being fed back, send to the global bit line amplification module after latching;
The global bit line amplification module connects a plurality of local bitline latch module through global bit line, is used for receiving through global bit line the level signal of the storage unit of local bitline latch module transmission, after amplification is latched, exports to external unit.
The latch function of local bitline latch module is accomplished by latch units; Latch units can adopt multiple mode to realize; Such as adopting the completion of oppositely joining of two reversers; Perhaps adopt four MOS transistors (CMOS) to realize, purpose is that the level signal with the storage unit that receives latchs back output, improves reading speed.Fig. 2 is a concrete circuit diagram of realizing of the local bitline latch module of prior art, and is as shown in the figure, and this latch units adopts the MOS of 2 P types and the MOS of 2 N types to form, and is respectively PMOS1, PMOS2, NMOS1 and NMOS2.Wherein,
The source electrode of PMOS1 is connected with the drain electrode of PMOS2, and the drain electrode of PMOS1 is connected with the drain electrode of NMOS1, and the source electrode of NMOS1 is connected with the drain electrode of NMOS2; The source electrode of NMOS2 is connected with the source electrode of PMOS2, and the grid of PMOS2 inserts first connecting line of PMOS1 and NMOS1 with after the grid of NMOS2 is connected; This first connecting line is connected with local bitline; After the grid of NMOS1 and PMOS1 is connected, insert second connecting line of PMOS2 and NMOS2, this second connecting line is as output.The source electrode of PMOS1 connects high level (Vdd), and the source electrode of NMOS1 also connects low level (Vss), and is not shown.
When this local bitline latch module work; Driving circuit (not shown) on the local bitline is given local bitline extra current (the local bitline latch module also is in opening); Make after the storage unit charging on the local bitline, through local bitline feedback levels signal.Level signal makes that (according to level signal is that high level or low level are confirmed for PMOS2 or NMOS2 conducting; High level signal makes the NMOS2 conducting; Low level signal makes the PMOS2 conducting), through the source electrode of PMOS2 or the source electrode of NMOS2 level signal is exported to PMOS1 and NMOS1, make that (according to level signal is that high level or low level are confirmed for PMOS1 or NMOS1 conducting; High level signal makes the NMOS1 conducting; Low level signal makes the PMOS1 conducting), through the source electrode of PMOS1 or the source electrode of NMOS1 level signal is exported to PMOS2 or NMOS2, thereby level signal is latched.At this moment; Even the level signal of local bitline changes; Can not influence the level signal that outputs to global bit line yet, guarantee the level signal of stable output storage unit, and can change the analog level signal of storage unit feedback into digital signal level.
The global bit line amplification module is composed in series by reverse amplifying unit, latch units and reverser; Wherein, Latch units also can adopt multiple mode to realize, such as above-mentioned mode, reverse amplifying unit also can adopt accomplished in many ways; Fig. 3 is a concrete circuit diagram of realizing of the reverse amplifying unit in the global bit line amplification module of prior art, comprising: PMOS3, NMOS3, PMOS4 and NMOS4.Wherein,
The grid of PMOS3 is connected with the grid of NMOS3, inserts global bus; The drain electrode of PMOS3 is connected with the drain electrode of NMOS3; The source electrode of PMOS3 is connected with the drain electrode of PMOS4, and the source electrode of PMOS4 connects high level, and grid is connected with latch signal; The source electrode of NMOS3 is connected with the drain electrode of NMOS3, and the source electrode of PMOS4 connects low level, and grid is connected with the OEN signal.
When work, open latch signal and OEN signal, conducting PMOS4 and NMOS4 make the source electrode of PMOS3 connect high level respectively, the source electrode of NMO3 connects low level.The level signal of the storage unit in the global bus makes that (according to level signal is that high level or low level are confirmed for PMOS3 or NMOS3 conducting; High level signal makes the NMOS3 conducting; Low level signal makes the PMOS3 conducting); Be input to after the reverse amplification through PMOS3 or NMOS3 (enlargement factor is confirmed by the character of PMOS3 or NMOS3) in the latch units,, export to external unit after reverse through reverser through latching.
Though above-mentioned amplification latch cicuit can reading cells each storage unit of zone data of storing, electric energy that but can labor.This be because, in reading the whole process of data that each storage unit store, apply current work all need for the amplification latch cicuit, particularly apply current work, the electric energy that this will labor to the local bitline latch module.In addition, be connected with the local bitline of memory cell region owing to amplify latch cicuit, and the storage unit in the memory cell region generally all is the capacitance-resistance structure; This is the load of amplifying latch cicuit, and when the Number of Storage Units on the local bitline was a lot, it is big that load also will become; Especially along with development of semiconductor; Semiconductor devices is more and more integrated, and characteristic dimension is more and more littler, and the Number of Storage Units on local bitline also can get more and more.This all can be when reading the data that each storage unit stores, the electric energy of labor.
Summary of the invention
In view of this, the present invention provides a kind of amplifying circuit that latchs that is applied in the storer, and this circuit can reduce the electric energy that expends when the data of reading cells storage.
The present invention also provides a kind of read method of memory cell region storage data of storer, and this method can reduce the electric energy that expends when the data of reading cells storage.
For achieving the above object, the technical scheme that the present invention implements specifically is achieved in that
A kind of amplifying circuit that latchs that is applied in the storer comprises a plurality of local bitline latch module and a global bit line amplification module, wherein,
The local bitline latch module; Be used for according to the precharge pulse signal that applies; Through local bitline is the storage unit charging on the local bitline, when the storage unit on the wait local bitline is passed through local bitline feedback levels signal, again according to the control signal that is applied; Send to the global bit line amplification module after receiving this level signal, the data that the level signal indication storage unit of said feedback is stored;
The global bit line amplification module is used for receiving through global bit line the level signal of the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
The local bitline latch module comprises control module and latch units, wherein,
Control module is used for according to the precharge pulse unblanking latch units that applies, and when the storage unit on the wait local bitline is passed through local bitline feedback levels signal, opens latch units once more according to the control signal that applies;
Latch units, being used for when opening through local bitline is the storage unit charging on the local bitline, receives the level signal of storage unit through the local bitline feedback on the local bitline, exports to the global bit line amplification module after latching.
Described local bitline latch module is connected on the local bitline one to one;
Be connected with a plurality of local bitline latch module on the perhaps same local bitline, be respectively the partial memory cell charging on the said local bitline.
Said local bitline latch module is made up of latch units and control module, wherein,
This latch units is made up of the first P-type mos PMOS, the 2nd PMOS, a N type metal oxide semiconductor NMOS and the 2nd NMOS,
The source electrode of the one PMOS is connected with the drain electrode of the 2nd PMOS; The drain electrode of the one PMOS is connected with the drain electrode of a NMOS, and the source electrode of a NMOS is connected with the drain electrode of the 2nd NMOS, and the source electrode of the 2nd NMOS is connected with the source electrode of the 2nd PMOS; After the grid of the grid of the 2nd PMOS and the 2nd NMOS is connected; Insert first connecting line of a PMOS and a NMOS, this first connecting line is connected with local bitline, after the grid of a NMOS and a PMOS is connected; Insert second connecting line of the 2nd PMOS and the 2nd NMOS, this second connecting line connects global bus;
Control module is made up of the 3rd PMOS, the 4th PMOS and the 3rd NMOS, and the grid of the 3rd PMOS inserts the precharge pulse signal, and source electrode connects high level, and drain electrode inserts the connecting line of the 2nd PMOS and the 2nd NMOS; The grid of the 4th PMOS connects first control signal, and source electrode connects high level, and drain electrode inserts a PMOS and the 2nd PMOS respectively;
The grid of the 3rd NMOS connects second control signal, and source electrode connects low level, and drain electrode inserts a NMOS1 and the 2nd NMOS2 respectively;
The precharge pulse signal that applies makes the 3rd PMOS conducting, gives the charging of the storage unit on this local bitline with the precharge pulse signal through local bitline; When the storage unit feedback levels signal on this local bitline; Applying first control signal makes its conducting for the 4th PMOS and applies second control signal and make its conducting for the 3rd NMOS; Make win PMOS and the 2nd PMOS in running order, make win NMOS and the 2nd NMOS in running order;
Storage unit feedback levels signal on this local bitline makes the 2nd PMOS or the 2nd NMOS conducting; Through the source electrode of the 2nd PMOS or the source electrode of the 2nd NMOS this level signal is exported to a PMOS or a NMOS1; Make win a PMOS or a NMOS conducting; Through the source electrode of a PMOS or the source electrode of a NMOS this level signal is exported to the 2nd PMOS and the 2nd NMOS, after this level signal is latched, export to global bit line.
A kind of read method of the memory cell region storage data to storer is characterized in that this method comprises:
Latching when local bitline latch module in the amplifying circuit is applied in the precharge pulse signal and open, is the storage unit charging on the local bitline through local bitline;
The storage unit that latchs on the local bitline latch module wait local bitline in the amplifying circuit is passed through local bitline feedback levels signal; Open once more when being added control signal; Obtain this level signal; Send to the global bit line amplification module that latchs in the amplifying circuit, the data that the level signal indication storage unit of said feedback is stored;
Latch global bit line amplification module in the amplifying circuit and receive the level signal of the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
Described local bitline latch module is connected on the local bitline one to one;
Be connected with a plurality of local bitline latch module on the perhaps same local bitline, be respectively the partial memory cell charging on the said local bitline.
Visible by technique scheme; The present invention increases control module in the local bitline latch module; Close after being used to adopt precharge pulse unblanking latch units; Latch units is the storage unit charging on the local bitline through local bitline, waits by the time open latch units through control signal again during time for reading point, receives the level signal of the storage unit of feeding back through local bitline.Latch units is exported to the global bit line amplification module after being used for this level signal that receives latched.Because scheme provided by the invention is not to read in the process all for the local bitline latch module provides electric energy, so than prior art, reduced spent electric energy whole.In addition; The number of memory cells of the present invention on same local bitline makes a local bitline have a plurality of local bitline latch module more for a long time, reads the data that a partial memory cell on the local bitline is stored respectively; Like this; Targetedly to wanting reading cells power supply, rather than electric energy all is provided, has further saved electric energy the storage unit on all these local bitline.
To sum up, provided by the invention being applied in latched amplifying circuit and read method in the storer, when the data of reading cells storage, reduces the electric energy that expends.
Description of drawings
Fig. 1 latchs the amplifying circuit synoptic diagram for prior art;
Fig. 2 is a concrete circuit diagram of realizing of the local bitline latch module of prior art;
Fig. 3 is a concrete circuit diagram of realizing of the amplifying unit in the global bit line amplification module of prior art;
Fig. 4 is amplifying circuit embodiment one synoptic diagram that latchs provided by the invention;
Fig. 5 is the concrete circuit diagram of realizing of of local bitline latch module provided by the invention;
Fig. 6 is the read method process flow diagram of the memory cell region storage data of storer provided by the invention;
Fig. 7 is amplifying circuit embodiment two synoptic diagram that latch provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is done further explain.
Can find out from prior art, when being positioned at the data that each storage unit of same local bitline stores in the reading cells zone, read in the process, latch amplifying circuit and all need apply electric current, so the electric energy that this can labor whole.But; Read in the process whole, latch amplifying circuit and at first will apply electric current, be used to each storage unit charging on the local bitline local bitline; After after a while; Each storage unit on the local bitline just can be latched amplifying circuit through local bitline feedback levels signal, at this moment latchs amplifying circuit and just starts working, and the level signal that latchs through amplification after handling is offered external unit.Therefore, each storage unit on local bitline is charged in the process of feedback levels signal, and latching amplifying circuit does not need work, but owing to be applied with electric current, so also can consume electric power.
In order to address this problem; The present invention has reset the local bitline latch module that latchs in the amplifying circuit; Increase control module in the local bitline latch module; Close after being used to adopt precharge pulse unblanking latch units, wait, receive the level signal of the storage unit of feeding back through local bitline by the time open latch units through control signal again during time for reading point.Latch units is exported to the global bit line amplification module after being used for this level signal that receives latched.Because scheme provided by the invention is not all for the local bitline latch module electric energy to be provided whole reading in the process; Each storage unit on local bitline is charged in the process of feedback levels signal; It is not local bitline latch module extra current; Do not need consume electric power, so, reduced spent electric energy than prior art yet.
Further, the prior art consume electric power is many, also is that particularly the characteristic dimension along with semiconductor devices is more and more littler because the storage unit on the local bitline too much causes, and the storage unit on the same local bitline can be more.Because the storage unit on the local bitline all is the capacitance-resistance structure, when on local bitline, applying electric current, no matter whether feed back the data (confirming) of being stored by word line through local bitline, all can consume electric power.So,, also all need expend a large amount of electric energy through latching amplifying circuit simultaneously for all storage unit chargings on this local bitline even only read data that storage unit is stored on the local bitline.Therefore; The present invention makes a local bitline have a plurality of local bitline latch module; Read the data that a partial memory cell on the local bitline is stored respectively, like this, targetedly to wanting the reading cells power supply; Rather than the storage unit on all these local bitline all supplied power, further saved electric energy.
Below circuit provided by the invention and read method are elaborated.
Fig. 4 is the amplifying circuit synoptic diagram that latchs provided by the invention, and is as shown in the figure, comprises local bitline latch module and global bit line amplification module, wherein,
The local bitline latch module has a plurality of; Connecting local bitline respectively, be used for according to the precharge pulse signal that applies, is the storage unit charging on the local bitline through local bitline; When the storage unit on the wait local bitline is passed through local bitline feedback levels signal; Again according to the control signal that is applied, send to the global bit line amplification module, the data that the level signal indication storage unit of said feedback is stored after receiving this level signal;
The global bit line amplification module is used for receiving through global bit line the level signal of the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
In the present invention, the local bitline latch module comprises control module and latch units, wherein,
Control module is used for according to the precharge pulse unblanking latch units that applies, and when the storage unit on the wait local bitline is passed through local bitline feedback levels signal, opens latch units according to the control signal that applies;
Latch units, being used for when opening through local bitline is the storage unit charging on the local bitline, receives storage unit on the local bitline through local bitline feedback levels signal, exports to the global bit line amplification module after latching.
In the present invention; Precharge pulse signal and control signal are all provided by external unit; External unit is according to the characteristic of storer; Can know in advance that storage unit is fed back the time period length that obtains level signal from being charged to through local bitline in the storer, thereby send precharge pulse signal and control signal at corresponding time point according to this time period length.
In the present invention, the width of precharge pulse signal is also confirmed according to the storage unit character on the local bitline.
Latch units in the local bitline latch module provided by the invention can adopt accomplished in many ways, oppositely connects realization such as two phase inverters, perhaps adopts the described structure of Fig. 2, and control module of the present invention also can adopt accomplished in many ways.
Fig. 5 is the concrete circuit diagram of realizing of of local bitline latch module provided by the invention, and wherein, this latch units adopts the MOS of 2 P types and the MOS of 2 N types to form, and is respectively PMOS1, PMOS2, NMOS1 and NMOS2.Wherein,
The source electrode of PMOS1 is connected with the drain electrode of PMOS2, and the drain electrode of PMOS1 is connected with the drain electrode of NMOS1, and the source electrode of NMOS1 is connected with the drain electrode of NMOS2; The source electrode of NMOS2 is connected with the source electrode of PMOS2, and the grid of PMOS2 inserts first connecting line of PMOS1 and NMOS1 with after the grid of NMOS2 is connected; This first connecting line is connected with local bitline; After the grid of NMOS1 and PMOS1 is connected, insert second connecting line of PMOS2 and NMOS2, this second connecting line is as output.
Control module is realized by PMOS5, PMOS6 and NMOS5.Wherein,
The grid of PMOS5 is used to insert the precharge pulse signal, and source electrode connects high level (Vdd), and drain electrode inserts the connecting line of PMOS2 and NMOS2;
The grid of PMOS6 connects control signal 1, and source electrode connects high level, and drain electrode inserts PMOS1 and PMOS2 respectively;
The grid of NMOS5 connects control signal 2, and source electrode connects low level, and drain electrode inserts NMOS1 and NMOS2 respectively.
When Where topical bit line latch module will read the data that the storage unit on the local bitline stores through local bitline; At first send the precharge pulse signal by external unit; After the PMOS5 conducting, give the charging of the storage unit on this local bitline through local bitline with the precharge pulse signal; When the storage unit feedback levels signal on this local bitline; External unit 1 (low level signal) that transmit control signal given NMOS5 to PMOS6 and 2 (high level signals) that transmit control signal; Make PMOS6 and NMOS5 conducting, give PMOS1 and PMOS2 by the drain electrode input low level of PMOS6 respectively, make that PMOS1 and PMOS2 are in running order; Drain electrode input high level by NMOS5 is given NMOS1 and NMOS2, makes that NMOS1 and NMOS2 are in running order.Storage unit feedback levels signal on this local bitline makes that (according to level signal is that high level or low level are confirmed for PMOS2 or NMOS2 conducting; High level signal makes NMOS2 conducting, low level signal make the PMOS2 conducting), through the source electrode of PMOS2 or the source electrode of NMOS2 level signal is exported to PMOS1 and NMOS1; Make that (according to level signal is that high level or low level are confirmed for PMOS1 or NMOS1 conducting; High level signal makes NMOS1 conducting, low level signal make the PMOS1 conducting), through the source electrode of PMOS1 or the source electrode of NMOS1 level signal is exported to PMOS2 or NMOS2; Thereby after level signal latched, export to global bit line.At this moment,, can not influence the level signal that outputs to global bit line yet, guarantee the level signal of stable output storage unit even the level signal of local bitline changes.
Fig. 6 is the read method process flow diagram of the memory cell region storage data of storer provided by the invention, and this method is based on the described amplifying circuit that latchs of Fig. 4, and concrete steps are:
Step 603, latch the level signal that global bit line amplification module in the amplifying circuit receives the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
In the present invention; Each bar local bitline for storer; Not only only connect a local bitline latch module; And connect a plurality of local bitline latch module, and local bitline is separated, read the data that the partial memory cell on this local bitline is stored by different local bitline latch module respectively.As shown in Figure 7; Fig. 7 is amplifying circuit embodiment two synoptic diagram that latch provided by the invention; On same local bitline, have a plurality of local bitline latch module; Be used for receiving respectively the level signal of the partial memory cell on this local bitline, the structure of each local bitline latch module is all as shown in Figure 4.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the amplifying circuit that latchs that is applied in the storer is characterized in that, comprises a plurality of local bitline latch module and a global bit line amplification module, wherein,
The local bitline latch module; Be used for according to the precharge pulse signal that applies; Through local bitline is the storage unit charging on the local bitline, when the storage unit on the wait local bitline is passed through local bitline feedback levels signal, again according to the control signal that is applied; Send to the global bit line amplification module after receiving this level signal, the data that the level signal indication storage unit of said feedback is stored;
The global bit line amplification module is used for receiving through global bit line the level signal of the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
2. the amplifying circuit that latchs as claimed in claim 1 is characterized in that the local bitline latch module comprises control module and latch units, wherein,
Control module is used for according to the precharge pulse unblanking latch units that applies, and when the storage unit on the wait local bitline is passed through local bitline feedback levels signal, opens latch units once more according to the control signal that applies;
Latch units, being used for when opening through local bitline is the storage unit charging on the local bitline, receives the level signal of storage unit through the local bitline feedback on the local bitline, exports to the global bit line amplification module after latching.
According to claim 1 or claim 2 latch amplifying circuit, it is characterized in that described local bitline latch module is connected on the local bitline one to one;
Be connected with a plurality of local bitline latch module on the perhaps same local bitline, be respectively the partial memory cell charging on the said local bitline.
4. the amplifying circuit that latchs as claimed in claim 1 is characterized in that said local bitline latch module is made up of latch units and control module, wherein,
This latch units is made up of the first P-type mos PMOS, the 2nd PMOS, a N type metal oxide semiconductor NMOS and the 2nd NMOS,
The source electrode of the one PMOS is connected with the drain electrode of the 2nd PMOS; The drain electrode of the one PMOS is connected with the drain electrode of a NMOS, and the source electrode of a NMOS is connected with the drain electrode of the 2nd NMOS, and the source electrode of the 2nd NMOS is connected with the source electrode of the 2nd PMOS; After the grid of the grid of the 2nd PMOS and the 2nd NMOS is connected; Insert first connecting line of a PMOS and a NMOS, this first connecting line is connected with local bitline, after the grid of a NMOS and a PMOS is connected; Insert second connecting line of the 2nd PMOS and the 2nd NMOS, this second connecting line connects global bus;
Control module is made up of the 3rd PMOS, the 4th PMOS and the 3rd NMOS, and the grid of the 3rd PMOS inserts the precharge pulse signal, and source electrode connects high level, and drain electrode inserts the connecting line of the 2nd PMOS and the 2nd NMOS; The grid of the 4th PMOS connects first control signal, and source electrode connects high level, and drain electrode inserts a PMOS and the 2nd PMOS respectively;
The grid of the 3rd NMOS connects second control signal, and source electrode connects low level, and drain electrode inserts a NMOS1 and the 2nd NMOS2 respectively;
The precharge pulse signal that applies makes the 3rd PMOS conducting, gives the charging of the storage unit on this local bitline with the precharge pulse signal through local bitline; When the storage unit feedback levels signal on this local bitline; Applying first control signal makes its conducting for the 4th PMOS and applies second control signal and make its conducting for the 3rd NMOS; Make win PMOS and the 2nd PMOS in running order, make win NMOS and the 2nd NMOS in running order;
Storage unit feedback levels signal on this local bitline makes the 2nd PMOS or the 2nd NMOS conducting; Through the source electrode of the 2nd PMOS or the source electrode of the 2nd NMOS this level signal is exported to a PMOS or a NMOS1; Make win a PMOS or a NMOS conducting; Through the source electrode of a PMOS or the source electrode of a NMOS this level signal is exported to the 2nd PMOS and the 2nd NMOS, after this level signal is latched, export to global bit line.
5. one kind is utilized the described circuit of claim 1 that the memory cell region of storer is stored the read method of data, it is characterized in that this method comprises:
Latching when local bitline latch module in the amplifying circuit is applied in the precharge pulse signal and open, is the storage unit charging on the local bitline through local bitline;
The storage unit that latchs on the local bitline latch module wait local bitline in the amplifying circuit is passed through local bitline feedback levels signal; Open once more when being added control signal; Obtain this level signal; Send to the global bit line amplification module that latchs in the amplifying circuit, the data that the level signal indication storage unit of said feedback is stored;
Latch global bit line amplification module in the amplifying circuit and receive the level signal of the storage unit that the local bitline latch module sends, amplify latch after, export to external unit.
6. method as claimed in claim 5 is characterized in that, described local bitline latch module is connected on the local bitline one to one;
Be connected with a plurality of local bitline latch module on the perhaps same local bitline, be respectively the partial memory cell charging on the said local bitline.
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| CN109979504A (en) * | 2019-03-29 | 2019-07-05 | 长江存储科技有限责任公司 | A kind of static random access memory control circuit |
| CN110660430A (en) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Memory device, memory input/output circuit and method thereof |
| CN113035263A (en) * | 2021-04-14 | 2021-06-25 | 长鑫存储技术有限公司 | Signal processing circuit and memory containing channel ECC |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107437425A (en) * | 2016-05-25 | 2017-12-05 | 格罗方德半导体公司 | Matched line for the matched line sensing of self reference is pre-charged framework |
| CN107437425B (en) * | 2016-05-25 | 2020-12-08 | 马维尔亚洲私人有限公司 | Matchline precharge architecture for self-referenced matchline sensing |
| CN110660430A (en) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Memory device, memory input/output circuit and method thereof |
| CN110660430B (en) * | 2018-06-29 | 2021-12-24 | 台湾积体电路制造股份有限公司 | Memory device, memory input/output circuit and method thereof |
| US11295791B2 (en) | 2018-06-29 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM with local bit line, input/output circuit, and global bit line |
| CN109979504A (en) * | 2019-03-29 | 2019-07-05 | 长江存储科技有限责任公司 | A kind of static random access memory control circuit |
| CN113035263A (en) * | 2021-04-14 | 2021-06-25 | 长鑫存储技术有限公司 | Signal processing circuit and memory containing channel ECC |
| CN113035263B (en) * | 2021-04-14 | 2022-05-31 | 长鑫存储技术有限公司 | Signal processing circuit and memory containing channel ECC |
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| CN102385899B (en) | 2014-05-21 |
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