CN102376753A - Silicon germanium source/drain structure and manufacturing method thereof - Google Patents
Silicon germanium source/drain structure and manufacturing method thereof Download PDFInfo
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- CN102376753A CN102376753A CN2010102615801A CN201010261580A CN102376753A CN 102376753 A CN102376753 A CN 102376753A CN 2010102615801 A CN2010102615801 A CN 2010102615801A CN 201010261580 A CN201010261580 A CN 201010261580A CN 102376753 A CN102376753 A CN 102376753A
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Abstract
The invention provides a silicon germanium source/drain structure which comprises a substrate, a grid electrode structure and a stair-shaped silicon germanium source/drain area, wherein the grid electrode structure is located on the substrate; the stair-shaped silicon germanium source/drain area is formed in the substrate, is located on two sides of the grid electrode structure and at least comprises a first depth silicon germanium layer and a second depth silicon germanium layer; the depth of the first depth silicon germanium layer is more than the depth of the second depth silicon germanium layer; the second depth silicon germanium layer is tightly close to the first depth silicon germanium layer; and compared with the first depth silicon germanium layer, the second depth silicon germanium layer is more close to the grid electrode structure. In the silicon germanium source/drain structure provided by the invention, by forming the stair-shaped silicon germanium source/drain structure, a channel of a transistor can bear higher stress and characteristics of an extending knot are never reduced, thereby being capable of further promoting hole-mobility and promoting the property of the transistor.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make field, particularly a kind of silicon Germanium source/drain structure and manufacturing approach thereof.
Background technology
Industry is applied in the selective epitaxial growth process of SiGe on the semiconductor technology at present, to increase mobility of charge carrier rate and cost benefit.Embedding SiGe (SiGe) technology has become a kind of promising technology for producing based on the high-performance transistor of silicon.The radius of the radius ratio silicon atom of germanium atom is big, so when germanium atom replacement part silicon atom, in the time of in the lattice (lattice) of entering silicon, whole lattice can so and twist.When the charge density of charge carrier was identical, the silicon or the sige alloy of lattice distortion were compared with monocrystalline silicon, and the mobility in its electronics and hole is significantly increase all, increases respectively about 5 and 10 times, just can reduce element resistance thus.Existing known in the silicon substrate of next-door neighbour's transistor channel embedding SiGe can on raceway groove, produce stress, thereby improve hole mobility, improve transistorized performance.But how can further improve the stress of raceway groove and can not reduce the extension junction characteristic further developing research then need be arranged technically.
Summary of the invention
The technical problem that the present invention will solve provides a kind of silicon Germanium source/drain structure and manufacturing approach thereof, with further raising channel stress and hole mobility, improves transistorized performance.
For solving the problems of the technologies described above, the present invention provides a kind of silicon Germanium source/drain structure, comprising:
Substrate;
Be positioned at the grid structure on the said substrate;
Be formed in the substrate, be positioned at the stepped ramp type silicon Germanium source/drain region of said grid structure both sides; Said stepped ramp type silicon Germanium source/drain region comprises first degree of depth germanium-silicon layer and second degree of depth germanium-silicon layer at least; The degree of depth of said first degree of depth germanium-silicon layer is greater than said second degree of depth germanium-silicon layer; Adjacent said first degree of depth germanium-silicon layer of said second degree of depth germanium-silicon layer, said second degree of depth germanium-silicon layer compared to said first degree of depth germanium-silicon layer more near said grid structure.
Optional, the degree of depth of said first degree of depth germanium-silicon layer is 450～800 dusts.
Optional, the degree of depth of said second degree of depth germanium-silicon layer is 100～250 dusts.
Optional, the transverse width of said second degree of depth germanium-silicon layer is 1nm～30nm.
The present invention also provides a kind of manufacturing approach of silicon Germanium source/drain structure, comprising:
Form grid structure at substrate surface, form insulating gap wall in the both sides of said grid structure;
Said substrate is carried out etching, form source/drain region first depressed part in the both sides of said insulating gap wall;
Said insulating gap wall is carried out etching, its transverse width is reduced, form new insulating gap wall and expose a part of substrate that is positioned at originally under the insulating gap wall;
The said substrate that exposes is carried out etching, formation source/drain region second depressed part, said source/drain region second depressed part is close to said source/drain region first depressed part, and the degree of depth of said source/drain region second depressed part is shallower than said source/drain region first depressed part;
Growth forms stepped ramp type silicon Germanium source/drain region in said source/drain region first depressed part and said source/drain region second depressed part;
Mixed in said stepped ramp type silicon Germanium source/drain region.
Optional, the transverse width of said insulating gap wall is 5nm～60nm.
Optional, the degree of depth of said source/drain region first depressed part is 450～800 dusts.
Optional, the degree of depth of said source/drain region second depressed part is 100～250 dusts.
Optional, the transverse width of said source/drain region second depressed part is 1nm～30nm.
Because germanium-silicon layer can improve the stress of raceway groove more the closer to raceway groove; Therefore in silicon Germanium source/drain structure of the present invention; Make transistorized raceway groove can bear bigger stress and can not reduce the extension junction characteristic through the silicon Germanium source/drain structure that forms the stepped ramp type shape; Therefore can further improve hole mobility, improve transistorized performance.
Description of drawings
Fig. 1 is the cross section structure sketch map of silicon Germanium source/drain structure of the present invention;
Fig. 2 a-Fig. 2 e is the manufacturing approach sketch map of preparation a kind of silicon Germanium source/drain structure shown in Figure 1.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Silicon Germanium source/drain structure of the present invention and manufacturing approach thereof multiple substitute mode capable of using realizes; Be to explain below through preferred embodiment; Certainly the present invention is not limited to this specific embodiment, and the general replacement that the one of ordinary skilled in the art knew is encompassed in protection scope of the present invention undoubtedly.
Secondly, the present invention utilizes sketch map to describe in detail, and when the embodiment of the invention was detailed, for the ease of explanation, sketch map disobeyed that general ratio is local amplifies, should be with this as to qualification of the present invention.
Please with reference to Fig. 1, Fig. 1 is the cross section structure sketch map of silicon Germanium source/drain structure of the present invention.As shown in Figure 1, silicon Germanium source/drain structure of the present invention comprises:
Be positioned at the grid structure 110 on the said substrate 100;
Be formed in the substrate 100; Be positioned at the stepped ramp type silicon Germanium source/drain region 120 of said grid structure 110 both sides; Said stepped ramp type silicon Germanium source/drain region 120 comprises first degree of depth germanium-silicon layer 121 and second degree of depth germanium-silicon layer 122 at least; The degree of depth of said first degree of depth germanium-silicon layer 121 is greater than said second degree of depth germanium-silicon layer 122; Said second degree of depth germanium-silicon layer, 121 adjacent said first degree of depth germanium-silicon layers 122, said second degree of depth germanium-silicon layer 122 compared to said first degree of depth germanium-silicon layer 121 more near said grid structure 110.
The degree of depth of said first degree of depth germanium-silicon layer 121 is 450～800 dusts, and the degree of depth of said second degree of depth germanium-silicon layer 122 is 100～250 dusts, and horizontal (direction that is parallel to said substrate) width of said second degree of depth germanium-silicon layer 122 is 1nm～30nm.
Please with reference to Fig. 2 a-Fig. 2 e, Fig. 2 a-Fig. 2 e is the manufacturing approach sketch map of preparation a kind of silicon Germanium source/drain structure shown in Figure 1.
At first, shown in Fig. 2 a, in substrate 100, form isolation structure 101, on said substrate 100, form grid structure 110 again, also form insulating gap wall 113 in the both sides of said grid structure 110.
Wherein, said substrate 100 can be a silicon substrate, and said isolation structure 101 can be the silica fleet plough groove isolation structure.Said grid structure 110 from bottom to top comprises gate dielectric layer 111 and gate electrode 112, and the material of said gate dielectric layer 111 can be a silica, and the material of said gate electrode 112 can be DOPOS doped polycrystalline silicon, metal, metal silicide or other conductor.Said insulating gap wall 113 can be insulating material such as silica, the silicon nitride of individual layer, or the insulating material of multilayer.The transverse width of said insulating gap wall 113 is thicker slightly compared to the thickness of common insulating gap wall, is 5nm～60nm.
Subsequently, shown in Fig. 2 b, said substrate 100 is carried out etching, form source/drain region first depressed part 102 in the both sides of said insulating gap wall 110.The degree of depth of said source/drain region first depressed part is 450～800 dusts.
Then, shown in Fig. 2 c, said insulating gap wall 113 is carried out etching, its transverse width that is parallel on the said substrate 100 is reduced, form new insulating gap wall 113 ' and expose a part of substrate that is positioned at originally under the insulating gap wall 113.Said lithographic method can be dry etching or wet etching.
Follow again; Shown in Fig. 2 d; The said substrate that exposes is carried out etching; Both sides at said new insulating gap wall 113 ' form source/drain region second depressed part 103; Said source/the drain region of second depressed part, 103 next-door neighbours, said source/drain region first depressed part 102, the degree of depth of said source/drain region second depressed part 103 are shallower than said source/drain region first depressed part 102 and said source/drain region second depressed part 103, and first depressed part 102 more approaches said new insulating gap wall 113 ' compared to said source/drain region.The transverse width of said source/drain region second depressed part 103 is 1nm～30nm, and the degree of depth of said source/drain region second depressed part is 100～250 dusts.
Then, shown in Fig. 2 e, growth forms stepped ramp type silicon Germanium source/drain region 120 in said source/drain region first depressed part 102 and said source/drain region second depressed part 103.Said stepped ramp type silicon Germanium source/drain region 120 comprises first degree of depth germanium-silicon layer 121 and second degree of depth germanium-silicon layer 122 at least; The degree of depth of said first degree of depth germanium-silicon layer 121 is greater than said second degree of depth germanium-silicon layer 122; Said second degree of depth germanium-silicon layer, 121 adjacent said first degree of depth germanium-silicon layers 122, said second degree of depth germanium-silicon layer 122 compared to said first degree of depth germanium-silicon layer 121 more near said grid structure 110.
Forming said stepped ramp type silicon Germanium source/drain region can adopt chemical gas-phase deposition method to form.
At last, mixed to adjust its electricity and chemical attribute in said stepped ramp type silicon Germanium source/drain region 200.Doping can be used various dopants and adopt various doping techniques to carry out.Can adopt p type impurity such as boron to be mixed in source/drain region 200, to form the PMOS transistor.Those skilled in the art is when knowing that also available other technology is mixed to source/drain region 200.
Because germanium-silicon layer can improve the stress of raceway groove more the closer to raceway groove; Therefore in silicon Germanium source/drain structure of the present invention; Make transistorized raceway groove can bear bigger stress and can not reduce the extension junction characteristic through the silicon Germanium source/drain structure that forms the stepped ramp type shape; Therefore can further improve hole mobility, improve transistorized performance.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. silicon Germanium source/drain structure comprises:
Substrate;
Be positioned at the grid structure on the said substrate;
Be formed in the substrate, be positioned at the stepped ramp type silicon Germanium source/drain region of said grid structure both sides; Said stepped ramp type silicon Germanium source/drain region comprises first degree of depth germanium-silicon layer and second degree of depth germanium-silicon layer at least; The degree of depth of said first degree of depth germanium-silicon layer is greater than said second degree of depth germanium-silicon layer; Adjacent said first degree of depth germanium-silicon layer of said second degree of depth germanium-silicon layer, said second degree of depth germanium-silicon layer compared to said first degree of depth germanium-silicon layer more near said grid structure.
2. silicon Germanium source/drain structure as claimed in claim 1 is characterized in that, the degree of depth of said first degree of depth germanium-silicon layer is 450～800 dusts.
3. silicon Germanium source/drain structure as claimed in claim 1 is characterized in that, the degree of depth of said second degree of depth germanium-silicon layer is 100～250 dusts.
4. silicon Germanium source/drain structure as claimed in claim 1 is characterized in that, the transverse width of said second degree of depth germanium-silicon layer is 1nm～30nm.
5. the manufacturing approach of a silicon Germanium source/drain structure comprises:
Form grid structure at substrate surface, form insulating gap wall in the both sides of said grid structure;
Said substrate is carried out etching, form source/drain region first depressed part in the both sides of said insulating gap wall;
Said insulating gap wall is carried out etching, its transverse width is reduced, form new insulating gap wall and expose a part of substrate that is positioned at originally under the insulating gap wall;
The said substrate that exposes is carried out etching, formation source/drain region second depressed part, said source/drain region second depressed part is close to said source/drain region first depressed part, and the degree of depth of said source/drain region second depressed part is shallower than said source/drain region first depressed part;
Growth forms stepped ramp type silicon Germanium source/drain region in said source/drain region first depressed part and said source/drain region second depressed part;
Mixed in said stepped ramp type silicon Germanium source/drain region.
6. the manufacturing approach of silicon Germanium source/drain structure as claimed in claim 5 is characterized in that, the transverse width of said insulating gap wall is 5nm～60nm.
7. the manufacturing approach of silicon Germanium source/drain structure as claimed in claim 5 is characterized in that, the degree of depth of said source/drain region first depressed part is 450～800 dusts.
8. the manufacturing approach of silicon Germanium source/drain structure as claimed in claim 5 is characterized in that, the degree of depth of said source/drain region second depressed part is 100～250 dusts.
9. the manufacturing approach of silicon Germanium source/drain structure as claimed in claim 5 is characterized in that, the transverse width of said source/drain region second depressed part is 1nm～30nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409352A (en) * | 2014-11-26 | 2015-03-11 | 上海华力微电子有限公司 | Manufacturing method of embedded germanium-silicon device |
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| CN1855535A (en) * | 2005-04-18 | 2006-11-01 | 株式会社东芝 | Step-embedded sige structure for pfet mobility enhancement |
| CN101133482A (en) * | 2005-01-06 | 2008-02-27 | 英特尔公司 | Device with stepped source/drain region profile |
| CN101483190A (en) * | 2008-01-09 | 2009-07-15 | 国际商业机器公司 | MOSFET having a high stress in the channel region and fabricating method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101133482A (en) * | 2005-01-06 | 2008-02-27 | 英特尔公司 | Device with stepped source/drain region profile |
| CN1855535A (en) * | 2005-04-18 | 2006-11-01 | 株式会社东芝 | Step-embedded sige structure for pfet mobility enhancement |
| CN101483190A (en) * | 2008-01-09 | 2009-07-15 | 国际商业机器公司 | MOSFET having a high stress in the channel region and fabricating method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409352A (en) * | 2014-11-26 | 2015-03-11 | 上海华力微电子有限公司 | Manufacturing method of embedded germanium-silicon device |
| CN104409352B (en) * | 2014-11-26 | 2017-05-24 | 上海华力微电子有限公司 | Manufacturing method of embedded germanium-silicon device |
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Application publication date: 20120314 |