CN102376626B - Reduce the method for size of through hole in semiconductor device - Google Patents
Reduce the method for size of through hole in semiconductor device Download PDFInfo
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- CN102376626B CN102376626B CN201010251339.0A CN201010251339A CN102376626B CN 102376626 B CN102376626 B CN 102376626B CN 201010251339 A CN201010251339 A CN 201010251339A CN 102376626 B CN102376626 B CN 102376626B
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Abstract
The invention provides a kind of method reducing size of through hole in semiconductor device, comprise (a) and front-end devices structure is provided, front-end devices structure has interlayer dielectric layer, interlayer dielectric layer has hard mask layer, hard mask layer is formed with the photoresist layer with patterns of openings, the size L of patterns of openings is greater than the through hole desired value D of setting; B () take photoresist layer as mask etching hard mask layer, patterns of openings is transferred to hard mask layer, until exposed portion interlayer dielectric layer; C () take photoresist layer as mask, adopt the etching condition identical with step (b) to etch hard mask layer, etch period=A × (L-D), A are a coefficient; D () take photoresist layer as mask etching interlayer dielectric layer, to form the through hole being of a size of desired value.According to the present invention, can size of through hole in semiconductor device be reduced, and can be formed the through hole of required size by the etch period adjusting hard mask layer in actual production.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly reduce the method for size of through hole in semiconductor device.
Background technology
Integrated circuit fabrication process is a kind of plane manufacture craft, and it, in conjunction with kinds of processes such as photoetching, etching, deposition, ion implantations, forms a large amount of various types of complex devices on the same substrate, and be connected to each other to have complete function.
In order to form interconnection line in the conductive layer more than two-layer, often need in semiconductor process to make a large amount of through holes.Along with semiconductor fabrication is advanced to more advanced deep sub-micron technique, the number of plies of semiconductor metal line gets more and more, and corresponding via etch process step also gets more and more, and the size of through hole also progressively reduces along with the reduction of device layout size.Be fabricated to example with DRAM (dynamic random access memory), when memory space develops into 512M by 4M, design rule narrows down to 0.16 μm by 1 μm, and wherein the size of through hole also drops to 0.25 μm from 0.8 μm.Clear size of opening is less, and the difficulty of etching is also increasing, and the formation quality of through hole is very large for the performance impact of circuit, especially for below 65nm technique, if deviation appears in its process results, the electrical property of circuit will be caused to be deteriorated, and time serious, device is by cisco unity malfunction.
In existing technique, form the method for the through hole in semiconductor device as shown in Figure 1A to 1B.
As shown in Figure 1A, deposit one deck etching stop layer 102 first on the substrate 101, metallization medium layer 103 on etching stop layer 102, this layer requires the layer of dielectric material for low k (dielectric constant).Hard mask layer 104 is formed on the surface of dielectric layer 103, bottom anti-reflection layer 105 is formed on the surface of hard mask layer 104, then at surface application one deck photoresist layer of this bottom anti-reflection layer 105, the figuratum photoresist layer 106 of tool is formed by exposure imaging method.
As shown in Figure 1B, with photoresist layer 106 for mask, etching bottom anti-reflecting layer 105, hard mask layer 104 and dielectric layer 103 successively, until etching stop layer 102, forms through hole 107.Wherein, when etching hard mask layer 104, namely change another gas after the etching technics of hard mask layer 104 completes with the dielectric layer 103 below etch.Cineration technics is finally adopted to remove photoresist layer 106 and bottom anti-reflection layer 105.
In order to reduce the size of through hole, generally achieved the goal by the patterns of openings reducing photoresist layer in traditional technique.The such as patent No. is the method that patent discloses a kind of re-expose by double-tiered arch dam formation fine pattern of 03102525.0, and its shortcoming is can not utilize legacy equipment and complex process; The patent No. be 200310124851.9 patent discloses a kind of method forming fine pattern, its shortcoming is to adopt new equipment and increases processing step and be difficult to accurately control the critical size of photoetching agent pattern.Therefore, need a kind of new method, can either size of through hole in semiconductor device be reduced, or can not need to adopt new equipment and production cost is increased because of increase processing step again.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The invention provides a kind of method forming through hole, comprise: (a) provides front-end devices structure, described front-end devices structure has interlayer dielectric layer, described interlayer dielectric layer has hard mask layer, described hard mask layer is formed with the photoresist layer with patterns of openings, the size L of described patterns of openings is greater than the through hole desired value D of setting; B () for mask, etches described hard mask layer with described photoresist layer, described patterns of openings is transferred to described hard mask layer, until interlayer dielectric layer described in exposed portion; C (), with described photoresist layer for mask, adopt the etching condition identical with step (b) to etch described hard mask layer, etch period=A × (L-D), wherein A is a coefficient; (d) with described photoresist layer for mask, etch described interlayer dielectric layer, to form the through hole being of a size of described desired value.
Preferably, wherein A between 1 second/nanometer to 2 second/nanometer.
Preferably, also comprise: between described front-end devices structure and described interlayer dielectric layer, also there is etching stop layer.
Preferably, also comprise: between described hard mask layer and described photoresist layer, also there is anti-reflecting layer, and after implementation step (a) and before implementation step (b), with described photoresist layer for anti-reflecting layer described in mask etching, until expose the described hard mask layer of below.
Preferably, described anti-reflecting layer the second bottom anti-reflection layer of being bottom anti-reflection layer or comprising the first bottom anti-reflection layer be formed on described hard mask layer, be formed at the low temperature oxide layer above described first bottom anti-reflection layer and be formed at above described low temperature oxide layer.
Preferably, the described etch period of (c) step is 1 ~ 15 second.
Preferably, the material that described hard mask layer adopts is silicon dioxide.
Preferably, the method etching described hard mask layer is dry etching, and the etching gas adopted is for comprising CHF
3with the mist of oxygen or comprise CH
2f
2with the mist of oxygen.
Preferably, the flow velocity of described oxygen is 10 ~ 25sccm.
Preferably, the volume ratio that described oxygen is shared in described mist is 5% ~ 20%.
Preferably, also comprise, after implementation step (a) and before implementation step (b), carry out plasma discharge treatment to the described photoresist layer with patterns of openings, described plasma discharge treatment comprises N for first adopting
2and H
2mist carry out the first discharge process and adopt N separately again
2carry out the second discharge process.
Preferably, in described first discharge process, N in described mist
2flow velocity be 10 ~ 100sccm, H
2flow velocity be 50 ~ 200sccm, discharge power is 200 ~ 1000W, and discharge time is 10 ~ 25 seconds.
Preferably, in described second discharge process, described N
2flow velocity be 20 ~ 100sccm, discharge power is 200 ~ 500W, and discharge time is 10 ~ 25 seconds.
According to the present invention, size of through hole in semiconductor device can be reduced, and can be formed the through hole of required size by the etch period adjusting hard mask layer in actual production, do not increase any processing step, yet need not adopt new equipment and production cost be increased.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Figure 1B is the cross-sectional view of traditional formation through hole;
Fig. 2 A to 2D is the schematic diagram of formation through hole according to an embodiment of the invention;
Fig. 3 is the schematic diagram forming the polymer adhesion condition generated in the process of through hole;
Fig. 4 is the process chart of the method forming through hole according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention reduces size of through hole in semiconductor device.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the clearly aid illustration embodiment of the present invention.Should understand, when mention one deck another layer " on " time, this layer directly above, or can have one or more intermediate layer.In addition, should also be understood that mention one deck two layers " between " time, it can be layer between the two layers, or also can have one or more intermediate layer.
According to the embodiment of one aspect of the invention as shown in Fig. 2 A to Fig. 2 D.
As shown in Figure 2 A, provide front-end devices structure 201, this front-end devices structure 201 comprises the device structure layer formed in preorder technique, such as metal interconnect structure layer etc.The concrete conductor layer that is exemplified as is formed in front-end devices structure 201, and conductor layer is the metal level needing to be drawn out to device surface, such as copper.Alternatively, can form etching stop layer 202 on the surface of front-end devices structure 201, material can be chosen as silicon nitride, and generation type can be chosen as CVD (chemical vapour deposition (CVD)) method.Then form interlayer dielectric layer 203 on the surface of etching stop layer 202, material can be but the one be not limited in silica, carborundum, silicon nitride, carbon silicon oxide compound, nitrogen-doped silicon carbide or its combination.Form hard mask layer 204 on the surface of interlayer dielectric layer 203, material can be the silicon dioxide adopting TEOS (tetraethyl orthosilicate salt) to make for source gas, and generation type can be CVD.Hard mask layer 204 can also be other material, such as SiC, SiN and SiON etc., can also be other any material being used as hard mask layer known in those skilled in the art.This hard mask layer 204 can as the etching barrier layer formed in via process, to avoid the damage to interlayer dielectric layer 203 in etching technics.Then, alternatively, anti-reflecting layer 205 is formed on the surface of hard mask layer 204.This anti-reflecting layer can be independent bottom anti-reflection layer (BARC), also can be to comprise the second bottom anti-reflection layer being formed at the first bottom anti-reflection layer on hard mask layer 204, being formed at the low temperature oxide layer (LTO) on the first bottom anti-reflection layer and being formed on low temperature oxide layer.Finally, at the surface application photoresist layer 206 of anti-reflecting layer 205.
As shown in Figure 2 B, the techniques such as exposure imaging are carried out to form the figuratum photoresist layer of tool to photoresist layer 206, namely has the photoresist layer 206 ' of patterns of openings 207.The size of patterns of openings 207 is set as L, and L is greater than the size of the final required through hole formed, and setting through hole is of a size of desired value D, L > D.Wherein, the size of L is 50 ~ 500nm, is preferably 80 ~ 150nm, is more preferably 90 ~ 120nm.In order to make the size L of patterns of openings 207 consistent with design load, alternatively, using plasma discharge processing method carries out the process of residue to patterns of openings 207, with avoid the existence due to residue make the size of patterns of openings 207 and design load inconsistent thus cause the dimension D of the through hole finally formed and the inconsistent situation of desired value.Preferably, first employing comprises N
2and H
2mist carry out the first discharge process, wherein N
2flow velocity be 10 ~ 100sccm, H
2flow velocity be 50 ~ 200sccm, discharge power is 200 ~ 1000W, and discharge time is 10 ~ 25 seconds.Then N is adopted
2carry out the second discharge process, N
2flow velocity be 20 ~ 100sccm, discharge power is 200 ~ 500W, and discharge time is 10 ~ 25 seconds.Wherein, sccm is under standard state, namely 1 atmospheric pressure, the flow of 1 cubic centimetre (1ml/min) per minute under 25 degrees Celsius.Alternatively, oxygen can also be adopted to carry out plasma discharge process to patterns of openings 207, the flow velocity of such as oxygen is 10 ~ 100sccm, and discharge power is 200 ~ 500W, and discharge time is 10 ~ 30 seconds.
As shown in Figure 2 C, with photoresist layer 206 ' for mask, etch anti-reflecting layer 205 and hard mask layer 204 successively, patterns of openings 207 to be transferred on anti-reflecting layer 205 and hard mask layer 204.Wherein, if the material of hard mask layer is silicon dioxide, at etching hard mask layer 204 so that patterns of openings 207 is transferred in the step on hard mask layer 204, preferably, adopts and comprise CHF
3with the mist of oxygen or comprise CH
2f
2carry out dry etching with the mist of oxygen to hard mask layer 204, wherein the flow velocity of oxygen is chosen for 10 ~ 25sccm.It is pointed out that other can also be adopted to well known to a person skilled in the art according to the material of hard mask layer 204 method etches hard mask layer 204, but not be confined to the method that adopts in the middle of the present embodiment.After step patterns of openings 207 being transferred to hard mask layer 204 completes, behind the surface of i.e. exposed portion interlayer dielectric layer 203, continue to adopt identical etching condition to etch hard mask layer 204, namely the etch period to hard mask layer 204 is extended, set etch period S=A × (L-D) of this step, wherein A is a coefficient.The value that can reduce the size of through hole in actual industrial as required selects the etch period of prolongation.Generally, A is between 1 second/nanometer to 2 second/nanometer.Such as, as L-D=6nm, the etch period S of this prolongation may be selected to be 6 ~ 12 seconds.In practical application, S is generally 1 ~ 15 second.
Extend the etch period of hard mask layer 204, namely after step patterns of openings 207 being transferred to hard mask layer 204 completes, do not change etching condition and still hard mask layer 204 etched, find that the size of last formed through hole 208 reduces, and the size of through hole 208 reduces gradually along with the increase of S.As shown in Figure 3, occur that the reason inventor of such result thinks, meeting polymerization reaction take place in the process of etching hard mask layer 204, after step patterns of openings 207 being transferred to hard mask layer 204 completes, do not change etching condition and proceed etching, the part that hard mask layer 204 comes out understands polymerization reaction take place equally, and etching gas now can't have an impact to interlayer dielectric layer 203.At the beginning, what produce in polymerization reaction also can be taken away by extract system containing C or containing H or containing F or containing the polymer of Si, along with the prolongation of time, polymer can be attached to the edge from hard mask layer 204 to photoresist layer 206 ' gradually, with patterns of openings 207 place attachment maximum, increasing of polymer causes the size of photoresist layer 206 ' patterns of openings 207 to reduce gradually, and the polymer at time longer patterns of openings 207 place is more, the polymer of going out by patterns of openings 207 is fewer, and the size of patterns of openings 207 is more and more less.Therefore, when ensuing etching interlayer dielectric layer 203, the size of the through hole finally formed is that the size of the patterns of openings 207 had with photoresist layer 206 ' is at that time as the criterion, now the size of the patterns of openings 207 of photoresist layer 206 ' reduces, and therefore the size of the last through hole formed also can reduce.Alternatively, the CHF adopted in the present embodiment
3with mist or the CH of oxygen
2f
2with the mist of oxygen, the volume shared by oxygen is smaller, such as, be about 5% ~ 20%, and smaller being conducive to of the volume shared by oxygen generates polymer.
As shown in Figure 2 D, after prolongation completes the step of the etch period of hard mask layer 204, change another etching gas to etch interlayer dielectric layer 203, until expose etching stop layer 202, form through hole 208.Adopt in the present embodiment and comprise CF
4interlayer dielectric layer 203 is etched with the mist of Ar.It is pointed out that those skilled in the art can also adopt other known mode to etch interlayer dielectric layer 203, but not be confined to the mode that adopts in the present embodiment.
According to the present invention, just can reach to the etch period of hard mask layer the object reducing the clear size of opening formed by means of only extending, and can be formed the through hole of required size by the etch period adjusting hard mask layer in actual production, do not increase any processing step, yet need not adopt new equipment and production cost be increased.
The flow chart of Fig. 4 shows the process chart reducing size of through hole in semiconductor device according to an embodiment of the invention.In step 401, front-end devices structure is provided, front-end devices structure has interlayer dielectric layer, interlayer dielectric layer has hard mask layer, hard mask layer is formed with the photoresist layer with patterns of openings, the size L of patterns of openings is greater than the through hole desired value D of setting.In step 402, take photoresist layer as mask, etching hard mask layer, transfers to hard mask layer by patterns of openings, until exposed portion interlayer dielectric layer.In step 403, take photoresist layer as mask, adopt and front step, the etching condition that namely step 402 is identical etches hard mask layer, etch period=A × (L-D), and wherein A is a coefficient.In step 404, take photoresist layer as mask, etching interlayer dielectric layer, to form the through hole being of a size of desired value.
Have and can be applicable in multiple integrated circuit (IC) according to the semiconductor device of the through hole of embodiment manufacture as above.Such as memory circuitry according to IC of the present invention, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for such as consumer electronic products, as in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. reduce a method for size of through hole in semiconductor device, comprising:
A () provides front-end devices structure, described front-end devices structure has interlayer dielectric layer, described interlayer dielectric layer has hard mask layer, described hard mask layer is formed with the photoresist layer with patterns of openings, the size L of described patterns of openings is greater than the through hole desired value D of setting;
B () for mask, etches described hard mask layer with described photoresist layer, described patterns of openings is transferred to described hard mask layer, until interlayer dielectric layer described in exposed portion;
(c) with described photoresist layer for mask, the etching condition identical with step (b) is adopted to etch described hard mask layer, to reduce the size of described photoresist layer split shed pattern, the size of described photoresist layer split shed pattern is made to equal through hole desired value D, etch period=A × (L-D), wherein A is a coefficient; With
D () for mask, etches described interlayer dielectric layer with described photoresist layer, to form the through hole being of a size of described desired value.
2. the method for claim 1, wherein A is between 1 second/nanometer to 2 second/nanometer.
3. the method for claim 1, also comprises:
Between described front-end devices structure and described interlayer dielectric layer, also there is etching stop layer.
4. the method for claim 1, also comprises:
Also there is anti-reflecting layer between described hard mask layer and described photoresist layer, and after implementation step (a) and before implementation step (b), with described photoresist layer for anti-reflecting layer described in mask etching, until expose the described hard mask layer of below.
5. method as claimed in claim 4, it is characterized in that, the second bottom anti-reflection layer that described anti-reflecting layer is bottom anti-reflection layer or comprises the first bottom anti-reflection layer be formed on described hard mask layer, is formed at the low temperature oxide layer above described first bottom anti-reflection layer and is formed at above described low temperature oxide layer.
6. the method for claim 1, is characterized in that, the described etch period of (c) step is 1 ~ 15 second.
7. the method for claim 1, is characterized in that, the material that described hard mask layer adopts is silicon dioxide.
8. method as claimed in claim 7, it is characterized in that, the method etching described hard mask layer is dry etching, and the etching gas adopted is for comprising CHF
3with the mist of oxygen or comprise CH
2f
2with the mist of oxygen.
9. method as claimed in claim 8, it is characterized in that, the flow velocity of described oxygen is 10 ~ 25sccm.
10. method as claimed in claim 8, is characterized in that, the volume ratio of described oxygen shared by described mist is 5% ~ 20%.
11. the method for claim 1, also comprise,
After implementation step (a) and before implementation step (b), carry out plasma discharge treatment to the described photoresist layer with patterns of openings, described plasma discharge treatment comprises N for first adopting
2and H
2mist carry out the first discharge process and adopt N separately again
2carry out the second discharge process.
12. methods as claimed in claim 11, is characterized in that, in described first discharge process, and N in described mist
2flow velocity be 10 ~ 100sccm, H
2flow velocity be 50 ~ 200sccm, discharge power is 200 ~ 1000W, and discharge time is 10 ~ 25 seconds.
13. methods as claimed in claim 11, is characterized in that, in described second discharge process, and described N
2flow velocity be 20 ~ 100sccm, discharge power is 200 ~ 500W, and discharge time is 10 ~ 25 seconds.
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| CN101459074A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Etching method and dual damascene structure forming method |
| CN101471286A (en) * | 2007-12-28 | 2009-07-01 | 东部高科股份有限公司 | Method for forming metal line of semiconductor device |
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| US7183195B2 (en) * | 2002-02-22 | 2007-02-27 | Samsung Electronics, Co., Ltd. | Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler |
| US20040192058A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pre-etching plasma treatment to form dual damascene with improved profile |
| CN100499038C (en) * | 2006-09-27 | 2009-06-10 | 联华电子股份有限公司 | Manufacturing method for contact hole |
| CN101593725A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of contact hole |
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| CN101459074A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Etching method and dual damascene structure forming method |
| CN101471286A (en) * | 2007-12-28 | 2009-07-01 | 东部高科股份有限公司 | Method for forming metal line of semiconductor device |
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