CN102376581A - MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof - Google Patents
MOS (Metal-Oxide-Semiconductor) transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an MOS (Metal-Oxide-Semiconductor) transistor and a manufacturing method thereof. The method comprises the following steps of: providing a semiconductor substrate, wherein a gate structure is formed on the semiconductor substrate; carrying out carbon ion implantation on the semiconductor substrates at two sides of the gate structure to form a defect adsorption zone; carrying out an oxidation process to form an oxide layer covering the gate structure; and sequentially forming a source/drain extension zone and a baggy implantation zone surrounding the source/drain extension zone in the semiconductor substrates at the two sides of the gate structure, wherein the size of the baggy implantation zone along the channel length direction is less than or equal to the size of the defect adsorption zone. In the invention, carbon ions are formed before the oxidation process is carried out; and by utilizing the defects formed by carbon ion adsorption and oxidation processes, the oxidation enhanced diffusion effect and the transient enhanced diffusion effect are eliminated, and the short channel effect and the adverse short channel effect are improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly MOS transistor and preparation method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is made, and they are in various integrated circuits, and the doping type during according to main charge carrier and manufacturing is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of manufacture method of MOS transistor.Please refer to Fig. 1 to Fig. 3, be the manufacture method cross-sectional view of the MOS transistor of prior art.
Please refer to Fig. 1; Semiconductor substrate 100 is provided, in said Semiconductor substrate 100, forms isolation structure 101, the Semiconductor substrate 100 between the said isolation structure 101 is an active area; In said active area, form the dopant well (not shown), in dopant well, adjust threshold voltage and inject.
Then, on the Semiconductor substrate 100 between the said isolation structure 101, form gate dielectric layer 102 and grid 103 successively, said gate dielectric layer 102 constitutes grid structure with grid 103.
Continuation is carried out oxidation technology with reference to figure 1, forms the oxide layer 104 that covers said grid structure.
With reference to figure 2, in the Semiconductor substrate of grid structure both sides, form source/drain extension region 105 successively, surround the bag shape injection region 108 of said source/drain extension region 105, said source/drain extension region 105 injects through ion with a bag shape injection region 108 and forms.Said bag shape injection region 108 forms through the injection of bag shape (pocket) ion.The dopant ion of the ion that bag shape ion injects can be phosphonium ion (for nmos pass transistor) or boron ion (for the PMOS transistor).
With reference to figure 3, on the Semiconductor substrate of grid structure both sides, form the side wall 111 of grid structure.Carry out source/drain electrode heavy doping and inject (S/D), formation source/drain electrode 112 in the Semiconductor substrate 100 of grid structure both sides, last, carry out annealing process, the dopant ion of activation of source/drain extension region 105, bag shape injection region 108, source/drain electrode 112.
, publication number can find more information in being the one Chinese patent application of CN 101789447A about prior art.
In reality, find; There is transient enhanced diffusion effect (Transistent Enhanced Diffusion in the MOS transistor that existing method is made; TED) defective, said transient enhanced diffusion effect have not only caused transistorized short-channel effect, and (Short Channel effect is SCE) with anti-short-channel effect (Reverse Short Channel Effect; And influence transistor channel mobility, junction capacitance and junction leakage RSCE).
Therefore, need a kind of manufacture method of MOS transistor, can transient suppression enhancement effect, the short-channel effect of suppression device and anti-short-channel effect.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of MOS transistor, has reduced the transient state enhancement effect, has improved the short-channel effect and the anti-short-channel effect of device.
For addressing the above problem, the present invention provides a kind of manufacture method of MOS transistor, comprising:
Semiconductor substrate is provided, is formed with grid structure on the said Semiconductor substrate;
The Semiconductor substrate of said grid structure both sides is carried out carbon ion inject, form the defective adsorption zone;
Carry out oxidation technology, form the oxide layer that covers said grid structure;
In the Semiconductor substrate of grid structure both sides, form source/drain extension region successively, surround the bag shape injection region of said source/drain extension region, said bag shape injection region is along the size of the orientation size smaller or equal to said defective adsorption zone.
Alternatively, the angle of inclination of said carbon ion injection is 15～45 degree.
Alternatively, the energy range of said carbon ion injection is: 2KeV～20KeV.
Alternatively, the dosage range of said carbon ion injection is: 1E14～3E16/cm
-2
Alternatively, said carbon ion is injected to the anglec of rotation and injects, and the start angle that the said anglec of rotation is injected is 0～45 degree.
Alternatively, the temperature of said oxidation technology is 700～1200 degrees centigrade, and the time is 10～100 minutes.
Alternatively, thickness of oxide layer 1.5～4 nanometers of said oxidation technology formation.
The present invention also provides a kind of MOS transistor, comprising:
Semiconductor substrate has grid structure on the said Semiconductor substrate;
Source/drain extension region is arranged in the Semiconductor substrate of said grid structure both sides;
Bag shape injection region is arranged in the Semiconductor substrate of said grid structure both sides, and said bag shape injection region surrounds said source/drain extension region;
Oxide layer covers said grid structure;
The defective adsorption zone; Be arranged in the Semiconductor substrate of said grid structure both sides; Said defective adsorption zone is along the size of the orientation size more than or equal to said bag shape injection region, and said defective adsorption zone injects through ion and forms, and the dopant ion of said defective adsorption zone is a carbon ion.
Alternatively, said thickness of oxide layer 1.5～4 nanometers.
Compared with prior art, the present invention has the following advantages:
Through in the Semiconductor substrate of grid structure both sides, injecting carbon ion; Form the defective adsorption zone; Carbon ion in the said defective adsorption zone is the defective that in Semiconductor substrate, causes of adsorption and oxidation technology effectively, and the defective that before bag shape injection region and source/drain extension region form, oxidation technology is formed is eliminated, thereby the dopant ion that effectively prevents follow-up bag shape injection region and source/drain extension region is along with defective spreads; Eliminate the oxidation-enhanced diffusion effect, suppressed the transient enhanced diffusion effect.
Further optimally, the temperature of said oxidation technology is 700～1200 degrees centigrade, and the time is 10～100 minutes; Utilize oxidation technology that the dopant ion of said defective adsorption zone is annealed; Repaired carbon ion and injected the damage that Semiconductor substrate is caused, and annealing makes carbon ion before formation source/drain extension region and bag shape injection region, in Semiconductor substrate, evenly distribute; Help carbon ion and fully absorb the defective in the Semiconductor substrate; And the dopant ion of avoiding carbon ion and source/drain extension region and bag shape injection region is at same annealing steps, and to the influence that is distributed with of source/drain extension region and bag dopant ion of shape injection region, thereby the present invention need not the dopant ion of consideration source/drain extension region and bag shape injection region and the relation that carbon ion distributes; Simplify technology, helped improving the stability of device.
Description of drawings
Fig. 1 to Fig. 3 is the manufacture method cross-sectional view of the MOS transistor of prior art.
Fig. 4 is a MOS transistor manufacture method schematic flow sheet of the present invention.
Fig. 5～Fig. 8 is the MOS transistor manufacture method cross-sectional view of one embodiment of the invention.
Fig. 9 is the channel length and the threshold voltage graph of relation of MOS transistor of the present invention.
Figure 10 is the drain saturation current and the threshold voltage graph of relation of MOS transistor of the present invention.
Embodiment
The inventor finds; Prior art forms in the method for MOS transistor, before formation source/drain extension region and bag shape injection region, carries out oxidation technology; Grid is protected in the peripheral oxide layer that forms of grid structure; But said oxidation technology can form defective in Semiconductor substrate, and said defective is called oxidation-enhanced diffusion (Oxidation-Enhanced Diffusion, OED) effect.Because the defective that the oxidation-enhanced diffusion effect causes can spread in subsequent annealing technology, make the source/drain extension region and the dopant ion of bag shape injection region spread thereupon, caused the transient state enhancement effect, strengthened the short-channel effect and the anti-short-channel effect of device.
Find through the research inventor; If after the peripheral formation of grid structure oxide layer; Carry out ion in bag shape injection region and inject, non-foreign ion (for example carbon ion) is injected Semiconductor substrate, can adsorb because the defective that oxidation technology causes in Semiconductor substrate.But be that defective can be further introduced in non-foreign ion injection itself in Semiconductor substrate, this defective also can influence the distribution of the source/drain extension region and the foreign ion of bag shape injection region.If foreign ion activates in same annealing steps with the dopant ion of bag shape injection region and source/drain extension region; Also can make the distribution influence bag shape injection region of non-foreign ion and the dopant ion of source/drain extension region distribute; Make that the dopant ion distribution of device is too complicated, be unfavorable for the control of technology and device property stability.
In order to address the above problem, the inventor proposes a kind of manufacture method of MOS transistor, please refer to Fig. 4, is MOS transistor manufacture method schematic flow sheet of the present invention.
Said method comprises:
Step S1 provides Semiconductor substrate, is formed with grid structure on the said Semiconductor substrate;
Step S2 carries out carbon ion to the Semiconductor substrate of said grid structure both sides and injects, and forms the defective adsorption zone;
Step S3 carries out oxidation technology, forms the oxide layer that covers said grid structure;
Step S4 forms source/drain extension region successively, surrounds the bag shape injection region of said source/drain extension region in the Semiconductor substrate of grid structure both sides, said bag shape injection region is along the size of the orientation size smaller or equal to said defective adsorption zone.
To combine concrete embodiment that technical scheme of the present invention is carried out detailed description below.Please refer to Fig. 5～Fig. 8, be the MOS transistor manufacture method cross-sectional view of one embodiment of the invention.
At first, please refer to Fig. 5, Semiconductor substrate 200 is provided, be formed with isolation structure 201 in the said Semiconductor substrate 200, the Semiconductor substrate outside the said isolation structure 201 is an active area.On the Semiconductor substrate between the isolation structure 201 200, be formed with gate dielectric layer 202 and grid 203 successively, said gate dielectric layer 202 constitutes grid structure with grid 203.
Wherein, said Semiconductor substrate 200 can be silicon (Si) or silicon-on-insulator (SOI).Said isolation structure 201 can leave (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench isolation.
Said gate dielectric layer 202 can be silica (SiO
2) or silicon oxynitride (SiNO).At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric layer 202 preferred high-k (high K) materials.Said hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.The formation technology of gate dielectric layer 202 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, the thickness of gate dielectric layer 202 is 15 to 60 dusts.
Said grid 203 can be the sandwich construction that comprises semi-conducting material, for example silicon, germanium, metal or its combination.The formation technology of said grid 203 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, for example low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology.The thickness of grid 203 is 800 to 3000 dusts.
Then,, the Semiconductor substrate 200 of said grid structure both sides is carried out carbon ion inject, form defective adsorption zone 213 with reference to figure 6.
In the follow-up oxidation technology of carrying out when on grid, forming oxide layer; Defective adsorption zone 213 carbon ions can be with the absorption of the defective that forms in the Semiconductor substrate, forms group bunch with defective, thereby defective is pricked surely around carbon ion; Reduced the number of free defective like this; Avoid defective in of the dopant ion diffusion of subsequent annealing activation of source/drain extension region, eliminate the oxidation-enhanced diffusion effect, reduced the transient enhanced diffusion effect with bag shape injection region.And; Because defective and carbon ion form group bunch, make the Semiconductor substrate of part of the group of formation bunch form irregular lattice arrangement, thereby make that the atom of Semiconductor substrate is arranged regular more on the whole; Lattice is more orderly; The scattering that the dopant ion of source/drain extension region and bag shape injection region receives reduces, thereby the diffusivity of said dopant ion reduces, and has further reduced the transient enhanced diffusion effect.
The inventor also finds, because the carbon ion injection can cause the Semiconductor substrate damage of grid structure both sides, can utilize annealing process that said Semiconductor substrate is repaired, and activate said carbon ion.Said annealing process be boiler tube annealing (furnace anneal) or rapid thermal annealing (Rapid Thermal Anneal, RTA).As the preferred embodiments of the present invention; Can also utilize follow-up oxidation technology that carbon ion is annealed in grid structure formation oxide layer; So not only practice thrift processing step, and damage that can the repairing semiconductor substrate, made the arranging evenly of carbon ion; And help carbon ion more and fully absorb the defective that oxidation technology produces, avoid the distribution of distribution influence source/drain extension region with the dopant ion of bag shape injection region of carbon ion.
In order to guarantee that effectively eliminating the oxide-diffused effect causes the transient enhanced diffusion effect; Said defective adsorption zone 213 should be more than or equal to the source/drain extension region of follow-up formation and the size of bag shape injection region along the size of orientation; Can effectively eliminate the defective of source/drain extension region and bag shape injection region like this, the ion of avoiding source/drain extension region and bag shape injection region is along with defective spreads.The defective that produces in the defective adsorption zone 213 is adsorbed by carbon ion with the defective that diffuses in the defective adsorption zone 213, and the carbon ion of defective adsorption zone 213 can suppress the dopant ion diffusion of source/drain extension region and bag shape injection region.
Usually, before carbon ion injects, need utilize mask (mask), carry out photoetching process, on Semiconductor substrate 200, form the photoresist of patterning, said photoresist exposed portions serve Semiconductor substrate; Be mask with said photoresist then, the Semiconductor substrate of exposing carried out ion inject, form defective adsorption zone 213.
As preferred embodiment, said carbon ion injects the mask of utilizing existing bag shape injection region, carries out photoetching process, on Semiconductor substrate 200, forms photoresist, and the semiconductor substrate region that said photoresist exposes is identical with the position of bag shape injection region.For the defective adsorption zone 213 that guarantees follow-up formation is not less than bag width of shape injection region along the size of channel direction, when the present invention injects at carbon ion, preferably select for use big angle of inclination to inject.The angle of inclination that ion of the present invention injects specifically is meant the direction of beam line (ion beam) and the angle of wafer normal direction.Big angle of inclination of the present invention specifically is meant, the angle of inclination that carbon ion injects is greater than the angle of inclination of the ion injection of bag shape injection region.The angle of inclination of injecting with the ion of bag shape injection region is that 15～35 degree are example, and the angle of inclination that said carbon ion injects is 15～45 degree, is preferably 15～35 degree.
As other embodiment; Said carbon ion injects and can utilize independent mask to carry out photoetching; On Semiconductor substrate, form photoresist; The size of the semiconductor substrate region that said photoresist exposes is greater than the size of bag shape injection region, and the angle of inclination that said carbon ion injects can be 0～45 degree.Those skilled in the art can carry out concrete selection.
As one embodiment of the present of invention, said carbon ion is injected to the anglec of rotation and injects.The start angle that said rotation is injected is 0～45 degree.The anglec of rotation of the present invention is injected and be meant that specifically wafer rotates in being parallel to the plane of its circular surface.As an embodiment, the start angle that the said anglec of rotation is injected with wafer begins, and carries out twice or four rotations, and the anglec of rotation each time is 180 degree or 360 degree.As other enforcement, said rotation can also be 6 times, the inferior rotation of 8 inferior even numbers.
As an embodiment, the energy range that said carbon ion injects is 2KeV～20KeV.The depth bounds that said carbon ion injects is 5～70 nanometers.The dosage range that said carbon ion injects is 1E14～5E15/cm
-2
Then,, carry out oxidation technology, form the oxide layer 204 that covers said grid structure with reference to figure 7.
The temperature of said oxidation technology is 700～1200 degrees centigrade, and the time is 10～100 minutes.The time range of oxidation technology described in the present embodiment is 15 minutes～40 minutes.Utilize above-mentioned process conditions, the thickness of oxide layer of formation is 1.5～4 nanometers.
Said oxidation technology can form oxide layer on whole half conductive substrate 200 surfaces, then, need carry out etching technics, removes the oxide layer on the Semiconductor substrate 200 that is positioned at the grid structure both sides, keeps the oxide layer 204 that covers said grid structure.
Said oxidation technology is with the carbon ion annealing of defective injection region 213; Repair carbon ion and inject the defective that Semiconductor substrate is caused; And make carbon ion form certain arranging; Source/drain extension region of avoiding carbon ion and subsequent step to form is together annealed with the dopant ion in the bag shape injection region, influences the distribution of the dopant ion in source/drain extension region and the bag shape injection region.
Then; Please refer to Fig. 8; In the Semiconductor substrate 200 of grid structure both sides, form source/drain extension region 205 successively, surround the bag shape injection region 208 of said source/drain extension region; Said bag shape injection region 208 is along the size of the orientation size less than said defective adsorption zone 213, and being surrounded by defective adsorption zone 213 along orientation of said bag shape injection region 208.
The conduction type of said source/drain extension region 205 is N type or P type.The dopant ion of said source/drain extension region 205 can be in phosphonium ion, arsenic ion, boron fluoride ion, boron ion or the indium ion any one.Specifically decide according to the type of MOS transistor to be formed.For example when transistor was nmos pass transistor, the conduction type of said source/drain extension region 205 was N type (dopant ion can be phosphonium ion, arsenic ion); When transistor was the PMOS transistor, the conduction type of said source/drain extension region 205 was P type (dopant ion can be boron fluoride ion, boron ion or indium ion).
As an embodiment, said source/drain extension region 205 ions are the boron ion, and the energy range that ion injects is 2KeV to 5KeV, and the ion implantation dosage scope is 5E14 to 2E15/cm
-2As another embodiment, said source/drain extension region 205 ions are phosphonium ion, and the energy range that ion injects is 1KeV to 4KeV, and ion implantation dosage is 5E14 to 2E15/cm
-2
Said bag shape injection region 208 is through bag shape injection (Pocket implant), and the angle of inclination that general said bag shape injects is 15～35 degree, and the bag shape is injected to anglec of rotation injection, and the start angle that the said anglec of rotation is injected is 0～45 degree.As preferred embodiment; The start angle that said bag shape ion injects is identical with the start angle that carbon ion injects; The ion distribution that makes carbon ion inject the defective adsorption zone that forms is mated with the bag-like region ion distribution that the injection of bag shape ion forms more, more helps suppressing the oxidation enhancement effect.
Then, with reference to figure 8, in the Semiconductor substrate 200 of grid structure both sides, form side wall 211 on the Semiconductor substrate 200 of the transistorized source of formation/drain electrode 212 and grid structure both sides.Said source/drain electrode 212 is carried out source/leakage ion and is injected.The method that said source/leakage ion injects is identical with prior art with the manufacture method of side wall, as technology as well known to those skilled in the art, does not describe in detail at this.
At last, anneal, with the dopant ion activation of said source/drain extension region 205, bag shape injection region 208, source/drain electrode 212.Said annealing can be boiler tube annealing or rapid thermal annealing.As an embodiment, the said rapid thermal annealing that is annealed into.The temperature range of said annealing is 700～1200 degrees centigrade, and annealing time is 10～120 seconds, and anneal gas is N
2, its range of flow is 50～500sccm.
Through said method, form MOS transistor, please refer to Fig. 8, said MOS transistor comprises:
Source/drain electrode 212 is positioned at the Semiconductor substrate 200 of said side wall 211 1 sides;
Source/drain extension region 205 is positioned at the Semiconductor substrate 200 of said grid structure both sides;
Bag shape injection region 208 is positioned at the Semiconductor substrate 200 of said grid structure both sides, and said bag shape injection region 208 surrounds said source/drain extension region 205;
With reference to figure 9, for utilizing the TCAD simulation softward of this (synopsys) company of U.S.'s snop, with the nmos device example, MOS transistor and the channel length of MOS transistor of the present invention and the relation of threshold voltage of simulation prior art.Transverse axis is represented channel length, and unit is a micron; The longitudinal axis is represented threshold voltage, the unit volt.Curve 1 is the nmos device simulation acquisition to prior art, and curve 2 is that nmos device simulation of the present invention is obtained.Can find out that from figure curve 1 is precipitous, and curve 2 is much more smooth than curve 1.This shows that the grid voltage of the nmos pass transistor of prior art is along with the variation of channel length is comparatively obvious, and compared with prior art, the grid voltage of nmos pass transistor of the present invention is along with the variation of channel length is not obvious.Nmos pass transistor of the present invention is along with the variation of channel length; Variations in threshold voltage is very little; The ability of the control threshold voltage of nmos pass transistor of the present invention is stronger; The effective oxidation-enhanced diffusion effect and transient state diffusion enhancement effect of having suppressed of nmos pass transistor of the present invention is described, significantly reduced the short-channel effect and the anti-short-channel effect of device.
Figure 10 simulates MOS transistor and the MOS transistor drain saturation current of the present invention and the threshold voltage relation of prior art, is example with the nmos pass transistor.Abscissa is represented saturated drain leakage, and unit is a microampere/micron, and ordinate is represented threshold voltage, and unit is a volt.Curve 1 is the nmos device simulation acquisition to prior art, and curve 2 is that nmos device simulation of the present invention is obtained.Curve 1 is precipitous, and curve 2 is more smooth than curve 1.This shows; Along with drain saturation current increases; The nmos pass transistor threshold voltage variation of prior art is remarkable, and the threshold voltage variation of nmos pass transistor of the present invention is not remarkable, explains that the saturated drain current driving force of nmos pass transistor of the present invention is strong; Oxidation enhancement effect and transient state oxidation enhancement effect are inhibited, and significantly reduce the short-channel effect and the anti-short-channel effect of device.
To sum up, MOS transistor provided by the invention and preparation method thereof injected carbon ion in the Semiconductor substrate of the both sides of grid structure before the oxidation technology of grid structure; Form the defective adsorption zone; Said defective adsorption zone is eliminated the defective that oxidation technology forms in Semiconductor substrate, defective is pricked surely, prevents defective diffusion when annealing; The dopant ion diffusion of aggravation source/drain extension region and bag shape injection region, the transient suppression enhancing diffusion; And said carbon ion is annealed when oxidation technology; Reduce damage that Semiconductor substrate is caused, make carbon ion form fixing distribution, avoid the distribution influence source/drain extension region of carbon ion and the dopant ion of bag shape injection region to distribute; Simplify technology, improve the stability of technology.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the manufacture method of a MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, is formed with grid structure on the said Semiconductor substrate;
The Semiconductor substrate of said grid structure both sides is carried out carbon ion inject, form the defective adsorption zone;
Carry out oxidation technology, form the oxide layer that covers said grid structure;
In the Semiconductor substrate of grid structure both sides, form source/drain extension region successively, surround the bag shape injection region of said source/drain extension region, said bag shape injection region is along the size of the orientation size smaller or equal to said defective adsorption zone.
2. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, the angle of inclination that said carbon ion injects is 15～45 degree.
3. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, the energy range that said carbon ion injects is: 2KeV～20KeV.
4. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, the dosage range that said carbon ion injects is: 1E14～3E16/cm
-2
5. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, said carbon ion is injected to the anglec of rotation and injects, and the start angle that the said anglec of rotation is injected is 0～45 degree.
6. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, the temperature of said oxidation technology is 700～1200 degrees centigrade, and the time is 10～100 minutes.
7. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, thickness of oxide layer 1.5～4 nanometers that said oxidation technology forms.
8. a MOS transistor is characterized in that, comprising:
Semiconductor substrate has grid structure on the said Semiconductor substrate;
Source/drain extension region is arranged in the Semiconductor substrate of said grid structure both sides;
Bag shape injection region is arranged in the Semiconductor substrate of said grid structure both sides, and said bag shape injection region surrounds said source/drain extension region;
Oxide layer covers said grid structure;
The defective adsorption zone; Be arranged in the Semiconductor substrate of said grid structure both sides; Said defective adsorption zone is along the size of the orientation size more than or equal to said bag shape injection region, and said defective adsorption zone injects through ion and forms, and the dopant ion of said defective adsorption zone is a carbon ion.
9. MOS transistor as claimed in claim 8 is characterized in that, said thickness of oxide layer 1.5～4 nanometers.
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| CN104900591A (en) * | 2014-03-06 | 2015-09-09 | 美格纳半导体有限公司 | Low-cost semiconductor device manufacturing method |
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| CN101312208A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and method for forming same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104900591A (en) * | 2014-03-06 | 2015-09-09 | 美格纳半导体有限公司 | Low-cost semiconductor device manufacturing method |
| US10586863B2 (en) | 2014-03-06 | 2020-03-10 | Magnachip Semiconductor, Ltd. | Low-cost semiconductor device manufacturing method |
| CN104900591B (en) * | 2014-03-06 | 2020-06-05 | 美格纳半导体有限公司 | Low cost semiconductor device manufacturing method |
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