CN102376575A - Method for forming source-drain stress region of MOS transistor and method for manufacturing MOS transistor - Google Patents
Method for forming source-drain stress region of MOS transistor and method for manufacturing MOS transistor Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 13
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- 238000000137 annealing Methods 0.000 claims abstract description 20
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- 230000015572 biosynthetic process Effects 0.000 claims description 37
- 238000005516 engineering process Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 230000006835 compression Effects 0.000 claims description 7
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- 238000002347 injection Methods 0.000 claims description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
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- 229910052751 metal Inorganic materials 0.000 claims description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
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- 239000000377 silicon dioxide Substances 0.000 claims description 3
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- 229910052732 germanium Inorganic materials 0.000 claims description 2
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Abstract
A method for forming a source-drain stress region of a MOS transistor comprises the following steps: providing a semiconductor substrate, and forming a sacrificial gate on the semiconductor substrate; performing ion implantation on the semiconductor substrate, and forming an amorphous region in the semiconductor substrate on two sides of the sacrificial gate; forming a dielectric layer comprising intrinsic stress on the semiconductor substrate; and annealing the semiconductor substrate to form a source-drain stress region at the amorphous region on the two sides of the sacrificial gate. According to the method for forming the source-drain stress region of the MOS transistor, the dielectric layer containing the inherent stress is directly formed on the source-drain regions on the two sides of the grid to introduce the stress, so that the difficulty of filling the stress film above the source-drain region is reduced, and the stress conversion ratio of a channel is greatly improved. Meanwhile, stress is transferred to the source-drain region through the semiconductor substrate which is pre-amorphized at the source-drain region, so that the stress of the channel region after the original dielectric layer is etched and the side wall is formed is still maintained, and the carrier mobility is improved due to the stress change.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to formation method and MOS transistor manufacture method that the stressed zone is leaked in a kind of MOS transistor source.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more littler.Yet when the MOS transistor characteristic size was constantly dwindled, device power consumption and contradiction between speed highlighted day by day, and had hindered further developing of integrated circuit technique.
The carrier mobility that improves the MOS transistor channel region is the effective means that solves said power consumption-speed contradiction.On the basis that the channel region carrier mobility significantly promotes, MOS transistor can adopt lower supply voltage to reduce power consumption; Simultaneously can also guarantee that device has enough current driving abilities and speed.Common, improving carrier mobility at channel region introducing stress is a kind of efficient ways.For MOS transistor, the stress that channel region is introduced can change the lattice structure of substrate, and then influences the band structure of channel region, thereby influences the carrier mobility of channel region.
One Chinese patent application 200610146392.8 promptly discloses a kind of employing dual stress memory technique (Stress Memory Technique, SMT) method of introducing stress in MOS transistor.In the method; After the grid structure (comprising sidewall) of MOS transistor forms; Can on the Semiconductor substrate of nmos transistor region and PMOS transistor area, deposit film respectively, and handle in the channel region with the introducing of the stress in said stress film MOS transistor through subsequent annealing with tensile stress and compression.For nmos pass transistor, the tensile stress of channel region can promote drive current (corresponding to the raising of electron mobility), and for the PMOS transistor, the compression of channel region can promote drive current (corresponding to the raising of hole mobility).
Yet along with device feature size is reduced to below 45 nanometers, device pitch is more and more littler.Accordingly, the zone that can be used to deposit stress film on the source-drain area of grid both sides is more and more narrow also, especially after sidewall forms, has been difficult on substrate deposition stress distribution film comparatively uniformly again.
Summary of the invention
The problem that the present invention solves provides formation method and the MOS transistor manufacture method that the stressed zone is leaked in a kind of MOS transistor source; In the channel region of MOS transistor, introduced stress with simple and easy to do method; The stress of said introducing has improved the channel region carrier mobility, and then has improved the driving force of MOS transistor.
For addressing the above problem, the invention provides the formation method that the stressed zone is leaked in a kind of MOS transistor source, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, forms sacrificial gate;
Said Semiconductor substrate is carried out ion inject, in the Semiconductor substrate of sacrificial gate both sides, form amorphous area;
On said Semiconductor substrate, form the stressed dielectric layer that comprises natural stress;
Said Semiconductor substrate is carried out annealing in process, leak the stressed zone in the formation source, amorphous area position of sacrificial gate both sides.
Optional, for forming MOS transistor, also comprise:
After the stressed zone was leaked in the formation source, the said stressed dielectric layer of anisotropic etching formed sidewall in the sacrificial gate both sides;
After forming sidewall, in the Semiconductor substrate of sacrificial gate both sides, form shallow, dark doped region;
Adopt grid replacement technology between said sidewall, to form the gate dielectric layer of metal gates and high-k dielectric material formation.
Compared with prior art, the present invention has the following advantages:
1. the stressed dielectric layer that has natural stress is formed on the Semiconductor substrate and grid that does not comprise sidewall, and the zone of grid both sides source-drain area to be formed still has the area of broad, and this greatly reduces the formation difficulty of stress film;
Stressor layers through the decrystallized in advance Semiconductor substrate in source-drain area position with stress transfer in source-drain area, and influence the stress characteristics of channel region, the STRESS VARIATION of said channel region has improved carrier mobility, and then has strengthened the driving force of MOS transistor.
Description of drawings
Fig. 1 shows the flow process that stressed zone formation method is leaked in MOS transistor of the present invention source.
Fig. 2 to Fig. 9 shows the formation method that adopts MOS transistor of the present invention source to leak the stressed zone and makes the transistorized flow process of CMOS.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part, prior art is often through depositing stress film to introduce stress in the grid structure both sides that include sidewall.But along with device feature size is reduced to below 45 nanometers; Device pitch is more and more littler; The zone that can be used to deposit stress film on the source-drain area of grid both sides is more and more narrow also, especially after sidewall forms, has been difficult on substrate deposition stress distribution film comparatively uniformly again.
To the problems referred to above, inventor of the present invention provides a kind of stress memory technique that adopts to leak the method that forms the stressed zone in the MOS transistor source.Adopting this method to make in the process of MOS transistor, introducing stress through on the zone of grid both sides source-drain area to be formed, directly depositing the stressed dielectric layer that comprises natural stress.Because said stressed dielectric layer is formed on the Semiconductor substrate and grid that does not comprise sidewall, the grid both sides still have the area of broad, and this greatly reduces the formation difficulty of stress film.Simultaneously, said stressed dielectric layer still can form sidewall through anisotropic etching, and this has also reduced cost of manufacture.
With reference to figure 1, show the flow process that stressed zone formation method is leaked in MOS transistor of the present invention source, comprising:
Execution in step S102 provides Semiconductor substrate, on said Semiconductor substrate, forms sacrificial gate (dummy gate).
Execution in step S104 carries out ion to said Semiconductor substrate and injects, and in the Semiconductor substrate of sacrificial gate both sides, forms amorphous area.
Execution in step S106 forms the stressed dielectric layer that comprises natural stress on said Semiconductor substrate.
Execution in step S108 carries out annealing in process to said Semiconductor substrate, leaks the stressed zone in the formation source, amorphous area position of sacrificial gate both sides.
Said step can form the channel region with certain stress after carrying out in Semiconductor substrate.The stress that said channel region is introduced can effectively promote carrier mobility, and then the driving force of enhance device.
For making MOS transistor, after above-mentioned steps was implemented, MOS transistor manufacture method of the present invention also comprised:
The said stressed dielectric layer of anisotropic etching forms sidewall in the sacrificial gate both sides;
In the Semiconductor substrate of sacrificial gate both sides, form shallow, dark doped region;
Adopt grid replacement technology between said sidewall, to form the gate dielectric layer of metal gates and high-k dielectric material formation.。
Below in conjunction with the specific embodiment of making MOS transistor, the formation method of MOS transistor of the present invention source being leaked the stressed zone further specifies.
Referring to Fig. 2 to Fig. 9, show and adopt MOS transistor of the present invention source to leak the cross-sectional view that formation method in stressed zone forms an embodiment of CMOS transistor.
As shown in Figure 2, Semiconductor substrate 201 is provided, wherein, said Semiconductor substrate 201 has P type doped region 202 and N type doped region 203, and said N type doped region 203 is used to form the PMOS transistor, and said P type doped region 202 is used to form nmos pass transistor.Said P type doped region 202 is isolated through channel separating zone 204 with N type doped region 203.In specific embodiment, said Semiconductor substrate 201 is not limited to the elemental silicon substrate, can also adopt germanium, germanium silicon, silicon-on-insulator or other semi-conducting materials.
Then, on said Semiconductor substrate 201, form pseudo-gate dielectric layer 205, sacrificial gate 206 and hard mask layer 220 successively.Said sacrificial gate 206 adopts polysilicon, adopts similar MOS transistor production method for polysilicon grid to form said sacrificial gate 206.Said hard mask layer 220 is as etch polysilicon and form the mask of sacrificial gate 206.According to the difference of specific embodiment, said pseudo-gate dielectric layer 205 can adopt silica or high-k dielectric material to form.
As shown in Figure 3, form photoresist layer on Semiconductor substrate 201 surfaces of N type doped region 203.Afterwards, be mask with said photoresist layer, said Semiconductor substrate 201 is carried out the amorphous area ion inject, in the Semiconductor substrate 201 of sacrificial gate 206 both sides of P type doped region 202, form amorphous area 208.
In said amorphous area ion implantation process, inject ion and can clash into the atom of Semiconductor substrate 201, make said atom depart from intrinsic lattice position, be non crystalline structure thereby the crystalline texture of Semiconductor substrate 201 near surfaces is destroyed.In addition, in the said decrystallized while of Semiconductor substrate 201 parts, it is also decrystallized with the polysilicon of sacrificial gate 206 simultaneously to inject ion.
In specific embodiment, said amorphous area ion injects and adopts the semi-conducting material of atomic number greater than silicon, or heavy inert gas ion, perhaps other heavy ions such as argon, krypton, xenon; Implantation dosage is 1E+14cm
-2To 5E+15cm
-2, after the injection, the degree of depth of amorphous area 208 is 5 nanometer to 30 nanometers.
As shown in Figure 4, remove the photoresist layer on the N type doped region 203.Then, on said Semiconductor substrate 201, form the stressed dielectric layer 209 that comprises natural stress.In the present embodiment; The said stressed dielectric layer 209 that includes natural stress is the tensile stress layer; Said tensile stress can be transferred in the channel region of the nmos pass transistor on the P type doped region 202 when subsequent treatment; And the tensile stress of channel region can promote electron mobility, and then improves the driving force of nmos pass transistor.
In various embodiment, said amorphous area can also be formed in the N type doped region 203, in this case, because the compression of channel region can promote hole mobility, and then improves the transistorized driving force of PMOS.Therefore, if need in the channel region of N type doped region 203, introduce stress, then need on Semiconductor substrate 201, form natural stress is the stressed dielectric layer of compression.And all need introduce under the situation of stress for PMOS transistor AND gate nmos pass transistor; After can in P type doped region and N type doped region, forming amorphous area; Adopt two stressed dielectric layer (Dual Stress Liner) technologies respectively on N type doped region and P type doped region respectively the corresponding stressed dielectric layer of formation introduce stress; Particularly, said pair of stressed dielectric layer technology comprises: deposition has the stressed dielectric layer of tensile stress simultaneously on N type doped region and P type doped region; Remove the stressed dielectric layer on the P type doped region with tensile stress; Said P type doped region with have on the stressed dielectric layer of tensile stress the stressed dielectric layer that deposition simultaneously has compression; Remove the stressed dielectric layer on the N type doped region with compression.
Can find out; When forming said stressed dielectric layer 209; Sacrificial gate 206 both sides do not form sidewall, and therefore, the zone of said sacrificial gate 206 both sides source-drain area to be formed still has the area of broad; It is also less relatively that formation has the difficulty of dielectric layer of homogeneous strain, and this has improved the feasibility that stressed zone formation method is leaked in MOS transistor of the present invention source greatly.This also makes the present invention be particularly suitable for the following CMOS transistor fabrication of 45 nanometers technology.
In specific embodiment, said stressed dielectric layer 209 adopts silicon nitride, silicon oxynitride, silica or other dielectric materials.For the stressed dielectric layer 209 that adopts silicon nitride; Can adopt plasma-reinforced chemical vapor deposition (PECVD) or high-density plasma (HDP) chemical vapor deposition to form; The reaction condition of said high-density plasma chemical vapor deposition is: reacting gas comprises argon gas, silane and nitrogen; The gas flow of said silane be 50 to 500 standard cubic centimeters/minute; The gas flow ratio of silane and nitrogen is 1: 1 to 5: 1, reaction pressure 10 to 100 millitorrs, 0 to 2000 watt of reaction rf bias power.
As shown in Figure 5, said Semiconductor substrate 201 is carried out annealing in process.In specific embodiment, the annealing temperature of said annealing in process is 400 degrees centigrade to 1100 degrees centigrade.In the preferred embodiment, said annealing in process adopts short annealing to handle (RTP), and the annealing time that said short annealing is handled is 10 seconds to 300 seconds.
The annealing in process of said Semiconductor substrate 201 makes the crystallization again of former amorphous area; Simultaneously; The stress of the stressed dielectric layer 209 of said former amorphous area top is released because of annealing in process, and transfers in the Semiconductor substrate of former amorphous area, has formed stressed zone 215 in former amorphous area position.Said stressed zone 215 has been equivalent to remember the stress in the stressed dielectric layer 209.Further, the stress of said stressed zone 215 directly acts on the channel region of MOS transistor, thereby has improved the mobility of charge carrier rate.
For sacrificial gate 206, its in the process of Semiconductor substrate 201 amorphisation simultaneously by decrystallized.Therefore, after annealing in process, sacrificial gate 206 has also been remembered certain stress, but because sacrificial gate 206 can be removed in subsequent treatment, therefore, the stress of memory can not influence the stress distribution of MOS transistor channel region on the said sacrificial gate 206.
Yet, for the Semiconductor substrate 201 of N type doped region 203, owing to wherein do not include amorphous area; Therefore; When annealing in process, the stress in the stressed dielectric layer 209 can not shift to Semiconductor substrate 201 basically, just can in the Semiconductor substrate 201 of N type doped region 203, not form the stressed zone yet.
As shown in Figure 6, after forming stressed zone 215, said stressed dielectric layer is carried out anisotropic etching, form sidewall 210 in sacrificial gate 206 both sides.The making of said sidewall 210 has directly utilized the stressed dielectric layer of accomplishing Stress Release.
Then, be mask with said sacrificial gate 206 and sidewall 210, P type doped region of said Semiconductor substrate 201 202 and N type doped region 203 are carried out shallow doped region ion respectively inject, in the Semiconductor substrate 201 of sacrificial gate 206 both sides, form shallow doped region 207.Afterwards, said P type doped region 202 and N type doped region 203 are proceeded heavy doping to form dark doped region 211, said shallow doped region 207 and dark doped region 211 have constituted the source-drain area of MOS transistor jointly.
As shown in Figure 7, after source-drain area forms, continue on said Semiconductor substrate 201, to form dielectric protection layer 212, said dielectric protection layer 212 surpasses the upper surface of hard mask layer at least.Afterwards, the said dielectric protection layer 212 of planarization also removes said hard mask layer, until exposing the sacrificial gate surface.
Then, remove said sacrificial gate, and the pseudo-gate dielectric layer of said sacrifice 206 belows, forming gate openings 221 in former sacrificial gate position, said gate openings 221 makes the surface portion of Semiconductor substrate 201 expose.
As shown in Figure 8, on said dielectric protection layer 212 and Semiconductor substrate 201, form gate dielectric layer 222 and workfunction layers 223, said gate dielectric layer 222 and workfunction layers 223 cover gate openings 221.Then, continue on said workfunction layers 223, to form grid conducting material, said grid conducting material fills up gate openings 221.Afterwards; Said Semiconductor substrate 201 is carried out planarization; Remove grid conducting material, workfunction layers and gate dielectric layer on the dielectric protection layer 212; Only keep gate dielectric layer and grid conducting material in the gate openings 221, grid conducting material in the said gate openings 221 and workfunction layers have promptly constituted the grid 224 of MOS transistor.Said grid 224 replaces former pseudo-gate dielectric layer and sacrificial gate respectively with gate dielectric layer 222, has promptly constituted replacement gate (Replacement Gate).
In the present embodiment, said gate dielectric layer 222 adopts HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, high-k dielectric material such as LaAlO; Said workfunction layers 223 adopts metal materials such as TiN, TiAlN, TaN, TaAlN, TaC; Said grid 224 adopts metal materials such as Ti, Co, Ni, Al, W.
As shown in Figure 9, after said grid 224 formed, partial etching dielectric protection layer 212 formed the opening that is positioned at source-drain area.Filled conductive material in said opening forms contact hole 226.Said contact hole 226 is drawn source region, the drain region of MOS transistor respectively.
So far, adopt the MOS transistor of the inventive method to complete.
In the above-described embodiments, adopt the back grid technique to form the method for the MOS transistor with high k gate dielectric layer, it is particularly suitable for making the MOS transistor under 45 nanometers and the following characteristic size.
Compared with prior art, MOS transistor source leakage stressed zone formation method of the present invention and MOS transistor manufacture method are introduced stress through on the zone of grid both sides source-drain area to be formed, directly forming the stressed dielectric layer that comprises natural stress.Because said stressed dielectric layer is formed on the Semiconductor substrate and grid that does not comprise sidewall, the grid both sides still have the area of broad, and this greatly reduces the formation difficulty of stress film; Simultaneously; In the manufacturing process of MOS transistor; Said stressor layers through the decrystallized in advance Semiconductor substrate in source-drain area position with stress transfer in source-drain area; And then influencing the stress characteristics of channel region, the STRESS VARIATION of said channel region has improved carrier mobility, and then has strengthened the driving force of MOS transistor.
Should be appreciated that example here and embodiment only are exemplary, those skilled in the art can make various modifications and corrigendum under the situation of the spirit and scope of the present invention that do not deviate from the application and accompanying claims and limited.
Claims (12)
1. the formation method that the stressed zone is leaked in the MOS transistor source is characterized in that, comprises
Semiconductor substrate is provided, on said Semiconductor substrate, forms sacrificial gate;
Said Semiconductor substrate is carried out ion inject, in the Semiconductor substrate of sacrificial gate both sides, form amorphous area;
On said Semiconductor substrate, form the stressed dielectric layer that comprises natural stress;
Said Semiconductor substrate is carried out annealing in process, leak the stressed zone in the formation source, amorphous area position of sacrificial gate both sides.
2. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 1 source, it is characterized in that,
The ion injection employing germanium of said formation amorphous area or atomic number are greater than the inert gas ion of silicon.
3. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 1 source, it is characterized in that,
The implantation dosage that the ion of said formation amorphous area injects is 1E14cm
-2To 5E15cm
-2, energy be 5KeV to 500KeV, after the injection, the degree of depth of amorphous area is 5 nanometer to 30 nanometers.
4. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 1 source, it is characterized in that,
Said stressed dielectric layer adopts silicon nitride, silicon oxynitride or silica.
5. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 4 source, it is characterized in that,
Said stressed dielectric layer adopts silicon nitride; Adopt high-density plasma chemical vapor deposition to form said stressed dielectric layer; Reaction condition is: reacting gas comprises argon gas, silane and nitrogen, the gas flow of said silane be 50 to 500 standard cubic centimeters/minute, the gas flow ratio of silane and nitrogen is 1: 1 to 5: 1; Reaction pressure 10 to 100 millitorrs, 0 to 2000 watt of reaction rf bias power.
6. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 1 source, it is characterized in that,
The said stressed dielectric layer that comprises natural stress that on said Semiconductor substrate, forms comprises:
Said amorphous area is arranged in the Semiconductor substrate that forms nmos pass transistor, and said stressed dielectric layer natural stress is a tensile stress;
Said amorphous area is arranged in and forms the transistorized Semiconductor substrate of PMOS, and said stressed dielectric layer natural stress is a compression.
7. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 6 source, it is characterized in that, adopts two stressed dielectric layer technologies to introduce stress forming on nmos pass transistor and the transistorized Semiconductor substrate of PMOS the corresponding stressed dielectric layer of formation respectively.
8. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 1 source, it is characterized in that,
The annealing temperature of said annealing in process is 400 degrees centigrade to 1100 degrees centigrade.
9. the formation method of stressed zone is leaked in MOS transistor as claimed in claim 8 source, it is characterized in that,
Said annealing in process adopts short annealing to handle, and the processing time is 5 seconds to 300 seconds.
10. an application rights requires 1 described source to leak the method that formation method in stressed zone is made MOS transistor, it is characterized in that,
After the stressed zone was leaked in the formation source, the said stressed dielectric layer of anisotropic etching formed sidewall in the sacrificial gate both sides;
After forming sidewall, in the Semiconductor substrate of sacrificial gate both sides, form shallow, dark doped region;
Adopt grid replacement technology between said sidewall, to form the gate dielectric layer of metal gates and high-k dielectric material formation.
11. MOS transistor manufacture method as claimed in claim 10 is characterized in that, said metal gates adopts Ti, Co, Ni, Al or W.
12. MOS transistor manufacture method as claimed in claim 10 is characterized in that, said high-k dielectric material adopts HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Or LaAlO.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013143035A1 (en) * | 2012-03-30 | 2013-10-03 | 中国科学院微电子研究所 | Mos device approaching source/drain region to channel region and manufacturing method therefor |
| WO2013189096A1 (en) * | 2012-06-20 | 2013-12-27 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US8841190B2 (en) | 2012-03-30 | 2014-09-23 | The Institute of Microelectronics Chinese Academy of Science | MOS device for making the source/drain region closer to the channel region and method of manufacturing the same |
| CN114267724A (en) * | 2022-03-01 | 2022-04-01 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN114899150A (en) * | 2022-04-24 | 2022-08-12 | 上海华力集成电路制造有限公司 | Manufacturing method for improving mobility of channel carrier of semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040253791A1 (en) * | 2003-06-16 | 2004-12-16 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device having MOS transistor with strained channel |
| US20060163671A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Silicide cap structure and process for reduced stress and improved gate sheet resistance |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| CN101266949A (en) * | 2007-03-16 | 2008-09-17 | 联华电子股份有限公司 | Method for making strain silicon CMOS transistor |
| US20090152626A1 (en) * | 2007-12-18 | 2009-06-18 | Texas Instruments Incorporated | Super Halo Formation Using a Reverse Flow for Halo Implants |
| CN101546770A (en) * | 2008-03-28 | 2009-09-30 | 株式会社东芝 | Semiconductor device and manufacturing method of same |
| CN101641780A (en) * | 2007-03-20 | 2010-02-03 | 索尼株式会社 | Semiconductor device and method for manufacturing the same |
-
2010
- 2010-08-16 CN CN2010102553862A patent/CN102376575A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040253791A1 (en) * | 2003-06-16 | 2004-12-16 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device having MOS transistor with strained channel |
| US20060163671A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Silicide cap structure and process for reduced stress and improved gate sheet resistance |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| CN101266949A (en) * | 2007-03-16 | 2008-09-17 | 联华电子股份有限公司 | Method for making strain silicon CMOS transistor |
| CN101641780A (en) * | 2007-03-20 | 2010-02-03 | 索尼株式会社 | Semiconductor device and method for manufacturing the same |
| US20090152626A1 (en) * | 2007-12-18 | 2009-06-18 | Texas Instruments Incorporated | Super Halo Formation Using a Reverse Flow for Halo Implants |
| CN101546770A (en) * | 2008-03-28 | 2009-09-30 | 株式会社东芝 | Semiconductor device and manufacturing method of same |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013143035A1 (en) * | 2012-03-30 | 2013-10-03 | 中国科学院微电子研究所 | Mos device approaching source/drain region to channel region and manufacturing method therefor |
| US8841190B2 (en) | 2012-03-30 | 2014-09-23 | The Institute of Microelectronics Chinese Academy of Science | MOS device for making the source/drain region closer to the channel region and method of manufacturing the same |
| WO2013189096A1 (en) * | 2012-06-20 | 2013-12-27 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103515233A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| US9064954B2 (en) | 2012-06-20 | 2015-06-23 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor devices and methods for manufacturing the same |
| CN103515233B (en) * | 2012-06-20 | 2016-04-06 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN114267724A (en) * | 2022-03-01 | 2022-04-01 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN114267724B (en) * | 2022-03-01 | 2022-05-31 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN114899150A (en) * | 2022-04-24 | 2022-08-12 | 上海华力集成电路制造有限公司 | Manufacturing method for improving mobility of channel carrier of semiconductor device |
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