CN102375795B - Interface conversion device and conversion method - Google Patents
Interface conversion device and conversion method Download PDFInfo
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- CN102375795B CN102375795B CN 201010262487 CN201010262487A CN102375795B CN 102375795 B CN102375795 B CN 102375795B CN 201010262487 CN201010262487 CN 201010262487 CN 201010262487 A CN201010262487 A CN 201010262487A CN 102375795 B CN102375795 B CN 102375795B
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Abstract
The invention relates to an interface conversion device and an interface conversion method. The interface conversion device comprises a DMA (Direct Memory Access) module, an intermediate processing module, a TCM (Terminal-to-Computer Multiplexer) module, wherein the DMA module is connected with a DMA interface for receiving a DMA signal from the DMA interface or transmitting a converted DMA signal to the DMA interface; the intermediate processing module is used for converting the DMA signal received from the DMA interface into a TCM signal and converting the TCM signal received from the TCM interface into a DMA signal; and the TCM module is connected with the TCM interface for transmitting the converted TCM signal to the TCM interface or receiving the TCM signal from the TCM interface. By implementing the technical scheme of the invention, data transmission between the DMA interface and the TCM interface can be realized.
Description
Technical field
The present invention relates to interface conversion, more particularly, relate to a kind of interface switching device and conversion method that realizes the data transmission between DMA interface and TCM interface.
Background technology
Comprise DMA interface, TCM interface at numerous memory access interfaces, as shown in Figure 1, the functional unit 200 that adopts DMA interface and the storage unit 300 of employing TCM interface are because DMA communication protocol and TCM communication protocol is different, make DMA interface and TCM interface completely cut off, that is, functional unit 200 can't storage unit access 300.
The following describes the communication protocol of DMA interface and TCM interface:
One, DMA interface:
Dma_req: the request signal position, totally 1 of dma_req is effectively high.Trigger along constantly at clock, during functional unit request DMA data transmission, dma_req is drawn high; At clock, trigger along constantly, when dma_ack is high, functional unit drags down dma_req.
Dma_addr: the start address position, totally 32 of dma_addr, DMA transmits starting address signal, and functional unit, when drawing high the dma_req signal, sends the dma_addr signal.
Dma_cnt: the total byte numerical digit, totally 16 of dma_cnt, this DMA transmission needs the total bytes of transmission, and functional unit, when drawing high the dma_req signal, sends the dma_cnt signal.
Dma_step: address jump position, totally 32 of dma_step.Suppose that low 16 place values are X, high 16 place values are Y, DMA read or write after the X byte data need to current location backward redirect Y byte address continue again to read or write the X byte, so repeatedly, until read or write the dma_cnt byte.
Dma_dir: the direction signal position, totally 1 of dma_dir, mean the direction that DMA transmits.0 means that data spread out of from functional unit, and functional unit writes out data; 1 expression data are imported functional unit into, i.e. the functional unit reading data.
Dma_ack: the response signal position, totally 1 of dma_ack, the DMA request response signal, the request of 1 presentation function unit has obtained response; 0 means not response.
Dma_udata: uploading data position, totally 16 or 32 of dma_udata, the data that functional unit writes out by DMA.
Dma_urd: upload signal bits, totally 1 of dma_urd.If present clock triggers edge constantly, dma_urd is high, at next clock, triggers along moment functional unit corresponding dma_udata need be provided.
Dma_ddata: downloading data position, totally 16 or 32 of dma_ddata, the data that functional unit reads in by DMA.
Dma_dwr: download signal position, totally 1 of dma_dwr.If it is high that present clock triggers along moment dma_dwr, at the current time functional unit, can read corresponding dma_ddata.
Two, TCM interface signal:
DRADDR: address bit, totally 18 of DRADDR, mean the address read and write data, take word as unit, i.e. first character in 0 corresponding stored unit, second word in 1 corresponding stored unit.
DRCS: the chip selection signal position, totally 1 of DRCS, the chip selection signal of storage unit is effectively high.
Totally 18 of DRDMAADDR:DRDMAADDR, do not used usually, is made as 0.
Totally 1 of DRDMAEN:DRDMAEN, do not used usually, is made as 0.
Totally 1 of DRDMACS:DRDMACS, do not used usually, is made as 0.
DRIDLE: the status signal position, totally 1 of DRIDLE, 0 means that data TCM reads and writes data; 1 means the data TCM free time.
DRnRW: read-write marking signal position, totally 1 of DRnRW.DRnRW is 0 expression read memory cell; DRnRW is that storage unit is write in 1 expression.
DRRD: read data bit, totally 32 of DRRD.
Totally 1 of DRSEQ:DRSEQ, 1 means that data TCM address is continuous, 0 means that address may not be continuous.
Totally 4 of DRSIZE:DRSIZE, the size of expression data TCM.The DRSIZE minimum is 3, is 11 to the maximum.DRSIZE is that 3 expression data TCM are the 4K byte-sized, and 4 mean the 8K byte-sized, and 5 mean the 16K byte-sized, the like.The storage unit minimum is the 4K byte, is the 1M byte to the maximum.
Totally 1 of DRWAIT:DRWAIT, data TCM waiting signal, 1 representative data TCM is current can not respond read-write requests, and 0 represents and can respond.
DRWD: write data bits, totally 32 of DRWD.
DRWBL: byte is selected signal bits, totally 4 of DRWBL, and byte when data TCM writes data is selected signal, effectively high.DRWBL from high to low 4 mean respectively DRWD from high to low writing of 4 bytes enable.
Summary of the invention
The technical problem to be solved in the present invention is, the above-mentioned defect that can't realize data transmission between DMA interface and TCM interface for prior art, provide a kind of interface switching device, can realize the data transmission between DMA interface and TCM interface.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of interface switching device, for realizing the data transmission between DMA interface and TCM interface, comprising:
Dma module, be connected with DMA interface, for receiving the DMA signal from DMA interface, or sends the DMA signal after changing to DMA interface;
Intermediate process module, be converted to the TCM signal for the signal of the DMA from DMA interface by received, and the received signal of the TCM from the TCM interface is converted to the DMA signal;
The TCM module, be connected with described TCM interface, for to the TCM interface, sending the TCM signal after changing, or receives the TCM signal from the TCM interface.
In interface switching device of the present invention,
Described dma module comprises:
The start address computing unit, be connected with the start address position of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, what start address was updated to the start address the start address position of DMA interface exported hangs down 20;
The total bytes computing unit, be connected with the total byte numerical digit of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit, for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, be updated to 0 by current byte number; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if second upload signal or the second download signal is 1, current byte number is added to 4; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if first upload signal or the first download signal is 1, current byte number is added to 4;
The response signal computing unit, be connected with the response signal position of DMA interface, for triggering along constantly at clock, if request signal is 1, response signal is updated to 1; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, response signal is updated to 0; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second upload signal or the second download signal is 1, and current byte number equals total bytes, response signal is updated to 0;
Upload signature computation unit, be connected with the signal bits of uploading of DMA interface, while for the data bit width when DMA interface, being 16, uploading signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
The download signal computing unit, be connected with the download signal position of DMA interface, and while for the data bit width when DMA interface, being 16, download signal equals the value that the second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface is 32, download signal equals the second download signal;
The downloading data computing unit, with the downloading data position of DMA interface, be connected, while for the data bit width when DMA interface, being 16, if the second download signal is 1, downloading data equals read data bit low 16 of TCM interface, otherwise downloading data equals read data bit high 16 of TCM interface; When the data bit width of DMA interface is 32, downloading data equals the read data bit of TCM interface;
Described intermediate process module comprises:
First uploads signature computation unit, and for triggering at clock along constantly, if request signal and response signal are all 1, and direction signal is 0, and first to upload signal update be 1; At clock, trigger along constantly, if first to upload signal be 1, first to upload signal update be 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1;
Second uploads signature computation unit, and for triggering at clock along constantly, if first to upload signal be 1, second to upload signal update be 1; At clock, trigger along constantly, if second to upload signal be 1, second to upload signal update be 0;
The 3rd uploads signature computation unit, and for triggering at clock along constantly, if second to upload signal be 1, the 3rd to upload signal update be 1; At clock, trigger along constantly, if the 3rd to upload signal be 1, the 3rd to upload signal update be 0;
The first download signal computing unit, for triggering at clock along constantly, if request signal, response signal, direction signal are all 1, the first download signal is updated to 1; At clock, trigger along constantly, if the first download signal is 1, the first download signal is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if the second download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1;
The second download signal computing unit, for triggering along constantly at clock, if the first download signal is 1, the second download signal is updated to 1; At clock, trigger along constantly, if the second download signal is 1, the second download signal is updated to 0;
The 3rd download signal computing unit, for triggering along constantly at clock, if the second download signal is 1, the 3rd download signal is updated to 1; At clock, trigger along constantly, if the 3rd download signal is 1, the 3rd download signal is updated to 0;
The TCM module comprises:
Read-write marking signal computing unit, be connected with the read-write marker bit of TCM interface, and while for the data bit width when DMA interface, being 16, the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface is 32, the read-write marking signal equals second and uploads signal;
Address calculation, be connected with the address bit of TCM interface, for making current address, equals start address position and current byte number sum, and, when the read-write marking signal is 1, low 2 of 20 gts that address equals current address subtract 1 again; When the read-write marking signal while being 0, address equals 2 of low 20 gts of current address;
The chip selection signal computing unit, be connected with the chip selection signal position of TCM interface, and while for the data bit width when DMA interface, being 16, chip selection signal equals the 3rd and uploads the value that signal, the first download signal, the second download signal carry out exclusive disjunction; When the data bit width of DMA interface is 32, chip selection signal equals second and uploads the value that signal, the first download signal carry out exclusive disjunction;
Byte is selected signature computation unit, with the byte of TCM interface, selects signal bits to be connected, and byte selects 4 of signal to be equal to the read-write marking signal;
Write the data computing unit, with the write data bits of TCM interface, be connected, for when the data bit width of DMA interface is 16, write high 16 uploading datas that equal DMA interface of data, at clock, trigger along constantly, if second to upload signal be 1, write low 16 uploading datas that are updated to DMA interface of data, other the time inscribe data low 16 place values remain unchanged; When the data bit width of DMA interface is 32, write the uploading data that data equal DMA interface.
In interface switching device of the present invention, trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, the first download signal, the second download signal, the 3rd download signal and all be reset to 0.
The present invention also constructs a kind of interface conversion method, for realizing the data transmission between DMA interface and TCM interface, it is characterized in that, comprising:
When from DMA interface to the TCM interface, transmitting data, carry out steps A 1 to A3:
A1. receive the DMA signal from DMA interface;
A2. the received signal of the DMA from DMA interface is converted to the TCM signal;
A3. send the TCM signal after changing to the TCM interface;
When from the TCM interface to DMA interface, transmitting data, carry out step B1 to B3:
B1. receive the TCM signal from the TCM interface;
B2. the received signal of the TCM from the TCM interface is converted to the DMA signal;
B3. send the DMA signal after changing to DMA interface.
In interface conversion method of the present invention, carry out following steps simultaneously:
Calculate start address: at clock, trigger along constantly, if request signal and response signal are 1 simultaneously, what start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Calculate total bytes: at clock, trigger along constantly, if request signal and response signal are 1 simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Calculate current byte number: trigger along constantly at clock, if request signal and response signal are 1 simultaneously, current byte number is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if second upload signal or the second download signal is 1, current byte number is added to 4; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if first upload signal or the first download signal is 1, current byte number is added to 4;
Calculated response signal: trigger along constantly at clock, if request signal is 1, response signal is updated to 1; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, response signal is updated to 0; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second upload signal or the second download signal is 1, and current byte number equals total bytes, response signal is updated to 0;
Signal is uploaded in calculating: when the data bit width of DMA interface is 16, uploads signal and be and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
Calculate download signal: when the data bit width of DMA interface is 16, download signal is to equal the value that the second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface is 32, download signal equals the second download signal;
Calculate downloading data: when the data bit width of DMA interface is 16, if the second download signal is 1, downloading data equals low 16 of read data bit of TCM interface, otherwise downloading data equals read data bit high 16 of TCM interface; When the data bit width of DMA interface is 32, downloading data equals the read data bit of TCM interface;
Calculate first and upload signal: at clock, trigger along constantly, if request signal and response signal are all 1, and direction signal is 0, and first to upload signal update be 1; At clock, trigger along constantly, if first to upload signal be 1, first to upload signal update be 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1;
Calculate second and upload signal: at clock, trigger along constantly, if first to upload signal be 1, second to upload signal update be 1; At clock, trigger along constantly, if second to upload signal be 1, second to upload signal update be 0;
Calculate the 3rd and upload signal: at clock, trigger along constantly, if second to upload signal be 1, the 3rd to upload signal update be 1; At clock, trigger along constantly, if the 3rd to upload signal be 1, the 3rd to upload signal update be 0;
Calculate the first download signal: at clock, trigger along constantly, if request signal, response signal, direction signal are all 1, the first download signal is updated to 1; At clock, trigger along constantly, if the first download signal is 1, the first download signal is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if the second download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1;
Calculate the second download signal: at clock, trigger along constantly, if the first download signal is 1, the second download signal is updated to 1; At clock, trigger along constantly, if the second download signal is 1, the second download signal is updated to 0;
Calculate the 3rd download signal: at clock, trigger along constantly, if the second download signal is 1, the 3rd download signal is updated to 1; At clock, trigger along constantly, if the 3rd download signal is 1, the 3rd download signal is updated to 0;
Calculate the read-write marking signal: when the data bit width of DMA interface is 16, the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface is 32, the read-write marking signal equals second and uploads signal;
Calculated address: make current address equal start address position and current byte number sum,, when the read-write marking signal is 1, low 2 of 20 gts that address equals current address subtract 1 again; When the read-write marking signal while being 0, address equals 2 of low 20 gts of current address;
Calculate chip selection signal: when the data bit width of DMA interface is 16, chip selection signal equals the 3rd and uploads the value that signal, the first download signal, the second download signal carry out exclusive disjunction; When the data bit width of DMA interface is 16, chip selection signal equals second and uploads the value that signal, the first download signal carry out exclusive disjunction;
Calculate byte and select signal: byte selects 4 of signal to be equal to the read-write marking signal;
Data are write in calculating: when the data bit width of DMA interface is 16, write high 16 uploading datas that equal DMA interface of data, at clock, trigger along constantly, if second to upload signal be 1, write low 16 uploading datas that are updated to DMA interface of data, other the time inscribe data low 16 place values remain unchanged; When the data bit width of DMA interface is 32, write the uploading data that data equal DMA interface.
In interface conversion method of the present invention, trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, the first download signal, the second download signal, the 3rd download signal and all be reset to 0.
Implement technical scheme of the present invention, owing to being converted into from the DMA signal of DMA interface the TCM signal and will being converted to the DMA signal from the TCM signal of TCM interface, so can realize the data transmission between DMA interface and TCM interface, and then make, can access the storage unit with the TCM interface with the functional unit of DMA interface.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is with the functional unit of DMA interface and storage unit with the TCM interface in prior art;
Fig. 2 is the building-block of logic of interface switching device embodiment mono-of the present invention;
Fig. 3 is the building-block of logic of interface switching device embodiment bis-of the present invention;
Fig. 4 A transmits the process flow diagram of data embodiment mono-from DMA interface to the TCM interface in interface conversion method of the present invention;
Fig. 4 B transmits the process flow diagram of data embodiment mono-from the TCM interface to DMA interface in interface conversion method of the present invention;
Fig. 5 A is the sequential chart of the present invention's each signal while from DMA interface to the TCM interface, transmitting 32 bit data;
Fig. 5 B is the sequential chart of the present invention's each signal while from the TCM interface to DMA interface, transmitting 32 bit data;
Fig. 5 C is the sequential chart of the present invention's each signal while from DMA interface to the TCM interface, transmitting 16 bit data;
Fig. 5 D is the present invention while from the TCM interface to DMA interface, transmitting 16 bit data, the sequential chart of each signal.
Embodiment
As shown in Figure 2, in the building-block of logic of interface switching device embodiment mono-of the present invention, this interface switching device is for realizing the data transmission between DMA interface and TCM interface, and this interface switching device comprises dma module 110, intermediate process module 120 and TCM module 130.Wherein, dma module 110 is connected with DMA interface (Fig. 2 is not shown), for receiving the DMA signal from DMA interface, or sends the DMA signal after changing to DMA interface; Intermediate process module 120 is converted to the TCM signal for the signal of the DMA from DMA interface by received, and received is converted to the DMA signal from TCM interface TCM signal; TCM module 130 is connected with described TCM interface (Fig. 2 is not shown), for to the TCM interface, sending the TCM signal after changing, or receives the TCM signal from the TCM interface.Implement this technical scheme, owing to being converted into the TCM signal from the DMA signal of DMA interface, and will be converted to the DMA signal from the TCM signal of TCM interface, so can realize the data transmission between DMA interface and TCM interface, and then make, can access the storage unit with the TCM interface with the functional unit of DMA interface.
As shown in Figure 3, in the building-block of logic of interface switching device embodiment bis-of the present invention, this interface switching device comprises dma module 110, intermediate process module 120 and TCM module 130.Wherein, dma module 110 comprises start address computing unit 111, total bytes computing unit 112, current byte number computing unit 113, response signal computing unit 114, uploads signature computation unit 115, download signal computing unit 116 and downloading data computing unit 117; Intermediate process module 120 comprises that first uploads signature computation unit 121, second and upload signature computation unit 122, the 3rd and upload signature computation unit 123, the first download signal computing unit 124, the second download signal computing unit 125 and the 3rd download signal computing unit 126; TCM module 130 comprises read-write marking signal computing unit 131, address calculation 132, chip selection signal computing unit 133, byte selection signature computation unit 134 and writes data computing unit 135.Below illustrate unit:
Start address computing unit 111, be connected with the start address position of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, what start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Total bytes computing unit 112, be connected with the total byte numerical digit of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit 113, for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, be updated to 0 by current byte number; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if second upload signal or the second download signal is 1, current byte number is added to 4; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if first upload signal or the first download signal is 1, current byte number is added to 4;
Response signal computing unit 114, be connected with the response signal position of DMA interface, for triggering along constantly at clock, if request signal is 1, response signal is updated to 1; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, response signal is updated to 0; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second upload signal or the second download signal is 1, and current byte number equals total bytes, response signal is updated to 0;
Upload signature computation unit 115, be connected with the signal bits of uploading of DMA interface, while for the data bit width when DMA interface, being 16, uploading signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
Download signal computing unit 116, be connected with the download signal position of DMA interface, and while for the data bit width when DMA interface, being 16, download signal equals the value that the second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface is 32, download signal equals the second download signal;
Downloading data computing unit 117, with the downloading data position of DMA interface, be connected, while for the data bit width when DMA interface, being 16, if the second download signal is 1, downloading data equals read data bit low 16 of TCM interface, otherwise downloading data equals read data bit high 16 of TCM interface; When the data bit width of DMA interface is 32, downloading data equals the read data bit of TCM interface;
First uploads signature computation unit 121, and for triggering at clock along constantly, if request signal and response signal are all 1, and direction signal is 0, and first to upload signal update be 1; At clock, trigger along constantly, if first to upload signal be 1, first to upload signal update be 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1;
Second uploads signature computation unit 122, and for triggering at clock along constantly, if first to upload signal be 1, second to upload signal update be 1; At clock, trigger along constantly, if second to upload signal be 1, second to upload signal update be 0;
The 3rd uploads signature computation unit 123, and for triggering at clock along constantly, if second to upload signal be 1, the 3rd to upload signal update be 1; At clock, trigger along constantly, if the 3rd to upload signal be 1, the 3rd to upload signal update be 0;
The first download signal computing unit 124, for triggering at clock along constantly, if request signal, response signal, direction signal are all 1, the first download signal is updated to 1; At clock, trigger along constantly, if the first download signal is 1, the first download signal is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if the second download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1;
The second download signal computing unit 125, for triggering along constantly at clock, if the first download signal is 1, the second download signal is updated to 1; At clock, trigger along constantly, if the second download signal is 1, the second download signal is updated to 0;
The 3rd download signal computing unit 126, for triggering along constantly at clock, if the second download signal is 1, the 3rd download signal is updated to 1; At clock, trigger along constantly, if the 3rd download signal is 1, the 3rd download signal is updated to 0;
Read-write marking signal computing unit 131, be connected with the read-write marker bit of TCM interface, and while for the data bit width when DMA interface, being 16, the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface is 32, the read-write marking signal equals second and uploads signal;
Chip selection signal computing unit 133, be connected with the chip selection signal position of TCM interface, and while for the data bit width when DMA interface, being 16, chip selection signal equals the 3rd and uploads the value that signal, the first download signal, the second download signal carry out exclusive disjunction; When the data bit width of DMA interface is 32, chip selection signal equals second and uploads the value that signal, the first download signal carry out exclusive disjunction;
Byte is selected signature computation unit 134, with the byte of TCM interface, selects signal bits to be connected, and byte selects 4 of signal to be equal to the read-write marking signal;
Write data computing unit 135, with the write data bits of TCM interface, be connected, for when the data bit width of DMA interface is 16, write high 16 uploading datas that equal DMA interface of data, at clock, trigger along constantly, if second to upload signal be 1, write low 16 uploading datas that are updated to DMA interface of data, other the time inscribe data low 16 place values remain unchanged; When the data bit width of DMA interface is 32, write the uploading data that data equal DMA interface.
Preferably, in each above computing unit, trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, the first download signal, the second download signal, the 3rd download signal and all be reset to 0.
Fig. 4 A and Fig. 4 B are respectively the process flow diagrams that transmits data in interface conversion method of the present invention from DMA interface to the TCM interface and transmit data embodiment mono-from the TCM interface to DMA interface, in Fig. 4 A, from DMA interface to the TCM interface, the method S100 of transmission data comprises the following steps:
S101. receive the DMA signal from DMA interface;
S102. the received signal of the DMA from DMA interface is converted to the TCM signal;
S103. send the TCM signal after changing to the TCM interface;
In Fig. 4 B, from the TCM interface to DMA interface, the method S200 of transmission data comprises the following steps:
S201. receive the TCM signal from the TCM interface;
S202. the received signal of the TCM from the TCM interface is converted to the DMA signal;
S203. send the DMA signal after changing to DMA interface.
Below illustrate interface switching device and interface conversion method and be the data transmission that how to realize DMA interface and TCM interface.At first should be noted that, for the consideration of circuit complexity, the present invention designs under the following conditions: the address jump position of DMA interface equals total byte numerical digit, i.e. dma_step=dma_cnt, also, DMA interface starts to read continuously or write the several bytes of total byte from start address; The DRDMAADDR of TCM interface, DRDMAEN, DRDMACS, DRWAIT all connects 0; DRIDLE, DRSEQ is not used, and the present invention does not discuss; DRSIZE rationally is connected according to the size of storage unit.
Fig. 5 A is the sequential chart of each signal while from DMA interface to the TCM interface, transmitting 32 bit data, in Fig. 5 A:
Rstn is reset signal, and the negative edge time trigger at t0 constantly, request signal req, response signal ack, is uploaded signal dma_urd, first and uploaded signal urd, second and upload signal urd_d1 and all be reset to 0.
Clk is clock signal, and at t1 constantly, the request signal position of DMA interface sends request signal req (high level is effective), and both transmit direction signals dir (being 0).
At t2 constantly, response signal ack starts response request signal req.
At t3 constantly, request signal req is dragged down because of the response of response signal ack; Simultaneously, because request signal req, response signal ack are 1, direction signal dir is 0, so first upload signal urd and be updated to 1.
At t4 constantly, to upload signal urd be 1 due to first, first uploads signal urd and be updated to 0, and simultaneously, second uploads signal urd_d1 is updated to 1.
And at t5 constantly, to upload signal urd_d1 be 1 due to second, second upload signal urd_d1 and be updated to 0, simultaneously, when current number of words is less than total bytes, first uploads signal urd is updated to 1.
Upload signal dma_urd and equal first and upload signal urd, to upload the sequential chart of signal urd identical for its sequential chart and first.Read-write marking signal DRnRW equals second and uploads signal urd_d1, and to upload the sequential chart of signal urd_d1 identical for its sequential chart and second.Chip selection signal DRCS equals second and uploads signal urd_d1, and to upload the sequential chart of signal urd_d1 identical for its sequential chart and second.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.
The following describes the calculating of address of transmission data: at t3 constantly, request signal req and response signal ack are 1 simultaneously, and start address is updated to low 20 of start address that the start address position of DMA interface sends; Simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface sends, and current byte number is updated to 0.At t4 constantly, to upload signal urd be 1 due to first, so, current byte number is updated to 4, current address is start address and current byte number (the t4 moment, current byte number is updated to 4) sum, owing to aliging with word in the address of TCM interface, so calculated current address is moved to right to 2, calculating due to current address is at t4 constantly again, and data transmission is at t5 constantly, , first carry out the address renewal and carried out again data transmission, so, also the current address after moving to right should be subtracted to 1 again, the value of gained is the corresponding address D RADDR of transmission data.Know through top can be calculated, at t5 constantly, 32 bit data can be transferred to the write data bits DRWD of TCM interface from the uploading data position dma_udata of DMA interface.The transmission of 32 bit data (4 bytes) below only has been described, according to the method described above, transmit one by one each 32 bit data, until a total bytes data all transfer, as, at tn constantly, second to upload signal urd_d1 be 1, and current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
Fig. 5 B is the sequential chart of each signal while from the TCM interface to DMA interface, transmitting 32 bit data, and in Fig. 5 B, reset signal rstn, request signal req are identical with the Computing Principle of reset signal rstn, request signal req in Fig. 5 A; In addition, at t1 constantly, the both transmit direction signals dir of direction signal position institute of DMA interface is 1, now, the Computing Principle of response signal ack, the first download signal dwr, the second download signal dwr_d1 and response signal ack, first in Fig. 5 A upload signal urd, second to upload the Computing Principle of signal urd_d1 identical, at this, do not do and repeat.Download signal dma_dwr equals the second download signal dwr_d1, and its sequential chart is identical with the sequential chart of the second download signal dwr_d1.Read-write marking signal DRnRW equals second and uploads signal urd_d1 (because of when the downloading data, do not use second and upload signal urd_d1, and second to upload signal urd_d1 be 0 when resetting, so read-write marking signal DRnRW is also 0, not shown).Chip selection signal DRCS equals the first download signal dwr, and its sequential chart is identical with the sequential chart of the first download signal dwr.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.Address computation in the calculating of address and Fig. 5 A is roughly the same, be also: first by start address and current byte number (the t4 moment, current byte number is updated to 4) addition obtains ，Zai Jiang current address, current address and moves to right 2, and the value of gained is the corresponding address D RADDR of data transmission.Compare the address computation in Fig. 5 A, without being subtracted 1 calculating, because of when the downloading data, read-write marking signal DRnRW is 0 again.Through top can be calculated, know, at t4 constantly, chip selection signal DRCS is 1, and this interface switching device is read 32 bit data from the read data bit DRRD of TCM interface, at t5 constantly, 32 read bit data is transferred to the downloading data position dma_ddata of DMA interface.The transmission of 32 bit data (4 bytes) below only has been described, according to the method described above, transmit one by one each 32 bit data, until a total bytes data all transfer, as, at tn constantly, the second download signal dwr_d1 is 1, and current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
Fig. 5 C is the sequential chart of each signal while from DMA interface to the TCM interface, transmitting 16 bit data, in Fig. 5 C, reset signal rstn, request signal req, direction signal dir, response signal ack are identical with the Computing Principle of reset signal rstn, request signal req in Fig. 5 A figure, direction signal dir, response signal ack, at this, do not do and repeat.At t3 constantly, request signal req, response signal ack are 1, and direction signal dir is 0, first upload signal urd and are updated to 1.At t4 constantly, to upload signal urd be 1 due to first, second uploads signal urd_d1 and be updated to 1.At t5 constantly, to upload signal urd_d1 be 1 due to second, the 3rd upload signal urd_d2 and be updated to 1, simultaneously, if t6 constantly current byte number be less than total bytes, first upload signal urd and be updated to 1.Uploading signal dwr_urd equals first and uploads signal urd and second and upload the value that signal urd_d1 carries out the exclusive disjunction gained.Read-write marking signal DRnRW equals the 3rd and uploads signal urd_d2.Chip selection signal DRCS equals the 3rd and uploads signal urd_d2.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.The following describes the calculating of the address of transmission data: at t3 constantly, request signal req and response signal ack are 1 simultaneously, start address is updated to low 20 of start address that the start address position of DMA interface sends, simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface sends, and current byte number is updated to 0.At t5 constantly, to upload signal urd_d1 be 1 due to second, so current byte number is updated to 4.Current address is start address and current byte number (the t5 moment, current byte number is updated to 4) sum, then calculated current address is moved to right to 2, again because read-write marking signal DRnRW is 1, current address so will move to right after 2 subtracts 1 again, and the value of gained is the transmission corresponding address of data.In addition, at t5 constantly, because the second low 16 of uploading write data bits DRWD that signal urd_d1 is 1, TCM interface are updated to 16 transmitted bit data.At t6 constantly, high 16 of the write data bits DRWD that chip selection signal DRCS is 1, TCM interface equal 16 bit data that uploading data position dma_udata transmits.The transmitting procedure of one 32 (two 16) data below only has been described, according to the method described above, has transmitted one by one each 16 bit data, until a total bytes data all transfer.As, at tn constantly, the 3rd to upload signal urd_d2 be 1, and current byte number equals total bytes, response signal ack is updated to 0, the end data transmission.
Fig. 5 D is the sequential chart of each signal while from the TCM interface to DMA interface, transmitting 16 bit data, and in Fig. 5 D, reset signal rstn, request signal req are identical with the Computing Principle of reset signal rstn, request signal req in Fig. 5 C figure; In addition, at t1 constantly, DMA interface is 1 to interface switching device both transmit direction signals dir, now, the Computing Principle of response signal ack, the first download signal dwr, the second download signal dwr_d1, the 3rd download signal dwr_d2 and the response signal ack, first in Fig. 5 C upload signal urd, second and upload signal urd_d1, the 3rd to upload the Computing Principle of signal urd_d2 identical, at this, do not do and repeat.Download signal dma_dwr equals the value that the second download signal dwr_d1 and the 3rd download signal dwr_d2 carry out the exclusive disjunction gained.Read-write marking signal DRnRW equals the 3rd and uploads signal urd_d2 (because of when the downloading data, do not use the 3rd and upload signal urd_d2, and the 3rd to upload signal urd_d2 being 0 when resetting, is also 0 so read and write marking signal DRnRW).Chip selection signal DRCS equals the value that the first download signal dwr and the second download signal dwr_d1 carry out the exclusive disjunction gained.4 of byte selection signal DRWBL are all identical with read-write marking signal DRnRW.The following describes the calculating of the address of transmission data: at t 3 constantly, request signal req and response signal ack are 1 simultaneously, start address is updated to low 20 of start address that the start address position of DMA interface sends, simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface sends, and current byte number is updated to 0.At t5 constantly, because the second download signal dwr_d1 is 1, so current byte number is updated to 4.Current address is start address and current byte number (constantly, current byte number is updated to 4 to t5) sum, and then, because the read-write marking signal is 0, so calculated current address is moved to right to 2, the value of gained is the transmission corresponding address of data.So, at t5 constantly, interface switching device is low 16 downloading data position dma_ddata that are transferred to DMA interface of the read data bit DRRD of TCM interface, then at t6 constantly by high 16 downloading data position dma_ddata that are transferred to DMA interface of the read data bit DRRD of TCM interface.The transmission of two 16 bit data (4 bytes) below only has been described, according to the method described above, transmit one by one the data of every 4 bytes, until a total bytes data all transfer, as, at tn constantly, the 3rd download signal dwr_d2 is 1, and current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in claim scope of the present invention.
Claims (4)
1. an interface switching device, for realizing the data transmission between DMA interface and TCM interface, is characterized in that, comprising:
Dma module, be connected with DMA interface, for receiving the DMA signal from DMA interface, or sends the DMA signal after changing to DMA interface;
Intermediate process module, be converted to the TCM signal for the signal of the DMA from DMA interface by received, and the received signal of the TCM from the TCM interface is converted to the DMA signal;
The TCM module, be connected with described TCM interface, for to the TCM interface, sending the TCM signal after changing, or receives the TCM signal from the TCM interface;
Described dma module comprises:
The start address computing unit, be connected with the start address position of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, what start address was updated to the start address the start address position of DMA interface exported hangs down 20;
The total bytes computing unit, be connected with the total byte numerical digit of DMA interface, and for triggering at clock along constantly, if request signal and response signal are 1 simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit, for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, be updated to 0 by current byte number; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if second upload signal or the second download signal is 1, current byte number is added to 4; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if first upload signal or the first download signal is 1, current byte number is added to 4;
The response signal computing unit, be connected with the response signal position of DMA interface, for triggering along constantly at clock, if request signal is 1, response signal is updated to 1; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, response signal is updated to 0; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second upload signal or the second download signal is 1, and current byte number equals total bytes, response signal is updated to 0;
Upload signature computation unit, be connected with the signal bits of uploading of DMA interface, while for the data bit width when DMA interface, being 16, uploading signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
The download signal computing unit, be connected with the download signal position of DMA interface, and while for the data bit width when DMA interface, being 16, download signal equals the value that the second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface is 32, download signal equals the second download signal;
The downloading data computing unit, with the downloading data position of DMA interface, be connected, while for the data bit width when DMA interface, being 16, if the second download signal is 1, downloading data equals read data bit low 16 of TCM interface, otherwise downloading data equals read data bit high 16 of TCM interface; When the data bit width of DMA interface is 32, downloading data equals the read data bit of TCM interface;
Described intermediate process module comprises:
First uploads signature computation unit, and for triggering at clock along constantly, if request signal and response signal are all 1, and direction signal is 0, and first to upload signal update be 1; At clock, trigger along constantly, if first to upload signal be 1, first to upload signal update be 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1;
Second uploads signature computation unit, and for triggering at clock along constantly, if first to upload signal be 1, second to upload signal update be 1; At clock, trigger along constantly, if second to upload signal be 1, second to upload signal update be 0;
The 3rd uploads signature computation unit, and for triggering at clock along constantly, if second to upload signal be 1, the 3rd to upload signal update be 1; At clock, trigger along constantly, if the 3rd to upload signal be 1, the 3rd to upload signal update be 0;
The first download signal computing unit, for triggering at clock along constantly, if request signal, response signal, direction signal are all 1, the first download signal is updated to 1; At clock, trigger along constantly, if the first download signal is 1, the first download signal is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if the second download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1;
The second download signal computing unit, for triggering along constantly at clock, if the first download signal is 1, the second download signal is updated to 1; At clock, trigger along constantly, if the second download signal is 1, the second download signal is updated to 0;
The 3rd download signal computing unit, for triggering along constantly at clock, if the second download signal is 1, the 3rd download signal is updated to 1; At clock, trigger along constantly, if the 3rd download signal is 1, the 3rd download signal is updated to 0;
The TCM module comprises:
Read-write marking signal computing unit, be connected with the read-write marker bit of TCM interface, and while for the data bit width when DMA interface, being 16, the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface is 32, the read-write marking signal equals second and uploads signal;
Address calculation, be connected with the address bit of TCM interface, for making current address, equals start address position and current byte number sum, and, when the read-write marking signal is 1, low 2 of 20 gts that address equals current address subtract 1 again; When the read-write marking signal while being 0, address equals 2 of low 20 gts of current address;
The chip selection signal computing unit, be connected with the chip selection signal position of TCM interface, and while for the data bit width when DMA interface, being 16, chip selection signal equals the 3rd and uploads the value that signal, the first download signal, the second download signal carry out exclusive disjunction; When the data bit width of DMA interface is 32, chip selection signal equals second and uploads the value that signal, the first download signal carry out exclusive disjunction;
Byte is selected signature computation unit, with the byte of TCM interface, selects signal bits to be connected, and byte selects 4 of signal to be equal to the read-write marking signal;
Write the data computing unit, with the write data bits of TCM interface, be connected, for when the data bit width of DMA interface is 16, write high 16 uploading datas that equal DMA interface of data, at clock, trigger along constantly, if second to upload signal be 1, write low 16 uploading datas that are updated to DMA interface of data, other the time inscribe data low 16 place values remain unchanged; When the data bit width of DMA interface is 32, write the uploading data that data equal DMA interface.
2. interface switching device according to claim 1, it is characterized in that, trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, the first download signal, the second download signal, the 3rd download signal and all be reset to 0.
3. an interface conversion method, for realizing the data transmission between DMA interface and TCM interface, is characterized in that, comprising:
When from DMA interface to the TCM interface, transmitting data, carry out steps A 1 to A3:
A1. receive the DMA signal from DMA interface;
A2. the received signal of the DMA from DMA interface is converted to the TCM signal;
A3. send the TCM signal after changing to the TCM interface;
When from the TCM interface to DMA interface, transmitting data, carry out step B1 to B3:
B1. receive the TCM signal from the TCM interface;
B2. the received signal of the TCM from the TCM interface is converted to the DMA signal;
B3. send the DMA signal after changing to DMA interface;
Carry out following steps simultaneously:
Calculate start address: at clock, trigger along constantly, if request signal and response signal are 1 simultaneously, what start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Calculate total bytes: at clock, trigger along constantly, if request signal and response signal are 1 simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Calculate current byte number: trigger along constantly at clock, if request signal and response signal are 1 simultaneously, current byte number is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if second upload signal or the second download signal is 1, current byte number is added to 4; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if first upload signal or the first download signal is 1, current byte number is added to 4;
Calculated response signal: trigger along constantly at clock, if request signal is 1, response signal is updated to 1; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, response signal is updated to 0; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second upload signal or the second download signal is 1, and current byte number equals total bytes, response signal is updated to 0;
Signal is uploaded in calculating: when the data bit width of DMA interface is 16, uploads signal and be and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal; Calculate download signal: when the data bit width of DMA interface is 16, download signal is to equal the value that the second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface is 32, download signal equals the second download signal;
Calculate downloading data: when the data bit width of DMA interface is 16, if the second download signal is 1, downloading data equals low 16 of read data bit of TCM interface, otherwise downloading data equals read data bit high 16 of TCM interface; When the data bit width of DMA interface is 32, downloading data equals the read data bit of TCM interface;
Calculate first and upload signal: at clock, trigger along constantly, if request signal and response signal are all 1, and direction signal is 0, and first to upload signal update be 1; At clock, trigger along constantly, if first to upload signal be 1, first to upload signal update be 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if second to upload signal be 1, and current byte number is less than total bytes, first to upload signal update be 1;
Calculate second and upload signal: at clock, trigger along constantly, if first to upload signal be 1, second to upload signal update be 1; At clock, trigger along constantly, if second to upload signal be 1, second to upload signal update be 0;
Calculate the 3rd and upload signal: at clock, trigger along constantly, if second to upload signal be 1, the 3rd to upload signal update be 1; At clock, trigger along constantly, if the 3rd to upload signal be 1, the 3rd to upload signal update be 0;
Calculate the first download signal: at clock, trigger along constantly, if request signal, response signal, direction signal are all 1, the first download signal is updated to 1; At clock, trigger along constantly, if the first download signal is 1, the first download signal is updated to 0; When the data bit width of DMA interface is 16, at clock, trigger along constantly, if the 3rd download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1; When the data bit width of DMA interface is 32, at clock, trigger along constantly, if the second download signal is 1, and current byte number is less than total bytes, the first download signal is updated to 1;
Calculate the second download signal: at clock, trigger along constantly, if the first download signal is 1, the second download signal is updated to 1; At clock, trigger along constantly, if the second download signal is 1, the second download signal is updated to 0;
Calculate the 3rd download signal: at clock, trigger along constantly, if the second download signal is 1, the 3rd download signal is updated to 1; At clock, trigger along constantly, if the 3rd download signal is 1, the 3rd download signal is updated to 0;
Calculate the read-write marking signal: when the data bit width of DMA interface is 16, the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface is 32, the read-write marking signal equals second and uploads signal;
Calculated address: make current address equal start address position and current byte number sum,, when the read-write marking signal is 1, low 2 of 20 gts that address equals current address subtract 1 again; When the read-write marking signal while being 0, address equals 2 of low 20 gts of current address;
Calculate chip selection signal: when the data bit width of DMA interface is 16, chip selection signal equals the 3rd and uploads the value that signal, the first download signal, the second download signal carry out exclusive disjunction; When the data bit width of DMA interface is 16, chip selection signal equals second and uploads the value that signal, the first download signal carry out exclusive disjunction;
Calculate byte and select signal: byte selects 4 of signal to be equal to the read-write marking signal;
Data are write in calculating: when the data bit width of DMA interface is 16, write high 16 uploading datas that equal DMA interface of data, at clock, trigger along constantly, if second to upload signal be 1, write low 16 uploading datas that are updated to DMA interface of data, other the time inscribe data low 16 place values remain unchanged; When the data bit width of DMA interface is 32, write the uploading data that data equal DMA interface.
4. interface conversion method according to claim 3, it is characterized in that, trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, the first download signal, the second download signal, the 3rd download signal and all be reset to 0.
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Address after: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 510555 No. 107 Bowen Road, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: Guangzhou Ankai Microelectronics Co.,Ltd. |