CN102375795A - Interface conversion device and conversion method - Google Patents
Interface conversion device and conversion method Download PDFInfo
- Publication number
- CN102375795A CN102375795A CN2010102624872A CN201010262487A CN102375795A CN 102375795 A CN102375795 A CN 102375795A CN 2010102624872 A CN2010102624872 A CN 2010102624872A CN 201010262487 A CN201010262487 A CN 201010262487A CN 102375795 A CN102375795 A CN 102375795A
- Authority
- CN
- China
- Prior art keywords
- signal
- download
- interface
- dma
- upload
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to an interface conversion device and an interface conversion method. The interface conversion device comprises a DMA (Direct Memory Access) module, an intermediate processing module, a TCM (Terminal-to-Computer Multiplexer) module, wherein the DMA module is connected with a DMA interface for receiving a DMA signal from the DMA interface or transmitting a converted DMA signal to the DMA interface; the intermediate processing module is used for converting the DMA signal received from the DMA interface into a TCM signal and converting the TCM signal received from the TCM interface into a DMA signal; and the TCM module is connected with the TCM interface for transmitting the converted TCM signal to the TCM interface or receiving the TCM signal from the TCM interface. By implementing the technical scheme of the invention, data transmission between the DMA interface and the TCM interface can be realized.
Description
Technical field
The present invention relates to interface conversion, more particularly, relate to a kind of interface switching device and conversion method that realizes the data transmission between DMA interface and the TCM interface.
Background technology
In numerous memory access interfaces, comprise DMA interface, TCM interface; As shown in Figure 1; The functional unit 200 that adopts DMA interface and the storage unit that adopts the TCM interface 300 are owing to DMA communication protocol and TCM communication protocol is different; Make DMA interface and TCM interface completely cut off, that is, functional unit 200 can't storage unit access 300.
The communication protocol of DMA interface and TCM interface is described below:
One, DMA interface:
Dma_req: the request signal position, totally 1 of dma_req is effectively high.Trigger along constantly at clock, during functional unit request DMA data transmission, dma_req is drawn high; Trigger along constantly at clock, when dma_ack was high, functional unit dragged down dma_req.
Dma_addr: the start address position, totally 32 of dma_addr, DMA transmits starting address signal, and functional unit sends the dma_addr signal when drawing high the dma_req signal.
Dma_cnt: the total byte numerical digit, totally 16 of dma_cnt, this DMA transmission needs the total bytes of transmission, and functional unit sends the dma_cnt signal when drawing high the dma_req signal.
Dma_step: address jump position, totally 32 of dma_step.Suppose that low 16 place values are X, high 16 place values are Y, DMA read or write after the X byte data need current location backward redirect Y byte address continue to read or write the X byte again, so repeatedly, accomplish the dma_cnt byte up to reading or writing.
Dma_dir: direction signal position, totally 1 of dma_dir, the direction of expression DMA transmission.0 expression data spread out of from functional unit, and promptly functional unit writes out data; 1 expression data are imported functional unit into, and promptly functional unit reads in data.
Dma_ack: the response signal position, totally 1 of dma_ack, the DMA request response signal, the request of 1 presentation function unit has obtained response; Not response of 0 expression.
Dma_udata: upload data bit, totally 16 or 32 of dma_udata, the data that functional unit writes out through DMA.
Dma_urd: upload signal bits, totally 1 of dma_urd.If present clock triggers the edge constantly, dma_urd is high, and then triggering along moment functional unit at next clock to provide corresponding dma_udata.
Dma_ddata: data download position, totally 16 or 32 of dma_ddata, the data that functional unit reads in through DMA.
Dma_dwr: download signal position, totally 1 of dma_dwr.If it is high that present clock triggers along moment dma_dwr, then can read corresponding dma_ddata at the current time functional unit.
Two, TCM interface signal:
DRADDR: totally 18 of address bits, DRADDR, the address that reads and writes data of expression is a unit with the word, i.e. first word in the 0 corresponding stored unit, second word in the 1 corresponding stored unit.
DRCS: the chip selection signal position, totally 1 of DRCS, the chip selection signal of storage unit is effectively high.
Totally 18 of DRDMAADDR:DRDMAADDR do not use usually, are made as 0.
Totally 1 of DRDMAEN:DRDMAEN does not use usually, is made as 0.
Totally 1 of DRDMACS:DRDMACS does not use usually, is made as 0.
DRIDLE: the status signal position, totally 1 of DRIDLE, 0 expression data TCM reads and writes data; 1 expression data TCM is idle.
DRnRW: read-write marking signal position, totally 1 of DRnRW.DRnRW is 0 expression read memory cell; DRnRW is that storage unit is write in 1 expression.
DRRD: read data bit, totally 32 of DRRD.
Totally 1 of DRSEQ:DRSEQ, 1 expression data TCM address is continuous, and 0 presentation address may not be continuous.
Totally 4 of DRSIZE:DRSIZE, the size of expression data TCM.The DRSIZE minimum is 3, is 11 to the maximum.DRSIZE is that 3 expression data TCM are the 4K byte-sized, 4 expression 8K byte-sized, and 5 expression 16K byte-sized, and the like.The storage unit minimum is the 4K byte, is the 1M byte to the maximum.
Totally 1 of DRWAIT:DRWAIT, data TCM waiting signal, 1 representative data TCM is current can not to respond read-write requests, and 0 represents and can respond.
DRWD: write data bits, totally 32 of DRWD.
DRWBL: byte is selected signal bits, totally 4 of DRWBL, and the byte during data TCM write data is selected signal, and is effectively high.DRWBL from high to low 4 represent respectively DRWD from high to low writing of 4 bytes enable.
Summary of the invention
The technical matters that the present invention will solve is that the above-mentioned defective that can't realize data transmission between DMA interface and the TCM interface to prior art provides a kind of interface switching device, can realize the data transmission between DMA interface and the TCM interface.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of interface switching device, be used to realize the data transmission between DMA interface and the TCM interface, comprising:
Dma module links to each other with DMA interface, is used to receive the DMA signal from DMA interface, or the DMA signal after DMA interface sends conversion;
Intermediate process module, being used for the DMA conversion of signals from DMA interface that is received is the TCM signal, reaching the TCM conversion of signals from the TCM interface that is received is the DMA signal;
The TCM module links to each other with said TCM interface, is used for the TCM signal after the TCM interface sends conversion, or receives the TCM signal from the TCM interface.
In interface switching device of the present invention,
Said dma module comprises:
The start address computing unit links to each other with the start address position of DMA interface, is used for triggering along constantly at clock, if request signal is 1 with response signal simultaneously, what then start address was updated to the start address the start address position of DMA interface exported hangs down 20;
The total bytes computing unit links to each other with the total byte numerical digit of DMA interface, is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then current byte number is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if second upload signal or second download signal is 1, then current byte number is added 4; When the data bit width of DMA interface is 32, trigger along constantly at clock, if first upload signal or first download signal is 1, then current byte number is added 4;
The response signal computing unit links to each other with the response signal position of DMA interface, is used for triggering along constantly at clock, if request signal is 1, then response signal is updated to 1; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, then response signal is updated to 0; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second upload signal or second download signal is 1, and current byte number equals total bytes, then response signal is updated to 0;
Upload signature computation unit, link to each other, be used for when the data bit width of DMA interface is 16, upload signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction with the signal bits of uploading of DMA interface; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
The download signal computing unit links to each other with the download signal position of DMA interface, is used for when the data bit width of DMA interface is 16, and download signal equals the value that second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface was 32, download signal equaled second download signal;
The data download computing unit; Link to each other with the data download position of DMA interface, be used for when the data bit width of DMA interface is 16, if second download signal is 1; Then data download equals read data bit low 16 of TCM interface, otherwise data download equals read data bit high 16 of TCM interface; When the data bit width of DMA interface was 32, data download equaled the read data bit of TCM interface;
Said intermediate process module comprises:
First uploads signature computation unit, is used for triggering along constantly at clock, if request signal and response signal all are 1, and direction signal is 0, and then first to upload signal update be 1; Trigger along constantly at clock, if first to upload signal be 1, then first to upload signal update be 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1;
Second uploads signature computation unit, is used for triggering along constantly at clock, if first to upload signal be 1, then second to upload signal update be 1; Trigger along constantly at clock, if second to upload signal be 1, then second to upload signal update be 0;
The 3rd uploads signature computation unit, is used for triggering along constantly at clock, if second to upload signal be 1, then the 3rd to upload signal update be 1; Trigger along constantly at clock, if the 3rd to upload signal be 1, then the 3rd to upload signal update be 0;
The first download signal computing unit is used for triggering along constantly at clock, all is 1 as if request signal, response signal, direction signal, and then first download signal is updated to 1; Trigger along constantly at clock, if first download signal is 1, then first download signal is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1;
The second download signal computing unit is used for triggering along constantly at clock, if first download signal is 1, then second download signal is updated to 1; Trigger along constantly at clock, if second download signal is 1, then second download signal is updated to 0;
The 3rd download signal computing unit is used for triggering along constantly at clock, if second download signal is 1, then the 3rd download signal is updated to 1; Trigger along constantly at clock, if the 3rd download signal is 1, then the 3rd download signal is updated to 0;
The TCM module comprises:
Read-write marking signal computing unit links to each other with the read-write marker bit of TCM interface, is used for when the data bit width of DMA interface is 16, and the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface was 32, the read-write marking signal equaled second and uploads signal;
Address calculation links to each other with the address bit of TCM interface, is used to make the current address to equal start address position and current byte number sum, and then when the read-write marking signal was 1, low 2 of 20 gts that the address equals the current address subtracted 1 again; When read-write marking signal when being 0, the address equals 2 of low 20 gts of current address;
The chip selection signal computing unit links to each other with the chip selection signal position of TCM interface, is used for when the data bit width of DMA interface is 16, and chip selection signal equals the 3rd and uploads the value that signal, first download signal, second download signal carry out exclusive disjunction; When the data bit width of DMA interface was 32, chip selection signal equaled second and uploads the value that signal, first download signal carry out exclusive disjunction;
Byte is selected signature computation unit, selects signal bits to link to each other with the byte of TCM interface, and byte selects 4 of signal to be equal to the read-write marking signal;
The write data computing unit; Link to each other with the write data bits of TCM interface, be used for when the data bit width of DMA interface is 16, high 16 data of uploading that equal DMA interface of write data; Trigger along constantly at clock; If second to upload signal be 1, low 16 data of uploading that are updated to DMA interface of write data then, other constantly low 16 place values of write data remain unchanged; When the data bit width of DMA interface was 32, write data equaled the data of uploading of DMA interface.
In interface switching device of the present invention; Trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, first download signal, second download signal, the 3rd download signal and all be reset to 0.
The present invention also constructs a kind of interface conversion method, is used to realize the data transmission between DMA interface and the TCM interface, it is characterized in that, comprising:
When during to TCM interface transmission data, carrying out steps A 1 to A3 from DMA interface:
A1. receive DMA signal from DMA interface;
A2. be the TCM signal with the DMA conversion of signals that is received from DMA interface;
A3. send the TCM signal after changing to the TCM interface;
When during to DMA interface transmission data, carrying out step B1 to B3 from the TCM interface:
B1. receive TCM signal from the TCM interface;
B2. be the DMA signal with the TCM conversion of signals that is received from the TCM interface;
B3. send the DMA signal after changing to DMA interface.
In interface conversion method of the present invention, carry out following steps simultaneously:
Calculate start address: trigger along constantly at clock, if request signal is 1 with response signal simultaneously, what then start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Calculate total bytes: trigger along constantly at clock, if request signal and response signal are 1 simultaneously, then total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Calculate current byte number: trigger along constantly at clock,, then current byte number is updated to 0 if request signal and response signal are 1 simultaneously; When the data bit width of DMA interface is 16, trigger along constantly at clock, if second upload signal or second download signal is 1, then current byte number is added 4; When the data bit width of DMA interface is 32, trigger along constantly at clock, if first upload signal or first download signal is 1, then current byte number is added 4;
Calculated response signal: trigger along constantly at clock,, then response signal is updated to 1 if request signal is 1; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, then response signal is updated to 0; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second upload signal or second download signal is 1, and current byte number equals total bytes, then response signal is updated to 0;
Signal is uploaded in calculating: when the data bit width of DMA interface is 16, uploads signal and be and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
Calculate download signal: when the data bit width of DMA interface was 16, download signal was to equal the value that second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface was 32, download signal equaled second download signal;
Calculate data download: when the data bit width of DMA interface was 16, if second download signal is 1, then data download equaled low 16 of read data bit of TCM interface, otherwise data download equals read data bit high 16 of TCM interface; When the data bit width of DMA interface was 32, data download equaled the read data bit of TCM interface;
Calculate first and upload signal: trigger along constantly at clock, if request signal and response signal all are 1, and direction signal is 0, and then first to upload signal update be 1; Trigger along constantly at clock, if first to upload signal be 1, then first to upload signal update be 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1;
Calculate second and upload signal: trigger along constantly at clock, if first to upload signal be 1, then second to upload signal update be 1; Trigger along constantly at clock, if second to upload signal be 1, then second to upload signal update be 0;
Calculate the 3rd and upload signal: trigger along constantly at clock, if second to upload signal be 1, then the 3rd to upload signal update be 1; Trigger along constantly at clock, if the 3rd to upload signal be 1, then the 3rd to upload signal update be 0;
Calculate first download signal: triggering along constantly at clock, all is 1 as if request signal, response signal, direction signal, and then first download signal is updated to 1; Trigger along constantly at clock, if first download signal is 1, then first download signal is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1;
Calculate second download signal: trigger along constantly at clock, if first download signal is 1, then second download signal is updated to 1; Trigger along constantly at clock, if second download signal is 1, then second download signal is updated to 0;
Calculate the 3rd download signal: trigger along constantly at clock, if second download signal is 1, then the 3rd download signal is updated to 1; Trigger along constantly at clock, if the 3rd download signal is 1, then the 3rd download signal is updated to 0;
Calculate the read-write marking signal: when the data bit width of DMA interface was 16, the read-write marking signal equaled the 3rd and uploads signal; When the data bit width of DMA interface was 32, the read-write marking signal equaled second and uploads signal;
Calculated address: make the current address equal start address position and current byte number sum, then when the read-write marking signal was 1, low 2 of 20 gts that the address equals the current address subtracted 1 again; When read-write marking signal when being 0, the address equals 2 of low 20 gts of current address;
Calculate chip selection signal: when the data bit width of DMA interface was 16, chip selection signal equaled the 3rd and uploads the value that signal, first download signal, second download signal carry out exclusive disjunction; When the data bit width of DMA interface was 16, chip selection signal equaled second and uploads the value that signal, first download signal carry out exclusive disjunction;
Calculate byte and select signal: byte selects 4 of signal to be equal to the read-write marking signal;
Calculate write data: when the data bit width of DMA interface is 16; High 16 data of uploading that equal DMA interface of write data; Trigger along constantly at clock; If second to upload signal be 1, low 16 data of uploading that are updated to DMA interface of write data then, other constantly low 16 place values of write data remain unchanged; When the data bit width of DMA interface was 32, write data equaled the data of uploading of DMA interface.
In interface conversion method of the present invention; Trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, first download signal, second download signal, the 3rd download signal and all be reset to 0.
The technical scheme of embodiment of the present invention; Because ability will be converted into the TCM signal from the DMA signal of DMA interface and will be the DMA signal from the TCM conversion of signals of TCM interface; So can realize the data transmission between DMA interface and the TCM interface; And then make that the functional unit that has DMA interface can be visited the storage unit that has the TCM interface.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
Fig. 1 is the functional unit and the storage unit that has the TCM interface that has DMA interface in the prior art;
Fig. 2 is the building-block of logic of interface switching device embodiment one of the present invention;
Fig. 3 is the building-block of logic of interface switching device embodiment two of the present invention;
Fig. 4 A is from the process flow diagram of DMA interface to TCM interface transmission data embodiment one in the interface conversion method of the present invention;
Fig. 4 B is from the process flow diagram of TCM interface to DMA interface transmission data embodiment one in the interface conversion method of the present invention;
Fig. 5 A is the sequential chart of the present invention from DMA interface each signal when the TCM interface transmits 32 bit data;
Fig. 5 B is the sequential chart of the present invention from TCM interface each signal when DMA interface transmits 32 bit data;
Fig. 5 C is the sequential chart of the present invention from DMA interface each signal when the TCM interface transmits 16 bit data;
Fig. 5 D be the present invention from the TCM interface when DMA interface transmits 16 bit data, the sequential chart of each signal.
Embodiment
As shown in Figure 2; In the building-block of logic of interface switching device embodiment one of the present invention; This interface switching device is used to realize the data transmission between DMA interface and the TCM interface, and this interface switching device comprises dma module 110, intermediate process module 120 and TCM module 130.Wherein, dma module 110 links to each other with DMA interface (Fig. 2 is not shown), is used to receive the DMA signal from DMA interface, or the DMA signal after DMA interface sends conversion; It is the TCM signal that intermediate process module 120 is used for the DMA conversion of signals from DMA interface that is received, and reaching what received is the DMA signal from TCM interface TCM conversion of signals; TCM module 130 links to each other with said TCM interface (Fig. 2 is not shown), is used for the TCM signal after the TCM interface sends conversion, or receives the TCM signal from the TCM interface.Implement this technical scheme; Owing to can will be converted into the TCM signal from the DMA signal of DMA interface; And will from the TCM conversion of signals of TCM interface the DMA signal; So can realize the data transmission between DMA interface and the TCM interface, and then make that the functional unit that has DMA interface can be visited the storage unit that has the TCM interface.
As shown in Figure 3, in the building-block of logic of interface switching device embodiment two of the present invention, this interface switching device comprises dma module 110, intermediate process module 120 and TCM module 130.Wherein, dma module 110 comprises start address computing unit 111, total bytes computing unit 112, current byte number computing unit 113, response signal computing unit 114, uploads signature computation unit 115, download signal computing unit 116 and data download computing unit 117; Intermediate process module 120 comprises that first uploads signature computation unit 121, second and upload signature computation unit the 122, the 3rd and upload signature computation unit 123, the first download signal computing unit 124, the second download signal computing unit 125 and the 3rd download signal computing unit 126; TCM module 130 comprises read-write marking signal computing unit 131, address calculation 132, chip selection signal computing unit 133, byte selection signature computation unit 134 and write data computing unit 135.Specify each unit below:
Start address computing unit 111 links to each other with the start address position of DMA interface, is used for triggering along constantly at clock, if request signal is 1 with response signal simultaneously, what then start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Total bytes computing unit 112 links to each other with the total byte numerical digit of DMA interface, is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit 113 is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then current byte number is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if second upload signal or second download signal is 1, then current byte number is added 4; When the data bit width of DMA interface is 32, trigger along constantly at clock, if first upload signal or first download signal is 1, then current byte number is added 4;
Response signal computing unit 114 links to each other with the response signal position of DMA interface, is used for triggering along constantly at clock, if request signal is 1, then response signal is updated to 1; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, then response signal is updated to 0; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second upload signal or second download signal is 1, and current byte number equals total bytes, then response signal is updated to 0;
Upload signature computation unit 115, link to each other, be used for when the data bit width of DMA interface is 16, upload signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction with the signal bits of uploading of DMA interface; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
Download signal computing unit 116 links to each other with the download signal position of DMA interface, is used for when the data bit width of DMA interface is 16, and download signal equals the value that second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface was 32, download signal equaled second download signal;
Data download computing unit 117; Link to each other with the data download position of DMA interface, be used for when the data bit width of DMA interface is 16, if second download signal is 1; Then data download equals read data bit low 16 of TCM interface, otherwise data download equals read data bit high 16 of TCM interface; When the data bit width of DMA interface was 32, data download equaled the read data bit of TCM interface;
First uploads signature computation unit 121, is used for triggering along constantly at clock, if request signal and response signal all are 1, and direction signal is 0, and then first to upload signal update be 1; Trigger along constantly at clock, if first to upload signal be 1, then first to upload signal update be 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1;
Second uploads signature computation unit 122, is used for triggering along constantly at clock, if first to upload signal be 1, then second to upload signal update be 1; Trigger along constantly at clock, if second to upload signal be 1, then second to upload signal update be 0;
The 3rd uploads signature computation unit 123, is used for triggering along constantly at clock, if second to upload signal be 1, then the 3rd to upload signal update be 1; Trigger along constantly at clock, if the 3rd to upload signal be 1, then the 3rd to upload signal update be 0;
The first download signal computing unit 124 is used for triggering along constantly at clock, all is 1 as if request signal, response signal, direction signal, and then first download signal is updated to 1; Trigger along constantly at clock, if first download signal is 1, then first download signal is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1;
The second download signal computing unit 125 is used for triggering along constantly at clock, if first download signal is 1, then second download signal is updated to 1; Trigger along constantly at clock, if second download signal is 1, then second download signal is updated to 0;
The 3rd download signal computing unit 126 is used for triggering along constantly at clock, if second download signal is 1, then the 3rd download signal is updated to 1; Trigger along constantly at clock, if the 3rd download signal is 1, then the 3rd download signal is updated to 0;
Read-write marking signal computing unit 131 links to each other with the read-write marker bit of TCM interface, is used for when the data bit width of DMA interface is 16, and the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface was 32, the read-write marking signal equaled second and uploads signal;
Chip selection signal computing unit 133 links to each other with the chip selection signal position of TCM interface, is used for when the data bit width of DMA interface is 16, and chip selection signal equals the 3rd and uploads the value that signal, first download signal, second download signal carry out exclusive disjunction; When the data bit width of DMA interface was 32, chip selection signal equaled second and uploads the value that signal, first download signal carry out exclusive disjunction;
Byte is selected signature computation unit 134, selects signal bits to link to each other with the byte of TCM interface, and byte selects 4 of signal to be equal to the read-write marking signal;
Write data computing unit 135; Link to each other with the write data bits of TCM interface, be used for when the data bit width of DMA interface is 16, high 16 data of uploading that equal DMA interface of write data; Trigger along constantly at clock; If second to upload signal be 1, low 16 data of uploading that are updated to DMA interface of write data then, other constantly low 16 place values of write data remain unchanged; When the data bit width of DMA interface was 32, write data equaled the data of uploading of DMA interface.
Preferably; In each above computing unit; Trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, first download signal, second download signal, the 3rd download signal and all be reset to 0.
Fig. 4 A and Fig. 4 B be respectively in the interface conversion method of the present invention from DMA interface to TCM interface transmission data with from the process flow diagram of TCM interface to DMA interface transmission data embodiment one; In Fig. 4 A, the method S100 to TCM interface transmission data may further comprise the steps from DMA interface:
S101. receive DMA signal from DMA interface;
S102. be the TCM signal with the DMA conversion of signals that is received from DMA interface;
S103. send the TCM signal after changing to the TCM interface;
In Fig. 4 B, the method S200 to DMA interface transmission data may further comprise the steps from the TCM interface:
S201. receive TCM signal from the TCM interface;
S202. be the DMA signal with the TCM conversion of signals that is received from the TCM interface;
S203. send the DMA signal after changing to DMA interface.
Illustrate interface switching device and interface conversion method below and be the data transmission that how to realize DMA interface and TCM interface.At first should be noted that; From the consideration of circuit complexity, the present invention designs under following condition: the address jump position of DMA interface equals total byte numerical digit, i.e. dma_step=dma_cnt; Also promptly, DMA interface begins to read continuously or write several bytes of total byte from start address; The DRDMAADDR of TCM interface, DRDMAEN, DRDMACS, DRWAIT all connect 0; DRIDLE, DRSEQ does not use, and the present invention does not discuss; DRSIZE carries out rationally linking to each other according to the size of storage unit.
Fig. 5 A is the sequential chart from DMA interface each signal when the TCM interface transmits 32 bit data, in Fig. 5 A:
Rstn is a reset signal, and the negative edge time trigger at t0 constantly, request signal req, response signal ack, is uploaded signal dma_urd, first and uploaded signal urd, second and upload signal urd_d1 and all be reset to 0.
Clk is a clock signal, and at t1 constantly, request signal req (high level is effective) is sent in the request signal position of DMA interface, and both transmit direction signals dir (being 0).
At t2 constantly, response signal ack begins response request signal req.
At t3 constantly, request signal req is dragged down because of the response of response signal ack; Simultaneously, because request signal req, response signal ack are 1, direction signal dir is 0, so first upload signal urd and be updated to 1.
At t4 constantly, because first to upload signal urd be 1, then first upload signal urd and be updated to 0, simultaneously, second uploads signal urd_d1 is updated to 1.
And at t5 constantly, because second to upload signal urd_d1 be 1, then second upload signal urd_d1 and be updated to 0, simultaneously, during less than total bytes, first uploads signal urd is updated to 1 in current number of words.
Upload signal dma_urd and equal first and upload signal urd, promptly to upload the sequential chart of signal urd identical for its sequential chart and first.Read-write marking signal DRnRW equals second and uploads signal urd_d1, and promptly to upload the sequential chart of signal urd_d1 identical for its sequential chart and second.Chip selection signal DRCS equals second and uploads signal urd_d1, and promptly to upload the sequential chart of signal urd_d1 identical for its sequential chart and second.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.
The calculating of the address of explanation transmission data below: at t3 constantly, request signal req and response signal ack are 1 simultaneously, and what start address was updated to the start address of the start address position of DMA interface being sent hangs down 20; Simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is sent, and current byte number is updated to 0.At t4 constantly, because first to upload signal urd be 1, so; Current byte number is updated to 4, and then the current address is start address and current byte number (in the t4 moment, current byte number is updated to 4) sum; Because the address of TCM interface is with the word alignment, so the current address of being calculated is moved to right 2, the calculating owing to the current address is at t4 constantly again; And data transmission is at t5 constantly, that is, carried out the address renewal earlier and carried out data transmission again; So, also should the current address after moving to right be subtracted 1 again, the value of gained is the pairing address D RADDR of transmission data.Can learn through top calculating, at t5 constantly, can be with upload the write data bits DRWD that data bit dma_udata be transferred to TCM interface of 32 bit data from DMA interface.The transmission of one 32 bit data (4 bytes) below only has been described, according to the method described above, has been transmitted each 32 bit data one by one; All transmitted up to a total bytes data, as, at tn constantly; Second to upload signal urd_d1 be 1; And current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
Fig. 5 B is the sequential chart from TCM interface each signal when DMA interface transmits 32 bit data, and in Fig. 5 B, the reset signal rstn among reset signal rstn, request signal req and Fig. 5 A, the calculating principle of request signal req are identical; In addition; At t1 constantly; The both transmit direction signals dir of direction signal position institute of DMA interface is 1; At this moment, the calculating principle of response signal ack, the first download signal dwr, the second download signal dwr_d1 and response signal ack, first among Fig. 5 A upload signal urd, second to upload the calculating principle of signal urd_d1 identical, do not do at this and give unnecessary details.Download signal dma_dwr equals the second download signal dwr_d1, and promptly its sequential chart is identical with the sequential chart of the second download signal dwr_d1.Read-write marking signal DRnRW equals second and upload signal urd_d1 (because of when the data download, do not use second and upload signal urd_d1, and second to upload signal urd_d1 being 0, also is 0 so read and write marking signal DRnRW, not shown) when resetting.Chip selection signal DRCS equals the first download signal dwr, and promptly its sequential chart is identical with the sequential chart of the first download signal dwr.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.Address computation among the calculating of address and Fig. 5 A is roughly the same; Also be: earlier with the start address and current byte number (the t4 moment; Current byte number is updated to 4) addition obtains the current address, again the current address moved to right 2, and the value of gained is the pairing address D RADDR of data transmission.Compare the address computation among Fig. 5 A, need not to subtract 1 again and calculate, because of when the data download, reading and writing marking signal DRnRW is 0.Can learn that through top calculating at t4 constantly, chip selection signal DRCS is 1, this interface switching device is read 32 bit data from the read data bit DRRD of TCM interface, at t5 constantly, 32 bit data of being read is transferred to the data download position dma_ddata of DMA interface.The transmission of one 32 bit data (4 bytes) below only has been described, according to the method described above, has been transmitted each 32 bit data one by one; All transmitted up to a total bytes data, as, at tn constantly; The second download signal dwr_d1 is 1; And current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
Fig. 5 C is the sequential chart from DMA interface each signal when the TCM interface transmits 16 bit data; In Fig. 5 C; The calculating principle of reset signal rstn among reset signal rstn, request signal req, direction signal dir, response signal ack and Fig. 5 A figure, request signal req, direction signal dir, response signal ack is identical, does not do at this and gives unnecessary details.At t3 constantly, request signal req, response signal ack are 1, and direction signal dir is 0, then first upload signal urd and are updated to 1.At t4 constantly, because first to upload signal urd be 1, then second upload signal urd_d1 and be updated to 1.At t5 constantly,, then the 3rd upload signal urd_d2 and be updated to 1 because second to upload signal urd_d1 be 1, simultaneously, if t6 constantly current byte number then first upload signal urd and be updated to 1 less than total bytes.Uploading signal dwr_urd equals first and uploads signal urd and second and upload the value that signal urd_d1 carries out the exclusive disjunction gained.Read-write marking signal DRnRW equals the 3rd and uploads signal urd_d2.Chip selection signal DRCS equals the 3rd and uploads signal urd_d2.Byte select 4 of signal DRWBL all with read and write the identical (not shown) of marking signal DRnRW.The calculating of the address of explanation transmission data below: constantly at t3; Request signal req and response signal ack are 1 simultaneously; Start address is updated to low 20 of the start address of the start address position of DMA interface being sent; Simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is sent, and current byte number is updated to 0.At t5 constantly, because second to upload signal urd_d1 be 1, so current byte number is updated to 4.The current address is the start address and current byte number (the t5 moment; Current byte number is updated to 4) sum; Then the current address of being calculated is moved to right 2; Again because read-write marking signal DRnRW is 1, so the current address that will move to right after 2 subtracts 1 again, the value of gained is the pairing address of transmission data.In addition, at t5 constantly, because second to upload signal urd_d1 be 1, low 16 of the write data bits DRWD of TCM interface are updated to 16 bit data of being transmitted.At t6 constantly, chip selection signal DRCS is 1, and high 16 of the write data bits DRWD of TCM interface equal to upload 16 bit data that data bit dma_udata is transmitted.The transmission course of one 32 (promptly two 16) data below only has been described, according to the method described above, has been transmitted each 16 bit data one by one, all transmitted up to a total bytes data.As, at tn constantly, the 3rd to upload signal urd_d2 be 1, and current byte number equals total bytes, response signal ack is updated to 0, the end data transmission.
Fig. 5 D is the sequential chart from TCM interface each signal when DMA interface transmits 16 bit data, and in Fig. 5 D, the reset signal rstn among reset signal rstn, request signal req and Fig. 5 C figure, the calculating principle of request signal req are identical; In addition; At t1 constantly; DMA interface is 1 to interface switching device both transmit direction signals dir; At this moment, the calculating principle of response signal ack, the first download signal dwr, the second download signal dwr_d1, the 3rd download signal dwr_d2 and response signal ack, first among Fig. 5 C upload signal urd, second and upload signal urd_d1, the 3rd to upload the calculating principle of signal urd_d2 identical, do not do at this and give unnecessary details.Download signal dma_dwr equals the value that the second download signal dwr_d1 and the 3rd download signal dwr_d2 carry out the exclusive disjunction gained.Read-write marking signal DRnRW equals the 3rd and upload signal urd_d2 (because of when the data download, do not use the 3rd and upload signal urd_d2, and the 3rd to upload signal urd_d2 being 0, also is 0 so read and write marking signal DRnRW) when resetting.Chip selection signal DRCS equals the value that the first download signal dwr and the second download signal dwr_d1 carry out the exclusive disjunction gained.4 of byte selection signal DRWBL are all identical with read-write marking signal DRnRW.The calculating of the address of explanation transmission data below: constantly at t 3; Request signal req and response signal ack are 1 simultaneously; Start address is updated to low 20 of the start address of the start address position of DMA interface being sent; Simultaneously, total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is sent, and current byte number is updated to 0.At t5 constantly, because the second download signal dwr_d1 is 1, so current byte number is updated to 4.The current address is start address and current byte number (in the t5 moment, current byte number is updated to 4) sum, and then, because the read-write marking signal is 0, so the current address of being calculated is moved to right 2, the value of gained is the pairing address of transmission data.So; At t5 constantly; Interface switching device is low 16 data download position dma_ddata that are transferred to DMA interface of the read data bit DRRD of TCM interface, then at t6 constantly with high 16 data download position dma_ddata that are transferred to DMA interface of the read data bit DRRD of TCM interface.The transmission of two 16 bit data (4 bytes) below only has been described, according to the method described above, has been transmitted the data of per 4 bytes one by one; All transmitted up to a total bytes data, as, at tn constantly; The 3rd download signal dwr_d2 is 1; And current byte number equals total bytes, and response signal ack is updated to 0, the end data transmission.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (6)
1. an interface switching device is used to realize the data transmission between DMA interface and the TCM interface, it is characterized in that, comprising:
Dma module links to each other with DMA interface, is used to receive the DMA signal from DMA interface, or the DMA signal after DMA interface sends conversion;
Intermediate process module, being used for the DMA conversion of signals from DMA interface that is received is the TCM signal, reaching the TCM conversion of signals from the TCM interface that is received is the DMA signal;
The TCM module links to each other with said TCM interface, is used for the TCM signal after the TCM interface sends conversion, or receives the TCM signal from the TCM interface.
2. interface switching device according to claim 1 is characterized in that,
Said dma module comprises:
The start address computing unit links to each other with the start address position of DMA interface, is used for triggering along constantly at clock, if request signal is 1 with response signal simultaneously, what then start address was updated to the start address the start address position of DMA interface exported hangs down 20;
The total bytes computing unit links to each other with the total byte numerical digit of DMA interface, is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Current byte number computing unit is used for triggering along constantly at clock, if request signal and response signal are 1 simultaneously, then current byte number is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if second upload signal or second download signal is 1, then current byte number is added 4; When the data bit width of DMA interface is 32, trigger along constantly at clock, if first upload signal or first download signal is 1, then current byte number is added 4;
The response signal computing unit links to each other with the response signal position of DMA interface, is used for triggering along constantly at clock, if request signal is 1, then response signal is updated to 1; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, then response signal is updated to 0; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second upload signal or second download signal is 1, and current byte number equals total bytes, then response signal is updated to 0;
Upload signature computation unit, link to each other, be used for when the data bit width of DMA interface is 16, upload signal and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction with the signal bits of uploading of DMA interface; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
The download signal computing unit links to each other with the download signal position of DMA interface, is used for when the data bit width of DMA interface is 16, and download signal equals the value that second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface was 32, download signal equaled second download signal;
The data download computing unit; Link to each other with the data download position of DMA interface, be used for when the data bit width of DMA interface is 16, if second download signal is 1; Then data download equals read data bit low 16 of TCM interface, otherwise data download equals read data bit high 16 of TCM interface; When the data bit width of DMA interface was 32, data download equaled the read data bit of TCM interface;
Said intermediate process module comprises:
First uploads signature computation unit, is used for triggering along constantly at clock, if request signal and response signal all are 1, and direction signal is 0, and then first to upload signal update be 1; Trigger along constantly at clock, if first to upload signal be 1, then first to upload signal update be 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1;
Second uploads signature computation unit, is used for triggering along constantly at clock, if first to upload signal be 1, then second to upload signal update be 1; Trigger along constantly at clock, if second to upload signal be 1, then second to upload signal update be 0;
The 3rd uploads signature computation unit, is used for triggering along constantly at clock, if second to upload signal be 1, then the 3rd to upload signal update be 1; Trigger along constantly at clock, if the 3rd to upload signal be 1, then the 3rd to upload signal update be 0;
The first download signal computing unit is used for triggering along constantly at clock, all is 1 as if request signal, response signal, direction signal, and then first download signal is updated to 1; Trigger along constantly at clock, if first download signal is 1, then first download signal is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1;
The second download signal computing unit is used for triggering along constantly at clock, if first download signal is 1, then second download signal is updated to 1; Trigger along constantly at clock, if second download signal is 1, then second download signal is updated to 0;
The 3rd download signal computing unit is used for triggering along constantly at clock, if second download signal is 1, then the 3rd download signal is updated to 1; Trigger along constantly at clock, if the 3rd download signal is 1, then the 3rd download signal is updated to 0;
The TCM module comprises:
Read-write marking signal computing unit links to each other with the read-write marker bit of TCM interface, is used for when the data bit width of DMA interface is 16, and the read-write marking signal equals the 3rd and uploads signal; When the data bit width of DMA interface was 32, the read-write marking signal equaled second and uploads signal;
Address calculation links to each other with the address bit of TCM interface, is used to make the current address to equal start address position and current byte number sum, and then when the read-write marking signal was 1, low 2 of 20 gts that the address equals the current address subtracted 1 again; When read-write marking signal when being 0, the address equals 2 of low 20 gts of current address;
The chip selection signal computing unit links to each other with the chip selection signal position of TCM interface, is used for when the data bit width of DMA interface is 16, and chip selection signal equals the 3rd and uploads the value that signal, first download signal, second download signal carry out exclusive disjunction; When the data bit width of DMA interface was 32, chip selection signal equaled second and uploads the value that signal, first download signal carry out exclusive disjunction;
Byte is selected signature computation unit, selects signal bits to link to each other with the byte of TCM interface, and byte selects 4 of signal to be equal to the read-write marking signal;
The write data computing unit; Link to each other with the write data bits of TCM interface, be used for when the data bit width of DMA interface is 16, high 16 data of uploading that equal DMA interface of write data; Trigger along constantly at clock; If second to upload signal be 1, low 16 data of uploading that are updated to DMA interface of write data then, other constantly low 16 place values of write data remain unchanged; When the data bit width of DMA interface was 32, write data equaled the data of uploading of DMA interface.
3. interface switching device according to claim 2; It is characterized in that; Trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, first download signal, second download signal, the 3rd download signal and all be reset to 0.
4. an interface conversion method is used to realize the data transmission between DMA interface and the TCM interface, it is characterized in that, comprising:
When during to TCM interface transmission data, carrying out steps A 1 to A3 from DMA interface:
A1. receive DMA signal from DMA interface;
A2. be the TCM signal with the DMA conversion of signals that is received from DMA interface;
A3. send the TCM signal after changing to the TCM interface;
When during to DMA interface transmission data, carrying out step B1 to B3 from the TCM interface:
B1. receive TCM signal from the TCM interface;
B2. be the DMA signal with the TCM conversion of signals that is received from the TCM interface;
B3. send the DMA signal after changing to DMA interface.
5. interface conversion method according to claim 1 is characterized in that, carries out following steps simultaneously:
Calculate start address: trigger along constantly at clock, if request signal is 1 with response signal simultaneously, what then start address was updated to the start address the start address position of DMA interface exported hangs down 20;
Calculate total bytes: trigger along constantly at clock, if request signal and response signal are 1 simultaneously, then total bytes is updated to the total bytes that the total byte numerical digit of DMA interface is exported;
Calculate current byte number: trigger along constantly at clock,, then current byte number is updated to 0 if request signal and response signal are 1 simultaneously; When the data bit width of DMA interface is 16, trigger along constantly at clock, if second upload signal or second download signal is 1, then current byte number is added 4; When the data bit width of DMA interface is 32, trigger along constantly at clock, if first upload signal or first download signal is 1, then current byte number is added 4;
Calculated response signal: trigger along constantly at clock,, then response signal is updated to 1 if request signal is 1; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd upload signal or the 3rd download signal is 1, and current byte number equals total bytes, then response signal is updated to 0; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second upload signal or second download signal is 1, and current byte number equals total bytes, then response signal is updated to 0;
Signal is uploaded in calculating: when the data bit width of DMA interface is 16, uploads signal and be and equal first and upload signal and second and upload the value that signal carries out exclusive disjunction; When the data bit width of DMA interface is 32, uploads signal and equal first and upload signal;
Calculate download signal: when the data bit width of DMA interface was 16, download signal was to equal the value that second download signal and the 3rd download signal are carried out exclusive disjunction; When the data bit width of DMA interface was 32, download signal equaled second download signal;
Calculate data download: when the data bit width of DMA interface was 16, if second download signal is 1, then data download equaled low 16 of read data bit of TCM interface, otherwise data download equals read data bit high 16 of TCM interface; When the data bit width of DMA interface was 32, data download equaled the read data bit of TCM interface;
Calculate first and upload signal: trigger along constantly at clock, if request signal and response signal all are 1, and direction signal is 0, and then first to upload signal update be 1; Trigger along constantly at clock, if first to upload signal be 1, then first to upload signal update be 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second to upload signal be 1, and current byte number is less than total bytes, then first to upload signal update be 1;
Calculate second and upload signal: trigger along constantly at clock, if first to upload signal be 1, then second to upload signal update be 1; Trigger along constantly at clock, if second to upload signal be 1, then second to upload signal update be 0;
Calculate the 3rd and upload signal: trigger along constantly at clock, if second to upload signal be 1, then the 3rd to upload signal update be 1; Trigger along constantly at clock, if the 3rd to upload signal be 1, then the 3rd to upload signal update be 0;
Calculate first download signal: triggering along constantly at clock, all is 1 as if request signal, response signal, direction signal, and then first download signal is updated to 1; Trigger along constantly at clock, if first download signal is 1, then first download signal is updated to 0; When the data bit width of DMA interface is 16, trigger along constantly at clock, if the 3rd download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1; When the data bit width of DMA interface is 32, trigger along constantly at clock, if second download signal is 1, and current byte number is less than total bytes, then first download signal is updated to 1;
Calculate second download signal: trigger along constantly at clock, if first download signal is 1, then second download signal is updated to 1; Trigger along constantly at clock, if second download signal is 1, then second download signal is updated to 0;
Calculate the 3rd download signal: trigger along constantly at clock, if second download signal is 1, then the 3rd download signal is updated to 1; Trigger along constantly at clock, if the 3rd download signal is 1, then the 3rd download signal is updated to 0;
Calculate the read-write marking signal: when the data bit width of DMA interface was 16, the read-write marking signal equaled the 3rd and uploads signal; When the data bit width of DMA interface was 32, the read-write marking signal equaled second and uploads signal;
Calculated address: make the current address equal start address position and current byte number sum, then when the read-write marking signal was 1, low 2 of 20 gts that the address equals the current address subtracted 1 again; When read-write marking signal when being 0, the address equals 2 of low 20 gts of current address;
Calculate chip selection signal: when the data bit width of DMA interface was 16, chip selection signal equaled the 3rd and uploads the value that signal, first download signal, second download signal carry out exclusive disjunction; When the data bit width of DMA interface was 16, chip selection signal equaled second and uploads the value that signal, first download signal carry out exclusive disjunction;
Calculate byte and select signal: byte selects 4 of signal to be equal to the read-write marking signal;
Calculate write data: when the data bit width of DMA interface is 16; High 16 data of uploading that equal DMA interface of write data; Trigger along constantly at clock; If second to upload signal be 1, low 16 data of uploading that are updated to DMA interface of write data then, other constantly low 16 place values of write data remain unchanged; When the data bit width of DMA interface was 32, write data equaled the data of uploading of DMA interface.
6. interface conversion method according to claim 1; It is characterized in that; Trigger along constantly in reset signal, start address, total bytes, current byte number, request signal, response signal, upload signal, first and upload signal, second and upload signal, the 3rd and upload signal, download signal, first download signal, second download signal, the 3rd download signal and all be reset to 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010262487 CN102375795B (en) | 2010-08-25 | 2010-08-25 | Interface conversion device and conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010262487 CN102375795B (en) | 2010-08-25 | 2010-08-25 | Interface conversion device and conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102375795A true CN102375795A (en) | 2012-03-14 |
| CN102375795B CN102375795B (en) | 2013-12-25 |
Family
ID=45794424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010262487 Active CN102375795B (en) | 2010-08-25 | 2010-08-25 | Interface conversion device and conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102375795B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107783927A (en) * | 2016-08-30 | 2018-03-09 | 安凯(广州)微电子技术有限公司 | For connecting the circuit conversion system and method for AXI interfaces and DMA interface |
| WO2021174826A1 (en) * | 2020-03-05 | 2021-09-10 | 苏州浪潮智能科技有限公司 | Method and apparatus for supporting tcm communication by arm server bios, device, and medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050022087A1 (en) * | 2003-02-14 | 2005-01-27 | Ankan Pramanick | Method and system for controlling interchangeable components in a modular test system |
| CN101281577A (en) * | 2008-05-16 | 2008-10-08 | 北京工业大学 | Dependable computing system capable of protecting BIOS and method of use thereof |
-
2010
- 2010-08-25 CN CN 201010262487 patent/CN102375795B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050022087A1 (en) * | 2003-02-14 | 2005-01-27 | Ankan Pramanick | Method and system for controlling interchangeable components in a modular test system |
| CN101281577A (en) * | 2008-05-16 | 2008-10-08 | 北京工业大学 | Dependable computing system capable of protecting BIOS and method of use thereof |
Non-Patent Citations (4)
| Title |
|---|
| 《ARM1136JF-S and ARM1136J-S Revision:r1p5 Technical Reference Manual》 20090220 ARM公司 《ARM1136JF-S and ARM1136J-S Revision:r1p5 Technical Reference Manual》 6-1至6-68,7-1至7-18 1,4 , * |
| 《Industrial Embedded Systems》 20071231 Heiko Hubert等 《Performance and Memory Profiling for Embedded System Design》 94-101 1-6 , * |
| ARM公司: "《ARM1136JF-S and ARM1136J-S Revision:r1p5 Technical Reference Manual》", 《ARM1136JF-S AND ARM1136J-S REVISION:R1P5 TECHNICAL REFERENCE MANUAL》, 20 February 2009 (2009-02-20) * |
| HEIKO HUBERT等: "《Performance and Memory Profiling for Embedded System Design》", 《INDUSTRIAL EMBEDDED SYSTEMS》, 31 December 2007 (2007-12-31), pages 94 - 101 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107783927A (en) * | 2016-08-30 | 2018-03-09 | 安凯(广州)微电子技术有限公司 | For connecting the circuit conversion system and method for AXI interfaces and DMA interface |
| CN107783927B (en) * | 2016-08-30 | 2020-11-20 | 安凯(广州)微电子技术有限公司 | Circuit conversion system and method for connecting AXI interface and DMA interface |
| WO2021174826A1 (en) * | 2020-03-05 | 2021-09-10 | 苏州浪潮智能科技有限公司 | Method and apparatus for supporting tcm communication by arm server bios, device, and medium |
| US11669477B2 (en) | 2020-03-05 | 2023-06-06 | Inspur Suzhou Intelligent Technology Co., Ltd. | Method and apparatus for supporting TCM communication by BIOS of ARM server, device, and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102375795B (en) | 2013-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109271335B (en) | FPGA implementation method for DDR cache of multi-channel data source | |
| CN105718390B (en) | Low-power in shared memory link enters | |
| CN106257434B (en) | A kind of data transmission method and device based on enhanced peripheral interconnection protocol bus | |
| CN110309088B (en) | ZYNQ FPGA chip, data processing method thereof and storage medium | |
| CN108351813A (en) | For quick in nonvolatile memory（NVMe）An other NVMe input/output is enabled on the heterogeneous networks address of controller（IO）The method and apparatus of queue | |
| CN105190524B (en) | Apparatus and method for the descriptor of the data transmission that generates whereabouts and nonvolatile semiconductor memory from memory driver | |
| CN103559156B (en) | Communication system between a kind of FPGA and computing machine | |
| CN101599004B (en) | SATA controller based on FPGA | |
| CN102122256B (en) | Pipe-type communication method and system for interprocess communication | |
| CN104798010A (en) | Serial storage protocol compatible frame conversion, at least in part | |
| JP2013020284A (en) | Device controller, usb device controller, and power control method | |
| CN103106169A (en) | High speed bus interface expansion structure based on aurora protocol | |
| CN103353851A (en) | Method and equipment for managing tasks | |
| CN101394349B (en) | Data transmission method and system in communication of different interface devices | |
| CN103077149A (en) | Method and system for transmitting data | |
| CN1326057C (en) | Bus system and bus interface for connection to a bus | |
| CN101004674B (en) | Data processing system and high-definition TV including the data processing system | |
| CN106489132A (en) | The method of read-write data, device, storage device and computer system | |
| CN103019990A (en) | Method for uploading data at collection end through starting PCI-E (Peripheral Component Interconnect-Express) bus DMA (Direct Memory Access) | |
| CN103019987A (en) | Method and system for transmitting data on basis of USB (universal serial bus) interfaces | |
| CN103222286B (en) | Route switching device, network switching system and route switching method | |
| JP2022038688A (en) | Memory system and control method | |
| JP2015041291A (en) | Storage device | |
| CN102375795B (en) | Interface conversion device and conversion method | |
| CN102013984B (en) | Two-dimensional net network-on-chip system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 510555 No. 107 Bowen Road, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 3 / F, C1 area, innovation building, 182 science Avenue, Science City, Guangzhou, Guangdong 510663 Patentee before: Guangzhou Ankai Microelectronics Co.,Ltd. |