CN102364878B - Large-range linear adjustable delay circuit - Google Patents

Abstract

The invention relates to a large-range linear adjustable delay circuit, which comprises an oscillation circuit and a frequency dividing circuit. The oscillation circuit comprises a first NOT gate, a second NOT gate, a current limiting resistor, a T-shaped resistance network and a capacitor, wherein the first NOT gate and the second NOT gate are connected in series; the current limiting resistor is connected between the input end of the first NOT gate and one end of the capacitor; the other end of the capacitor is connected with the output end of the second NOT gate; the T-shaped resistance network comprises a first resistive divider, a second resistive divider and a delay resistor; one end of each of the first resistive divider, the second resistive divider and the delay resistor is in T-shaped connection; the other end of the first resistive divider is connected with the output end of the first NOT gate; the other end of the second resistive divider is connected with the output end of the second NOT gate; the other end of the delay resistor is connected with the common end of the current limiting resistor and the capacitor; and the output end of the oscillation circuit is led out from the output end of the second NOT gate. The large-range linear adjustable delay circuit replaces the delay resistor by adopting the T-shaped resistance network, so linear relationships between the delay resistor and delay time are improved, and the accuracy of the delay circuit is improved; and the large-range linear adjustable delay circuit has a small volume and high reliability.

Description

Linear on a large scale adjustable delay circuit

Technical field

The present invention relates to a kind of delay circuit, specifically, relate to a kind of linear adjustable delay circuit on a large scale.

Background technology

Delay circuit generally is made up of the oscillating circuit sum counter.Multivibrator with R, C and CMOS gate circuit constitute because it is simple in structure, input impedance is very high, need not just can obtain bigger time constant with jumbo capacitor, thereby obtains using more widely.It changes time of delay through the resistance that changes a time delay resistance.The modularization trend of modern electronic product makes other of delay circuit together partly integrated, only draws through two and brings in external time delay resistance, reaches the adjustable purpose of time-delay.

But the time delay resistance of existing adjustable delay circuit and the linear relationship of time of delay are relatively poor, and particularly in time-delay on a large scale, its precision is relatively poor.For example differing 10 times time of delay, its error reaches ± and 5%, this does not often reach the required precision of delay circuit.

Summary of the invention

The purpose of this invention is to provide the linear adjustable delay circuit that a kind of error is less, precision is higher on a large scale.

For achieving the above object, the technical scheme that the present invention adopts is:

A kind of linear on a large scale adjustable delay circuit; It comprises the oscillating circuit that is used to produce oscillator signal, the frequency dividing circuit that is used to produce time delayed signal; The output of described oscillating circuit is connected with the input of described frequency dividing circuit, and described oscillating circuit comprises first not gate that is in series and second not gate, current-limiting resistance, T type resistor network, electric capacity;

Described current-limiting resistance is connected between the end of input and described electric capacity of described first not gate, and the other end of described electric capacity is connected with the output of described second not gate;

Described T type resistor network comprises first divider resistance, second divider resistance, the time delay resistance that an end phase T type connects; The other end of described first divider resistance is connected with the output of described first not gate; The other end of described second divider resistance is connected with the output of described second not gate, and the other end of described time delay resistance is connected with the common ends of described current-limiting resistance and described electric capacity;

The output of described oscillating circuit is drawn by the output of described second not gate.

Preferably, described time delay resistance is resistance fixed resistance or adjustable resistance.

Preferably, the time delayed signal that is produced of described frequency dividing circuit is the feedback control signal of the described frequency dividing circuit of input.

Preferably, described frequency dividing circuit comprises the CMOS counter.

Preferably, the output of described oscillating circuit is drawn test lead, and the oscillator signal that described oscillating circuit produced is drawn as test signal.

Preferably, the oscillator signal of described oscillating circuit generation is the square wave pulse.

Preferably, the part except that described time delay resistance of described oscillating circuit is integrated into time delay module with described frequency dividing circuit, and described time delay resistance is the outer meeting resistance of described time delay module.

Because the technique scheme utilization, the present invention compared with prior art has advantage:

1, the present invention adopts T type resistor network to substitute the time delay resistance of existing delay circuit, has improved the linear relationship of time delay resistance and time of delay, has improved the precision of delay circuit;

2, advantages of small volume of the present invention, reliability height.

Description of drawings

Accompanying drawing 1 is the circuit block diagram of the linear adjustable delay circuit of invention on a large scale.

Accompanying drawing 2 is the circuit diagram of the oscillating circuit of linear on a large scale adjustable delay circuit of the present invention.

Accompanying drawing 3 is the circuit diagram of the frequency dividing circuit of linear on a large scale adjustable delay circuit of the present invention.

Accompanying drawing 4 is the oscillogram of linear on a large scale adjustable delay circuit of the present invention.

Accompanying drawing 5 is the circuit diagram of linear on a large scale adjustable delay circuit of the present invention when no current-limiting resistance.

Accompanying drawing 6 is the equivalent circuit diagram of linear on a large scale adjustable delay circuit of the present invention when no current-limiting resistance.

Accompanying drawing 7 is the equivalent circuit diagram of linear adjustable delay circuit of the present invention when current-limiting resistance is arranged on a large scale.

Embodiment

Below in conjunction with embodiment shown in the drawings the present invention is further described.

Embodiment one: shown in accompanying drawing 1.

A kind of linear on a large scale adjustable delay circuit, it comprises the oscillating circuit that is used to produce oscillator signal, the frequency dividing circuit that is used to produce time delayed signal, the output of oscillating circuit is connected with the input of frequency dividing circuit.

Shown in accompanying drawing 2, oscillating circuit comprises first not gate that is in series and second not gate, current-limiting resistance Rs, T type resistor network, capacitor C t.Current-limiting resistance Rs is connected between the end of input and capacitor C t of first not gate, and the other end of capacitor C t is connected with the output of second not gate.T type resistor network comprises the first divider resistance R1, the second divider resistance R2, the time delay resistance Rext that an end phase T type connects; The other end of the said first divider resistance R1 is connected with the output of first not gate, and the other end of the second divider resistance R2 is connected with the output of second not gate, and the other end of time delay resistance Rext is connected with the common ends of capacitor C t with current-limiting resistance Rs.Time delay resistance Rext is required resistance fixed resistance or adjustable resistance.The output of oscillating circuit is drawn by the output of second not gate.

Shown in accompanying drawing 3, frequency dividing circuit comprises the CMOS counter, and its input is introduced by the 5th pin, and output is drawn by the 4th pin.

Oscillating circuit produces self-oscillation, does not need external trigger signal, and after energized, it produces oscillator signal, and this oscillator signal is the square wave pulse.Oscillator signal inserts frequency dividing circuit, behind frequency division, produces time delayed signal output.This time delayed signal is the feedback control signal of input frequency dividing circuit, and it makes the output of time delayed signal remain unchanged.Because frequency dividing circuit only carries out frequency division to the output of oscillating circuit, thereby it can not influence the precision of delay circuit.

The output of oscillating circuit is drawn test lead, and the oscillator signal that oscillating circuit produced is drawn as test signal, because this test signal frequency division not, thereby its cycle is shorter, test signal multiply by divide ratio and is delay time.The feasible test to long delay of this design is converted into test of short time parameter.

The part except that time delay resistance Rext and the frequency dividing circuit of oscillating circuit are integrated into time delay module, and time delay resistance Rext is the outer meeting resistance of time delay module.

1 end of supposing first not gate is a high level, and then 2,3 ends are low level, and 4 ends are high level.A point current potential is because capacitor C t discharges and recharges continuous reduction through time delay resistance Rext.When the breakover voltage that is lower than the CMOS gate circuit when a point current potential is threshold voltage, 2,3 ends from low transition to high level, 4 ends from the high level saltus step to low level.Because the voltage at electric capacity two ends can not suddenly change, when 4 terminal potentials during from high level saltus step to low level, a point current potential becomes lower, and to keep the electric capacity voltage constant, 2,3 ends charge to capacitor C t through time delay resistance Rext then, and a point current potential raises gradually.When the breakover voltage that is higher than the CMOS gate circuit when a point current potential is threshold voltage, 2,3 terminal potentials from the high level saltus step to low level, 4 ends from low transition to high level.So repeatedly, 4 ends output rectangular pulse.The waveform of each point is shown in accompanying drawing 4.

The cycle t of oscillating circuit calculates as follows:

Can know t=t by accompanying drawing 4 ₁+ t ₂+ t _A+ t _B, wherein, t ₁+ t ₂Be the cycle of oscillation during no current-limiting resistance Rs in the accompanying drawing 2.

Cycle of oscillation when calculating earlier no R current-limiting resistance Rs.Shown in accompanying drawing 5, establishing the A point is high level, and then the B point is a low level, and the C point is a high level.

Use the Dai Weinan equivalent transformation, in this moment oscillating circuit capacitor discharge and recharge equivalent electric circuit shown in accompanying drawing 6, R3=R1//R2 wherein, $V_{{\mathrm{DD}}^{\&prime;}}=\frac{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}2\&CenterDot;V_{\mathrm{DD}}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}1+R2}.$

Suppose that capacitor C t voltage is Uc (t), then has

V _DD′+Uc(t)＝ic·(Rext+R3)

$\mathrm{ic}=\frac{\mathrm{dq}}{\mathrm{dt}}=-\frac{d\left(\mathrm{Cuc}\right)}{\mathrm{dt}}=-C\frac{\mathrm{duc}}{\mathrm{dt}}$

$\frac{\mathrm{Duc}}{\mathrm{Dt}}-\frac{1}{-\mathrm{\&tau;}}\mathrm{Uc}=\frac{V_{{\mathrm{DD}}^{\&prime;}}}{-\mathrm{\&tau;}},$ The Ct of τ=(Rext+R3) wherein.

Know Uc (t)=Ke by mathematics ^{-t/ τ}-V _{DD '}, know by accompanying drawing 4, during t=0, Uc=U _A-U _C=V _F, try to achieve K=V _F+ V _{DD '}Thereby,

Uc(t)＝(V _F+V _DD′)e ^-t/τ-V _DD′

Work as t=t ₁The time, Uc (t)=V _TR1-V _DD, the substitution following formula is tried to achieve,

${\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">t</figure-callout>}}_1=-\mathrm{\&tau;}\ln \frac{V_{\mathrm{TR}1}-V_{\mathrm{DD}}+V_{{\mathrm{DD}}^{\&prime;}}}{V_{{\mathrm{DD}}^{\&prime;}}+V_F}$

Ask t ₂For the multivibrator B point high level shown in the accompanying drawing 5, C point low level, its capacitor charging/discharging differential equation does

ic·(Rext+R3)+V _DD′＝Uc(t)

$\mathrm{ic}=\frac{\mathrm{dq}}{\mathrm{dt}}=-\frac{d\left(\mathrm{Cuc}\right)}{\mathrm{dt}}=-C\frac{\mathrm{duc}}{\mathrm{dt}}$

$\frac{\mathrm{Duc}}{\mathrm{Dt}}-\frac{1}{-\mathrm{\&tau;}}\mathrm{Uc}=\frac{V_{{\mathrm{DD}}^{\&prime;}}}{-\mathrm{\&tau;}},$ The Ct of τ=(Rext+R3) wherein.

Get Uc (t)=Ke by mathematics ^{-t/ τ}+ V _{DD '}, know by accompanying drawing 4, during t=0, Uc=U _A-U _C=-V _F, try to achieve K=-V _F-V _{DD '}Thereby,

Uc(t)＝(-V _F-V _DD′)e ^-t/τ+V _DD′

Work as t=t ₂The time, Uc (t)=V _TR2, the substitution following formula is tried to achieve,

${\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">t</figure-callout>}}_2=-\mathrm{\&tau;}\ln \frac{V_{{\mathrm{DD}}^{\&prime;}}-V_{\mathrm{TR}2}}{V_{{\mathrm{DD}}^{\&prime;}}+V_F}$

When then not having current-limiting resistance Rs, the cycle of oscillation of oscillating circuit:

$t={\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">t</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">t</figure-callout>}}_2=-\mathrm{\&tau;}\ln \frac{(V_{{\mathrm{DD}}^{\&prime;}}+V_{\mathrm{TR}1}-V_{\mathrm{DD}})(V_{{\mathrm{DD}}^{\&prime;}}-V_{\mathrm{TR}2})}{{(V_{{\mathrm{DD}}^{\&prime;}}+V_F)}^2}$

For Fig. 2,4 end high level of second not gate, during 2,3 end low levels, its capacitor C t discharges and recharges the Dai Weinan equivalent transformation shown in accompanying drawing 7, R3=R1//R2 wherein, $V_{{\mathrm{DD}}^{\&prime;}}=\frac{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}2\&CenterDot;V_{\mathrm{DD}}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}1+R2}.$

Suppose that capacitor C t voltage is Uc (t), then has

$-C\frac{\mathrm{duc}}{\mathrm{dt}}=\frac{\mathrm{uc}-V_F}{\mathrm{Rs}}+\frac{\mathrm{uc}+V_{{\mathrm{DD}}^{\&prime;}}}{\mathrm{Rt}+\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}3}$

$\frac{\mathrm{duc}}{\mathrm{dt}}-\frac{1}{-{\mathrm{\&tau;}}_1}\mathrm{uc}=-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-R{t}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}\&CenterDot;{\mathrm{Rt}}^{\&prime;}\&CenterDot;\mathrm{Ct}}$

Rt '=Rext+R3 wherein, τ ₁=(Rs//Rt ') Ct.Because Rt '＞＞Rt, so τ ₁=RsCt.

Get by mathematics, $\mathrm{Uc}\left(t\right)={\mathrm{Ke}}^{-\frac{t}{{\mathrm{\&tau;}}_1}}-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}},$ Can knowledge by accompanying drawing 4, during t=0, Uc=U _A-U _C=V _TR2, the substitution following formula is tried to achieve the K value, and then Uc (t) expression formula becomes:

$\mathrm{Uc}\left(t\right)=({\mathrm{<figure-callout\; id="2"\; label="V\; TR"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{TR}}+\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}})e^{-\frac{t}{\mathrm{\&tau;}1}}-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}}$

Work as t=t _AThe time, Uc (t)=V _F, the substitution following formula is tried to achieve,

$t_A=-{\mathrm{\&tau;}}_1\ln \frac{\mathrm{Rs}(V_F+V_{D{D}^{\&prime;}})}{\mathrm{Rs}(V_{{\mathrm{DD}}^{\&prime;}}+V_{\mathrm{TR}2})+{\mathrm{Rt}}^{\&prime;}(V_{\mathrm{TR}2}-V_F)}$

For 4 end low levels of accompanying drawing 2, the second not gates, during 2,3 end high level, its capacitor C t discharges and recharges the differential equation and is: $-C\frac{\mathrm{Duc}}{\mathrm{Dt}}=\frac{\mathrm{Uc}+V_{\mathrm{DD}}}{\mathrm{Rt}+\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">R</figure-callout>}3}+\frac{\mathrm{Uc}-V_F}{\mathrm{Rs}},$ That is:

$\frac{\mathrm{Duc}}{\mathrm{Dt}}-\frac{1}{-{\mathrm{\&tau;}}_1}\mathrm{Uc}=-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-R{t}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}\&CenterDot;{\mathrm{Rt}}^{\&prime;}\&CenterDot;\mathrm{Ct}},$ τ wherein ₁=RsCt.

Know by mathematics, $\mathrm{Uc}\left(t\right)={\mathrm{Ke}}^{-\frac{t}{{\mathrm{\&tau;}}_1}}-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}},$

Know by accompanying drawing 4, during t=0, Uc=U _C-U _A=V _DD-V _TR1, the substitution following formula is tried to achieve the K value, and then following formula becomes:

$\mathrm{Uc}\left(t\right)=({V_{\mathrm{DD}}-\mathrm{<figure-callout\; id="1"\; label="V\; TR"\; filenames="111026102910.png,111026102920.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{TR}}+\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}})e^{-\frac{t}{{\mathrm{\&tau;}}_1}}-\frac{\mathrm{Rs}\&CenterDot;V_{{\mathrm{DD}}^{\&prime;}}-{\mathrm{Rt}}^{\&prime;}\&CenterDot;V_F}{\mathrm{Rs}+{\mathrm{Rt}}^{\&prime;}}$

Work as t=t _BThe time, Uc (t)=V _F, the substitution following formula is tried to achieve:

$t_B=-{\mathrm{\&tau;}}_1\ln \frac{\mathrm{Rs}(V_F+V_{D{D}^{\&prime;}})}{\mathrm{Rs}(V_{\mathrm{DD}}+V_{{\mathrm{DD}}^{\&prime;}}-V_{\mathrm{TR}1})+{\mathrm{Rt}}^{\&prime;}({V_{\mathrm{DD}}-V}_{\mathrm{TR}1}-V_F)}$

Can know t by above-mentioned analysis ₁+ t ₂Rext is linear with time delay resistance.t _A+ t _BWith lnRext be linear relationship basically.When time delay resistance Rext increases 10 times, t ₁+ t ₂Increase 10 times, and t _A+ t _BIncrease less than ln10 doubly, promptly less than 2.3 times, and t _A+ t _BThe time that accounts for total time-delay t is very little, thereby, in the cycle of whole oscillating circuit, t ₁+ t ₂Can be considered constant, promptly do not change with time delay resistance Rext.(t of the present invention _A+ t _BThe maximum of)/t is about 2% at the minimum period place of oscillating circuit.If oscillating circuit is Rext=R during the minimum period ₀, t then _A+ t _B, t ₁+ t ₂Can be expressed as following form:

t _A+ t _B=k ₀RsCt, wherein k ₀Be constant,

t ₁+ t ₂=k ₁(R0+R1//R2) Ct, wherein k ₁Be constant.

Then can be expressed as the cycle of oscillation of this linear on a large scale adjustable delay circuit:

t＝t ₁+t ₂+t _A+t _B＝k ₁(Rext+R1//R2)·Ct+k ₀·Rs·Ct

＝k ₁·R1//R2·Ct+k ₀·Rs·Ct+k ₁·Rext·Ct

Make k ₁R1//R2Ct+k ₀RsCt=t ₀, then have:

t＝t ₀+k ₁·Rext·Ct

The delay time error of the linear on a large scale adjustable delay circuit that the present invention proposes has only 1/10th of existing delay circuit error, and promptly ± 0.5%, precision is higher.

The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences of doing based on spirit of the present invention change or modify, and all should be encompassed within protection scope of the present invention.

Claims (6)

1. linear on a large scale adjustable delay circuit; It comprises the oscillating circuit that is used to produce oscillator signal, the frequency dividing circuit that is used to produce time delayed signal; The output of described oscillating circuit is connected with the input of described frequency dividing circuit; It is characterized in that: described oscillating circuit comprises current-limiting resistance, T type resistor network, electric capacity, first not gate, second not gate, and the output of wherein said first not gate is connected to the input of described second not gate;

Described current-limiting resistance is connected between the end of input and described electric capacity of described first not gate, and the other end of described electric capacity is connected with the output of described second not gate;

Described T type resistor network comprises first divider resistance, second divider resistance, time delay resistance, and an end of an end of wherein said first divider resistance, an end of described second divider resistance, described time delay resistance connects into the T type; The other end of described first divider resistance is connected with the output of described first not gate; The other end of described second divider resistance is connected with the output of described second not gate, and the other end of described time delay resistance is connected with the common ends of described current-limiting resistance and described electric capacity;

The output of described oscillating circuit is drawn by the output of described second not gate.

2. linear on a large scale adjustable delay circuit according to claim 1 is characterized in that: described time delay resistance is resistance fixed resistance or adjustable resistance.

3. linear on a large scale adjustable delay circuit according to claim 1 is characterized in that: the time delayed signal that is produced of described frequency dividing circuit is the feedback control signal of the described frequency dividing circuit of input.

4. linear on a large scale adjustable delay circuit according to claim 1, it is characterized in that: described frequency dividing circuit comprises the CMOS counter.

5. linear on a large scale adjustable delay circuit according to claim 1, it is characterized in that: the output of described oscillating circuit is drawn test lead, and the oscillator signal that described oscillating circuit produced is drawn as test signal.

6. linear on a large scale adjustable delay circuit according to claim 1; It is characterized in that: the part except that described time delay resistance of described oscillating circuit is integrated into time delay module with described frequency dividing circuit, and described time delay resistance is the outer meeting resistance of described time delay module.

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