CN102360326B

CN102360326B - Field-programmable gate array (FPGA) simulating method and device

Info

Publication number: CN102360326B
Application number: CN201110136504.2A
Authority: CN
Inventors: 柴宁
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2011-05-24
Filing date: 2011-05-24
Publication date: 2014-01-01
Anticipated expiration: 2031-05-24
Also published as: CN102360326A

Abstract

The invention provides a field-programmable gate array (FPGA) simulating method and an FPGA simulating device. The method comprises the following steps that: an FPGA control module writes a starting identifier into an FPGA module to be tested so as to start the FPGA module to be tested; the FPGA module to be tested performs direct memory access (DMA) reading operation according to downlink BD ring information to acquire a data content of a downlink BD ring; the FPGA module to be tested performs DMA writing operation according to uplink BD ring information and writes the data content into an uplink BD ring; a BD management module outputs the data content which is written by the FPGA module to be tested to a data file; and when simulation time is over, a comparison output module compares the data content of the downlink BD ring with the data content in the data file and outputs a comparison result. Due to the adoption of the technical scheme, an FPGA of a DMA technology can be subjected to simulation test, so that a testing effect is improved, and testing cost is reduced.

Description

Field programmable gate array emulation mode and device

Technical field

The present invention relates to data communication field, relate in particular to a kind of field programmable gate array (Field-Programmable Gate Array; Referred to as: FPGA) emulation mode and device.

Background technology

FPGA is the novel high-performance programmable chip that a kind of integrated level is very high, and its internal circuit function is programmable (Programmable), can pass through hardware description language (Hardware Description Language; Referred to as: HDL) with the special designs instrument, section realizes and complicated circuit function flexibly within it, is applicable to high speed, highdensity high-end digital logic circuit design field.Direct memory access (Direct Memory Access; Referred to as: DMA) technology refers to a kind of data transfer operation of high speed, allow externally direct read/write data between equipment and storer, whole data transfer operation carries out under a control that is called dma controller, does not need central processing unit (Central Processing Unit in transmitting procedure; Referred to as: intervention CPU), CPU can carry out other work, thereby has greatly improved the operational efficiency of CPU.

If realize the DMA technology based on FPGA, and it is applied in Ethernet exchanging, allow ethernet medium access control (Media Access Control; Referred to as: MAC) Ether frame of layer directly is transferred to internal memory, and do not need the interference of CPU, simultaneously, also allow the data in internal memory directly are transferred to the ethernet mac layer, do not need the intervention of CPU yet, take full advantage of the advantage of DMA technology and FPGA technology, can improve greatly the processing data packets ability of network processing unit.

When based on FPGA, realizing circuit function, usually need to there is corresponding simulating, verifying technology to carry out simulating, verifying to the important component part of FPGA exploitation link, to guarantee the correctness of the function logic based on the FPGA realization.

In prior art, a kind of mode is the waveform adopted after the emulation tool of main flow is directly observed emulation, judge that whether design is correct, the method is applicable to the minimum design of scale, for the FPGA that realizes the DMA technology due to its density and complexity all higher, the method is inapplicable, can't guarantee the quality of design.In prior art, another kind of mode is directly the FPGA code to be changed in the burned FPGA of programming file, on the enterprising andante of built board, verifies, this mode not only testing efficiency is low higher, and testing cost is also higher.

Summary of the invention

The invention provides a kind of field programmable gate array emulation mode and device, in order to realize the emulation testing of the FPGA to realizing the DMA technology, reduce testing cost.

The invention provides a kind of on-site programmable gate array FPGA emulation mode, be applicable to the FPGA simulator, described FPGA simulator comprises: buffer description BD administration module, FPGA control module, memory module and comparison output module; Described method comprises:

Described FPGA control module is to FPGA module write-enable sign to be measured, to start described FPGA module to be measured;

Described FPGA module to be measured, according to pre-configured descending BD ring information and executing direct memory access DMA read operation, is obtained descending BD and is encircled corresponding data content from described memory module;

Described FPGA module to be measured, according to pre-configured up BD ring information and executing DMA write operation, writes up BD in described memory module by described data content and encircles in corresponding storage space;

The data content that described BD administration module will be written in described storage space by described FPGA module to be measured outputs to data file;

When simulation time finishes, the described relatively data content that output module encircles described descending BD in corresponding data content and described data file compares, and the output comparative result.

The invention provides a kind of on-site programmable gate array FPGA simulator, comprising:

Memory module, encircle corresponding data content for storing descending buffer description BD ring, up BD ring and described descending BD;

The FPGA control module, be used for to FPGA module write-enable sign to be measured, to start described FPGA module to be measured, so that described FPGA module to be measured is according to pre-configured descending BD ring information and executing direct memory access DMA read operation, obtain descending BD and encircle corresponding data content from described memory module, and make described FPGA module to be measured according to pre-configured up BD ring information and executing DMA write operation, described data content is written to up BD in described memory module and encircles in corresponding storage space;

The BD administration module, output in data file for the data content that will be written to described storage space by described FPGA module to be measured;

Compare output module, for when simulation time finishes, the data content that described descending BD is encircled in corresponding data content and described data file compares, and the output comparative result.

Field programmable gate array emulation mode of the present invention and device, the FPGA simulator is simulated respectively CPU and memory headroom by FPGA control module and memory module, and by starting FPGA module to be measured, make FPGA module to be measured carry out the DMA read-write operation, the data content of up BD is write in descending BD, the data content of the descending BD write by BD management module records FPGA module to be measured, after emulation finishes, the data content of the data content of up BD and descending BD is compared and exports comparative result, whether the function logic that judges FPGA module to be measured by comparative result is correct, reached realizing that the FPGA module of DMA technology carries out the purpose of emulation testing, simultaneously, compared with prior art, technical solution of the present invention, without the FPGA code is changed in the burned FPGA of programming file, has improved testing efficiency, has reduced testing cost.

The accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 be the embodiment of the present invention based on the structural representation of FPGA simulator;

The process flow diagram of the FPGA emulation mode that Fig. 2 provides for one embodiment of the invention;

The process flow diagram of the FPGA emulation mode that Fig. 3 provides for another embodiment of the present invention;

The process flow diagram of the FPGA emulation mode that Fig. 4 provides for further embodiment of this invention;

The structural representation of the FPGA simulator that Fig. 5 provides for one embodiment of the invention;

The structural representation of the FPGA simulator that Fig. 6 provides for another embodiment of the present invention.

Embodiment

For the purpose, technical scheme and the advantage that make the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.

Fig. 1 be the embodiment of the present invention based on the structural representation of FPGA simulator.As shown in Figure 1, this FPGA simulator comprises: FPGA control module 11, buffer description (Buffer Descriptor; Referred to as: BD) administration module 12, memory module 13 and comparison output module 14.

Wherein, FPGA control module 11 is for simulating the CPU of real network equipment, and main being responsible for carried out necessary configuration to FPGA module 10 to be measured, the quantity of available BD etc. in encircling such as first address, mode of operation, the BD of configurating downlink BD ring and up BD ring.Wherein, BD is a kind of data structure, usually forms circular linked list and uses, and in various embodiments of the present invention, the BD circular linked list is called to the BD ring, and the BD ring refers to the circular linked list consisted of a plurality of BD.In various embodiments of the present invention, will be for for FPGA module 10 to be measured, from the BD ring of memory module 13 reading out datas, being called descending BD ring, will be for for FPGA module 10 to be measured, to the BD of memory module 13 data writings ring, being called up BD ring, and the first address of descending BD ring and up BD ring refer to respectively descending BD ring and up BD encircle in the memory location of first BD in memory module 13.In addition, FPGA control module 11 also, for to FPGA module 10 write-enable signs to be measured,, to a register write-enable sign of FPGA module 10 to be measured, to start FPGA module 10 to be measured, makes FPGA module 10 to be measured carry out the DMA read-write operation.

Wherein, memory module 13 is for the internal memory of analog network equipment, encircle corresponding data content for storing descending BD ring, up BD ring and descending BD, descending BD encircles the data content that corresponding data content refers to that FPGA module 10 to be measured will read from memory module 13.In addition, memory module 13 is also write the data content of up BD ring by FPGA module 10 to be measured for storage, and FPGA module 10 to be measured writes data content in memory module 13 automatically according to up BD ring.

Wherein, BD administration module 12 is mainly by carrying out alternately with memory module 13, descending BD ring in managed storage module 13 and up BD ring, and the data content of being responsible for FPGA module 10 to be measured is written in memory module 13 outputs in a data file, for output module 14 relatively, descending BD is encircled to corresponding data content and compare with the data content that FPGA module 10 to be measured writes, and export comparative result.In addition, BD administration module 12 is also upgraded descending BD ring and up BD ring for being responsible for, and is about to used BD and reclaims, and again write new BD.

Further, as shown in Figure 1, this FPGA simulator also comprises: interface modular converter 15 and storage control module 16.Interface modular converter 15, with storage control module 16, with FPGA module 10 to be measured, be connected respectively, for be responsible for carrying out the conversion of bus interface form between FPGA module 10 to be measured and FPGA simulator, for example: the bus interface format conversion that FPGA module 10 to be measured is used becomes the inner interface format used of FPGA simulator, or the interface format that the FPGA simulator is used converts the bus interface form that FPGA module 10 to be measured is used to.Described form mainly refers to interface sequence, and interface modular converter 15 is specifically by two kinds of interface sequences are resolved and mutually changed, to guarantee that FPGA module 10 to be measured and FPGA simulator can proper communications.Storage control module 16 is connected between interface modular converter 15 and memory module 13, is responsible for memory module 13 is carried out to read-write operation.

The process flow diagram of the FPGA emulation mode that Fig. 2 provides for one embodiment of the invention.The FPGA simulator realization of the present embodiment based on shown in Fig. 1, as shown in Figure 2, the method for the present embodiment comprises:

Step 201, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Concrete, the FPGA control module, to write-enable sign in a register of FPGA module to be measured, to start FPGA module to be measured, makes the FPGA module carry out dma operation, starts the emulation testing process to FPGA to be measured.FPGA module to be measured is the FPGA code write, for realizing the DMA function.

Step 202, FPGA module to be measured, according to pre-configured descending BD ring information and executing DMA read operation, are obtained descending BD and are encircled corresponding data content from memory module.

Wherein, before emulation starts, the FPGA control module has been carried out the configuration of relevant information to FPGA module to be measured in advance, comprises descending BD ring information.This descending BD ring information comprises: the first address of descending BD ring, and descending BD encircles the start address in memory module, the length of descending BD ring, this descending BD ring comprises how many BD, number of available BD etc. in descending BD ring.

When FPGA module to be measured need to read the data content in memory module, according to these descending BD ring information, to reading descending BD in memory module, encircle corresponding data content.Wherein, for ease of describing, " FPGA module to be measured reads the data content in the storage space that descending BD is corresponding " is referred to as to " reading the data content of descending BD ".The data content that FPGA module to be measured reads descending BD ring can be to read data content corresponding to each BD in whole descending BD ring, can be also to read one of them or some data content corresponding to BD.The operation of due to FPGA module to be measured, reading descending BD belongs to prior art, at this, does not do too much description.

Step 203, FPGA module to be measured, according to pre-configured up BD ring information and executing DMA write operation, are written to up BD in memory module by the data content read and encircle in corresponding storage space.

Wherein, when the relevant information of the pre-configured FPGA module to be measured of FPGA control module, also comprise collocating uplink BD ring information.This up BD ring information comprises: the first address of up BD ring, and up BD encircles the start address in memory module, the length of up BD ring, this up BD ring comprises how many BD, number of available BD etc. in up BD ring.

When, arrive first in memory module and read up BD according to these up BD ring information, obtain the address information of wanting the data writing content, and then data content is write in memory module in the corresponding storage space of this address information.For ease of describing, " data writing content in the FPGA module to be measured storage space corresponding toward up BD " is referred to as to " to up BD data writing content ".

In the present embodiment, the data content that FPGA module to be measured writes in up BD is the data content that FPGA module to be measured is read from descending BD, carry out according to the operation of reading BD the operation of writing BD, but the present embodiment does not limit the mode of carrying out the operation of writing BD according to the operation of reading BD.For example: FPGA module to be measured can often read a data content from descending BD, and then carries out the operation that the data content that will read writes up BD.Again for example: FPGA module to be measured can also read a plurality of descending BD continuously, after obtaining a plurality of data contents, then carries out the operation that a plurality of data contents of reading is write successively to up BD, and then carries out the operation of reading BD.Again for example: after FPGA module to be measured also can all read the descending BD in whole descending BD ring, then carry out the operation that all data contents that read is write successively to up BD.Wherein, the operation of writing BD due to FPGA module to be measured belongs to prior art, at this, does not do too much description.

The data content that step 204, BD administration module will be written in storage space by FPGA module to be measured outputs to data file.

Whether in the present embodiment, the BD administration module is responsible for up BD in the detection of stored space, for finding, exist by the BD of FPGA module write-back to be measured.Wherein, the BD of write-back refers to the up BD by FPGA module data writing content to be measured.

To in up BD during the data writing content, can rewrite the zone bit of corresponding up BD, for example: the zone bit of up BD is rewritten as to " 0 " by " 1 ", identifies this up BD by write-back when FPGA module to be measured.Based on this, the BD administration module is specifically found by the up BD of write-back by the zone bit that detects each up BD in up BD ring.

When the BD administration module is found by the up BD of write-back, data content (follow-up referred to as the data content in up BD) by this up BD in corresponding storage space outputs in a data file, so that record writes the data content in up BD by FPGA module to be measured.In this explanation, in the present embodiment, FPGA module to be measured is that order reads the data content in descending BD, and the BD administration module to be order write the output of data content in up BD by FPGA module to be measured.

Step 205, when simulation time finishes, relatively output module encircles corresponding data content by descending BD and the data content in data file compares, and the output comparative result.

In the present embodiment, the tester pre-estimates emulation and finishes the required time, and sets accordingly simulation time.Before simulation time finishes, FPGA module to be measured will continue to carry out the DMA read-write operation according to above-mentioned steps 202 and step 203, and write the data content in up BD by the BD administration module according to step 204 output FPGA module to be measured.

When simulation time finishes, read successively the data content in descending BD by the order that relatively output module is read descending BD according to FPGA module to be measured, then the data content in descending BD and the data content in data file are compared, and the output comparative result.Wherein, if in comparative result, all data contents are all consistent, illustrate and take under the test condition that current BD data excitation file is test case, the DMA action of this FPGA module to be measured is correct, i.e. dma logic design is correct; If occur inconsistent data content in comparative result, illustrate that problem has appearred in the DMA action of FPGA module to be measured.When finding the problems in the design, the tester can further adopt other instruments or the method inspection place of ging wrong, for example can be by the daily record (log) of checking and analyze the BD administration module, or further by places of pinpointing the problems such as wave form analyses, and design is modified to DMA.

The FPGA emulation mode of the present embodiment, the FPGA simulator is simulated respectively CPU and memory headroom by FPGA control module and memory module, and by starting FPGA module to be measured, make FPGA module to be measured carry out the DMA read-write operation, the data content of descending BD is write in up BD, the data content of the up BD write by BD management module records FPGA module to be measured, after emulation finishes, the data content of the data content of up BD and descending BD is compared and exports comparative result, whether the function logic that judges FPGA module to be measured by comparative result is correct, reached realizing that the FPGA module of DMA technology carries out the purpose of emulation testing, simultaneously, compared with prior art, the emulation test method of the present embodiment does not need the FPGA code is converted in the burned special FPGA module of programming file and carries out, and can directly to the FPGA module realized by the FPGA code, be tested, therefore, can reduce testing cost.

The process flow diagram of the FPGA emulation mode that Fig. 3 provides for another embodiment of the present invention.The present embodiment is based on realization embodiment illustrated in fig. 2, and as shown in Figure 3, the method for the present embodiment comprises:

Step 301, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Step 302, BD administration module, according to update cycle and BD data excitation file, upgrade up BD ring and/or descending BD ring in memory module.

Before emulation testing starts, the tester is in advance according to testing requirement, configuration interface by the FPGA simulator has configured many descending BD information and many up BD information, these descending BD information and up BD information structure the BD data excitations file used of emulation testing.Wherein, the data content that information (such as next BD pointer, length field etc.), this descending BD that every descending BD information comprises this descending BD is corresponding and the information such as memory address (i.e. the first memory address) of storing this data content, wherein, the first memory address means the memory location of data content in memory module of descending BD.Every up BD information comprises the information (such as next BD pointer, length field etc.) of this up BD, the information such as memory address (i.e. the second memory address) that this up BD is corresponding, wherein, the second memory address means to write the memory location of data content in memory module in up BD.

Wherein, the capacity of descending BD ring and up BD ring is normally limited; and in order to carry out emulation testing to FPGA module to be measured more accurately; the tester can configure more descending BD information and up BD information usually, and these descending BD information and up BD information generally are greater than the capacity of descending BD ring and up BD ring.Carrying out along with the emulation testing process, BD in descending BD ring and up BD ring can be consumed, for this reason, the BD administration module has been set the update cycle of upgrading descending BD ring and up BD ring, when the update cycle arrives, the BD administration module is inquired about respectively descending BD ring and up BD ring in memory module, to find whether to exist descending BD and the up BD be used.Wherein, whether the BD administration module is rewritten by the zone bit that judges each BD, judges whether BD is used.For example: if the zone bit of descending BD is rewritten as " 0 " by " 1 ", show that this descending BD is used, show that FPGA module to be measured carried out the DMA read operation to this descending BD, and when read operation finishes, it has been carried out to write-back (be about to zone bit and be rewritten as " 0 " by original value " 1 "); In like manner, if the zone bit of up BD is rewritten as " 0 " by " 1 ", show that this up BD is used, show that FPGA module to be measured carried out the DMA write operation to this up BD, and when write operation finishes, it has been carried out to write-back (be about to zone bit and be rewritten as " 0 " by original value " 1 ").

While having the descending BD crossed by FPGA module execution DMA read operation write-back to be measured in inquiring descending BD ring, the BD administration module reads the descending BD information be not used from BD data excitation file, and the descending BD crossed with the descending BD information updating write-back read.This renewal process specifically refers to by the descending BD information read and covers original information, comprises with the data content in the descending BD information read and cover original data content.In this explanation, for fear of the problem that the data content that originally should not cover occurs having covered with the data content in the descending BD information read, requirement, when configurating downlink BD information, guarantees that the first memory address that every descending BD is corresponding is different, not overlapped.

While having the up BD crossed by FPGA module execution DMA write operation write-back to be measured in inquiring up BD ring, the BD administration module reads the up BD information be not used from BD data excitation file, and the up BD crossed with the up BD information updating write-back read, by the up BD information read, cover original information.

In this explanation, the BD administration module not only can be set the update cycle, can also set the BD quantity of each renewal, and the BD administration module not only can once upgrade a descending BD and/or up BD, can also upgrade a plurality of descending BD and/or a plurality of up BD simultaneously.

Realize recycling of descending BD ring and up BD ring through aforesaid operations, and then made and can be tested the DMA function of FPGA module to be measured by more BD information, improved test accuracy and test effect.

Step 303, FPGA module to be measured, according to pre-configured descending BD ring information and executing DMA read operation, are obtained descending BD and are encircled corresponding data content from memory module.

Step 304, FPGA module to be measured, according to pre-configured up BD ring information and executing DMA write operation, are written to up BD in memory module by the data content read and encircle in corresponding storage space.

The data content that step 305, BD administration module will be written in storage space by FPGA module to be measured outputs to data file.

Step 306, when simulation time finishes, relatively output module encircles corresponding data content by descending BD and the data content in data file compares, and the output comparative result.

Wherein, above-mentioned steps 303-step 306 can, referring to the description of above-mentioned steps 202-step 205, not repeat them here.

In this explanation, the operation that in the present embodiment, the BD administration module encircles descending BD and/or up BD ring is upgraded is step 302, with the operation of step 303-step 306, can separately carry out, it does not have sequencing, upgrades operation and is triggered and carried out by the update cycle.

The FPGA emulation mode of the present embodiment, the BD administration module is by being upgraded descending BD ring and/or up BD ring, make descending BD ring and up BD ring to recycle, and then make and can be tested the DMA function of FPGA module to be measured by more BD information, improve test accuracy and test effect.

Further, the BD administration module can be equal to the renewal operation of descending BD ring and/or up BD ring the situation that CPU in the network equipment processes descending BD or up BD, and can simulate by the different update cycles is set the various processing sights of CPU, and then realize under CPU different disposal sight the performance test to FPGA module to be measured.For example: shorter by the update cycle is set, upgrade operation comparatively frequent, can simulate CPU and process each BD situation more timely, and then test FPGA module to be measured various performances in this case, for example whether logic is correct, and whether response is timely etc.Again for example: longer by the update cycle is set, carry out after the long period and once upgrade operation, can simulate the situation that CPU has little time to process each BD, and then test FPGA module to be measured various performances in this case.

The process flow diagram of the FPGA emulation mode that Fig. 4 provides for further embodiment of this invention.As shown in Figure 4, the present embodiment can realize based on above-described embodiment, and as shown in Figure 4, the method for the present embodiment comprises:

Step 401, tester are according to testing requirement, by the configuration interface configuration FPGA configuration excitation file of FPGA simulator.

This FPGA configuration excitation file comprises descending BD ring information and up BD ring information, for for the FPGA control module, before emulation testing starts, FPGA module to be measured being carried out to the configuration of necessary information.

Step 402, tester are according to testing requirement, by the configuration interface configuration BD data excitation file of FPGA simulator.

This BD data excitation file comprises many descending BD information and many up BD information, and required BD information when emulation DMA function is provided, for the emulation testing process lays the first stone.

Wherein, the tester configures FPGA configuration excitation file and configures the BD data and encourages the sequencing of file not do restriction.Wherein, descending BD ring information and up BD ring information are for making FPGA module to be measured find descending BD and up BD in memory module.

Step 403, FPGA control module, according to FPGA configuration excitation file, write descending BD ring information and up BD ring information to FPGA module to be measured, so that FPGA module to be measured is configured.

Wherein, descending BD ring information comprises: the size of the first address of descending BD ring, descending BD ring (comprising how many descending BD); Up BD ring information comprises: the information such as size of the first address of up BD ring, up BD ring.

Concrete, the FPGA control module writes the information such as first address of the first address of descending BD ring, up BD ring respectively in the different registers of FPGA module to be measured, to realize the configuration to FPGA module to be measured.In addition, in this layoutprocedure, the FPGA control module can also configure the mode of operation of FPGA module to be measured, for example: can configure FPGA to be measured and be operated in the repeating query pattern, under this mode of operation, FPGA module to be measured can be carried out dma operation according to the first address of descending BD ring and the first address of up BD ring automatically, and the FPGA control module only need once configure and get final product FPGA module to be measured.Not only for example: can also configure FPGA to be measured and be operated in initiatively and inform (but also can be described as write tail) pattern, under this mode of operation, the every renewal of BD administration module once descending BD ring and/or up BD ring just need to reconfigure once FPGA module to be measured by the FPGA control module, needs in other words the configuration information of FPGA module to be measured is carried out to adaptive renewal.

In the present embodiment, FPGA module to be measured is operated under the repeating query pattern as example.

Step 404, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Step 405, BD administration module, according to update cycle and BD data excitation file, upgrade up BD ring and/or descending BD ring in memory module.

After above-mentioned preliminary work finishes, the FPGA control module starts FPGA module to be measured, starts emulation testing.Wherein, step 404 and step 405 can be referring to the descriptions of step 301 and step 302.

Step 406, FPGA module to be measured, according to pre-configured descending BD ring information and executing DMA read operation, are obtained descending BD and are encircled corresponding data content from memory module.

In actual application, the bus interface that FPGA module to be measured and the network equipment adopt is often different, therefore, need to carry out format conversion to two kinds of bus interface.Wherein, described format conversion mainly refers to the sequential of two kinds of bus interface is changed.

Based on this, in the emulation testing process of the present embodiment, by the interface modular converter of FPGA simulator, be responsible for two kinds of bus interface are carried out to format conversion, FPGA module more to be measured is tested.Wherein, this interface modular converter look the difference of the bus interface that FPGA module to be measured adopts can be by different implementations.

The specific implementation of this step 406 comprises following sub-step: step 4601, FPGA module to be measured are when needs read the data content in memory module, and according to the BD eye address in descending BD ring information, transmission is read first of descending BD and read the BD instruction.Step 4602, interface modular converter are read the BD instruction by first and are carried out format conversion, reading interface sequence corresponding to BD instruction to first is resolved, and, after being converted to the inner interface sequence used of FPGA simulator, send to the storage control module of FPGA simulator.Step 4603, storage control module are read the BD instruction according to first after format conversion, obtain the first memory address in descending BD from memory module, and send to interface modular converter.Step 4064, interface modular converter carry out format conversion by the first memory address, and the interface sequence while being about to send the first memory address sends to FPGA module to be measured after being converted to the interface sequence that FPGA module to be measured can identify.Step 4605, FPGA module to be measured, according to the first memory address, send the read data instruction of reading out data.After step 4606, interface modular converter carry out format conversion by the read data instruction, after soon the inner interface sequence used of FPGA simulator will be resolved and be converted to interface sequence corresponding to read data instruction, send to storage control module.Step 4607, storage control module, according to the read data instruction after format conversion, are obtained the data content that descending BD is corresponding, and are sent to interface modular converter the storage space of corresponding memory module from the first memory address.After the data content that step 4608, interface modular converter are corresponding by descending BD carries out format conversion, the interface sequence when being about to the FPGA simulator and sending data content sends to FPGA module to be measured after being converted to the interface sequence that FPGA module to be measured can identify.

Step 407, FPGA module to be measured, according to pre-configured up BD ring information and executing DMA write operation, are written to up BD in memory module by the data content read and encircle in corresponding storage space.

Based on above-mentioned, the embodiment of step 407 comprises following sub-step: step 4071, FPGA module to be measured be at needs during to memory module data writing content, according to the BD eye address in up BD ring information, sends and read second of up BD and read the BD instruction.Step 4072, interface modular converter are read after the BD instruction carries out format conversion, to second, to read interface sequence corresponding to BD instruction and resolved, and, after being converted to the inner interface sequence used of FPGA simulator, send to storage control module by second.Step 4073, storage control module are read the BD instruction according to second after format conversion, read the second memory address in up BD, and send to interface modular converter.After step 4074, interface modular converter carry out format conversion by the second memory address, the interface sequence while being about to send the second memory address sends to FPGA module to be measured after being converted to the interface sequence that FPGA module to be measured can identify.Step 4075, FPGA module to be measured send the data command of writing of data writing, and this is write data command and comprises the second memory address and data content.After step 4076, interface modular converter will be write data command and carry out format conversion, after being about to write interface sequence that data command is corresponding and being resolved and be converted to the inner interface sequence used of FPGA simulator, send to storage control module.Step 4077, storage control module, according to the data command of writing after format conversion, store data content in the storage space of memory module corresponding to the second memory address.

The data content that step 408, BD administration module will be written in storage space by FPGA module to be measured outputs to data file.

Step 409, when simulation time finishes, relatively output module encircles corresponding data content by descending BD and the data content in data file compares, and the output comparative result.

Above-mentioned steps 408 and step 409 can be referring to the descriptions of step 204 and step 205.

The FPGA emulation mode of the present embodiment, pre-configured various excitation files provide condition for emulation testing; By interface modular converter, two kinds of bus interface are carried out to format conversion and guaranteed that emulation testing can be in the situation that bus interface be different carries out, further comprehensive performance test to FPGA module to be measured.

In the above-described embodiments, when configuration FPGA module to be measured is operated in while writing the tail pattern, the BD administration module needs according to the renewal result to descending BD ring and/or up BD ring, by the FPGA control module, upgrades descending BD ring information and/or the up BD ring information in FPGA module to be measured.In other words, when descending BD ring and up BD encircle that wherein any one has renewal, just need to again to FPGA module to be measured, be configured.This process reconfigured is: the BD administration module will upgrade result and inform the FPGA control module, by the FPGA control module, again vicissitudinous information be write in the corresponding registers of FPGA module to be measured.Now, FPGA module to be measured can be carried out dma operation according to the configuration information after upgrading.

From the above, in the emulation testing process, on two kinds of bus interface, except having the request of DMA reading and writing data, also can exist the FPGA control module to configure the operation of FPGA module to be measured.Therefore, the interface modular converter of the present embodiment is except the format conversion of carrying out two kinds of bus interface, also for being responsible for the execution sequence of the various operations of arbitration.For example: interface modular converter is responsible for arbitrating the configuration operation of the request of DMA reading and writing data and FPGA control module.A kind of simple arbitration embodiment is: adopt the mode of distributing queue number to process the competition between different requests, be about to various requests and squeeze into first-in first-out (First Input First Output according to the principle of first-in first-out; Referred to as: FIFO) in the command queue, when repeating query, during to a request, take out this request and carry out subsequent treatment; For the request that repeating query is not arrived, continue to wait in line.

By above-mentioned embodiment, can do further test to FPGA module to be measured writing under the tail pattern, FPGA module more to be measured is tested, both can improve the test effect, there is again lower testing cost.

Further, the configuration interface related in the various embodiments described above is each tester's of being provided by the FPGA simulator interactive interface.This configuration interface can be developed based on excel, the formula that utilizes excel to provide and VBA (Visual Basic for Applications) construct each test suite, also the various excitation files of tester's configuration can be changed into to text (txt) file simultaneously, make and do not need compiling to get final product generating test use case, improved testing efficiency, reduced testing cost.

On this configuration interface, allow the tester to carry out format configuration to the data content in descending BD.Such as: can be configured to fixed mode (fix), certainly increase pattern (inc), from size reduction mode (dec) or random pattern (ram) etc.

In addition, this configuration interface can also be for showing comparative result or location mistake.For example: by calling data content in descending BD and the data content in data file, show two kinds of data contents by this configuration interface, and by comparing code, two kinds of data contents are compared, show comparative result simultaneously, can show more intuitively comparative result by this mode, be convenient to the tester and understand and locate errors present, carry out time update.

Further, because the excitation file in the embodiment of the present invention is invoked with textual form, do not need to be compiled, saved compilation time, the configuration of excitation file is simpler, therefore, can also to FPGA module to be measured, be tested by hyperchannel.

In sum, the FPGA emulation mode of the embodiment of the present invention has following beneficial effect: 1, utilize the excel instrument, the visual configuration interface is provided, be convenient to configuration excitation file, can show comparative result, easier analyzing and positioning problem simultaneously.2, compared with prior art, no longer carry out simulating, verifying on plate, belong to logical simulation, can pinpoint the problems fast, testing efficiency is higher, testing cost is low.3, can more comprehensively to FPGA module to be measured, be tested.

The structural representation of the FPGA simulator that Fig. 5 provides for one embodiment of the invention.As shown in Figure 5, the device of the present embodiment comprises: memory module 51, FPGA control module 52, BD administration module 53 and comparison output module 54.

Wherein, memory module 51, encircle corresponding data content for storing descending BD ring, up BD ring and descending BD.FPGA control module 52, with FPGA module 10 to be measured, be connected, be used for to FPGA module 10 write-enable signs to be measured, to start FPGA module 10 to be measured, so that FPGA module 10 to be measured is according to pre-configured descending BD ring information and executing DMA read operation, obtain descending BD and encircle corresponding data content from memory module 51, and make FPGA module 10 to be measured according to pre-configured up BD ring information and executing DMA write operation, data content is written to up BD in memory module 51 and encircles in corresponding storage space.BD administration module 53, be connected with memory module 51, for the data content that will be written to storage space by FPGA module 10 to be measured, outputs in data file.Relatively output module 54, is connected with memory module 51 with BD administration module 53, for when simulation time finishes, descending BD is encircled to corresponding data content and the data content in data file compares, and exports comparative result.

The FPGA simulator of the present embodiment can be used for the flow process of FPGA emulation mode shown in execution graph 2, and its specific works principle repeats no more, and refers to the description of embodiment of the method.

The FPGA simulator of the present embodiment, simulate respectively CPU by FPGA control module and memory module, internal memory, and by starting FPGA module to be measured, make FPGA module to be measured carry out dma operation, read the data content of descending BD and the data content read is write in up BD, by comparing output module, two kinds of data contents are compared to the output comparative result again, thereby realize the emulation testing to the FPGA module, simultaneously, compared with prior art, the FPGA simulator of the present embodiment can directly carry out emulation testing to the FPGA code, belong to logical simulation, without the programming of FPGA code is tested to the enterprising andante of FPGA board, both improved testing efficiency, reduced again testing cost.

The structural representation of the FPGA simulator that Fig. 6 provides for another embodiment of the present invention.The present embodiment is based on realization embodiment illustrated in fig. 5, and as shown in Figure 6, the device of the present embodiment also comprises: interface modular converter 61 and storage control module 62.

Wherein, interface modular converter 61, with FPGA module 10 to be measured, be connected, first read the BD instruction and format conversion is carried out in the read data instruction for what FPGA module to be measured 10 was sent, and send to storage control module 62, also for the first memory address and the data content that storage control module 62 is read, carry out sending to FPGA module 10 to be measured after format conversion.Wherein, first to read the BD instruction be according to the BD eye address in descending BD ring information, the instruction of reading descending BD of transmission by FPGA module 10 to be measured; The read data instruction be by FPGA module 10 to be measured according to the first memory address, the instruction of the read data of transmission.

Storage control module 62, with interface modular converter 61, with memory module 51, be connected, for according to first after format conversion, reading the BD instruction, obtain the first memory address in descending BD from memory module 51, and send to interface modular converter 61, also, for the read data instruction according to after format conversion, from the first memory address, the storage space of corresponding memory module 51, obtain the data content that descending BD is corresponding, and send to interface modular converter 61.

The above-mentioned functions module can be used for carrying out the operation of step 4061-step 4068 in said method embodiment, and its specific works principle repeats no more.

Further, when FPGA module 10 to be measured is carried out the DMA write operation, interface modular converter 61 is also for reading second of FPGA module 10 transmissions to be measured the BD instruction and write data command and carry out format conversion, and send to storage control module 62, and the second memory address that storage control module 62 is read carries out sending to FPGA module 10 to be measured after format conversion.Wherein, second to read the BD instruction be according to the BD eye address in up BD ring information, the instruction of reading up BD of transmission by FPGA module 10 to be measured; Write data command and be by FPGA module 10 to be measured according to the second memory address the instruction of writing data of transmission.

Storage control module 62 is also for reading the BD instruction according to second after format conversion, read the second memory address in up BD, and send to interface modular converter 61, and, for the data command of writing according to after format conversion, data content is stored in the storage space of memory module corresponding to the second memory address 51.

Further, the FPGA simulator of the present embodiment also comprises: configuration interface 63.This configuration interface 63 can be realized based on excel, for supplying the tester before starting emulation, according to testing requirement many descending BD information of configuration and many up BD information, generates BD data excitation file; Wherein, every descending BD information comprises data content that start address, each descending BD of descending BD ring is corresponding and the first memory address of storage data content; Every up BD information comprises start address and second memory address corresponding to each up BD of up BD ring.

Based on above-mentioned, BD administration module 53, also be connected with configuration interface 63, for according to update cycle and BD data excitation file, upgrades up BD ring and/or descending BD ring in memory module 51.Concrete, when the update cycle arrives, BD administration module 53 is inquired about respectively descending BD ring and up BD ring, and in descending BD ring, exist while by FPGA module 10 to be measured, carrying out the descending BD that DMA read operation write-backs cross, read a descending BD information from BD data excitation file, and the descending BD crossed with the BD information updating write-back read, and in up BD ring, exist while by FPGA module 10 to be measured, carrying out the up BD that DMA write operation write-backs cross, read a up BD information from BD data excitation file, and the up BD crossed with the up BD information updating write-back read.

In addition, this configuration interface 63 is also for supplying the tester according to testing requirement, and configuration FPGA configuration encourages file; Wherein, this FPGA configuration excitation file comprises descending BD ring information and up BD ring information.

Based on above-mentioned, FPGA control module 52 also is connected with configuration interface 63, for according to FPGA configuration excitation file, writes descending BD ring information and up BD ring information to FPGA module 10 to be measured, so that FPGA module to be measured is configured.

Wherein, FPGA control module 52 can also configure the mode of operation of FPGA module 10 to be measured, for example: repeating query pattern or write the tail pattern.When being operated in, FPGA module 10 to be measured writes tail pattern lower time, BD administration module 53 also is connected with FPGA control module 52, for the renewal result according to descending BD ring and/or up BD ring, by FPGA control module 52, upgrade descending BD ring information and/or the up BD ring information in FPGA module 10 to be measured.

Above-mentioned each functional module can be used for the corresponding flow process in the FPGA emulation mode shown in execution graph 2 or Fig. 3 or Fig. 4, and its principle of work repeats no more, and refers to the description of embodiment of the method.

The FPGA simulator of the present embodiment, simulate respectively CPU, internal memory by FPGA control module and memory module, and by starting FPGA module to be measured, make FPGA module to be measured carry out dma operation, read the data content of descending BD and the data content read is write in up BD, by comparing output module, two kinds of data contents are compared to the output comparative result again, thereby realize the emulation testing to the FPGA module, not only improved testing efficiency but also reduced testing cost.Further, the FPGA simulator of the present embodiment is convenient to by configuration interface the configuration that the tester carries out test case, has improved testing efficiency, has further reduced testing cost.And the FPGA simulator of the present embodiment also allows, under various sights, FPGA module to be measured being tested, to have realized the comprehensive coverage test to FPGA module to be measured, has improved the test effect, has reduced testing cost.

One of ordinary skill in the art will appreciate that: realize that the hardware that all or part of step of said method embodiment can be relevant by programmed instruction completes, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.

Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: its technical scheme that still can put down in writing aforementioned each embodiment is modified, or part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims

1. an on-site programmable gate array FPGA emulation mode, is characterized in that, is applicable to the FPGA simulator, and described FPGA simulator comprises: buffer description BD administration module, FPGA control module, memory module and comparison output module; Described method comprises:

Described FPGA module to be measured, according to pre-configured descending BD ring information and executing direct memory access DMA read operation, is obtained descending BD and is encircled corresponding data content from described memory module; Described descending BD ring refers to for the BD ring from described memory module reading out data for described FPGA module to be measured; Described BD ring refers to the circular linked list consisted of a plurality of BD;

Described FPGA module to be measured, according to pre-configured up BD ring information and executing DMA write operation, writes up BD in described memory module by described data content and encircles in corresponding storage space; Described up BD ring refers to for the BD ring to described memory module data writing for described FPGA module to be measured;

2. FPGA emulation mode according to claim 1, is characterized in that, described FPGA control module, to FPGA module write-enable sign to be measured, to start described FPGA module to be measured, comprises afterwards:

Described BD administration module, according to update cycle and BD data excitation file, upgrades up BD ring and/or descending BD ring in described memory module.

3. FPGA emulation mode according to claim 2, is characterized in that, described BD administration module is according to update cycle and BD data excitation file, and the up BD ring or the descending BD ring that upgrade in described memory module comprise:

When the described update cycle arrives, described BD administration module is inquired about respectively described descending BD ring and described up BD ring;

While having the descending BD crossed by described FPGA module execution DMA read operation write-back to be measured in described descending BD ring, from described BD data excitation file, read a descending BD information, and the descending BD crossed with the described write-back of descending BD information updating read;

While having the up BD crossed by described FPGA module execution DMA write operation write-back to be measured in described up BD ring, from described BD data excitation file, read a up BD information, and the up BD crossed with the described write-back of up BD information updating read.

4. FPGA emulation mode according to claim 3, is characterized in that, described FPGA control module, to FPGA module write-enable sign to be measured, to start described FPGA module to be measured, comprises before:

The tester, according to testing requirement, configures many described descending BD information and many described up BD information by configuration interface, generates described BD data excitation file.

5. according to claim 2 or 3 or 4 described FPGA emulation modes, it is characterized in that, described FPGA control module, to FPGA module write-enable sign to be measured, to start described FPGA module to be measured, comprises before:

Described FPGA control module, according to FPGA configuration excitation file, writes described descending BD ring information and described up BD ring information to described FPGA module to be measured, so that described FPGA module to be measured is configured.

6. FPGA emulation mode according to claim 5, it is characterized in that, described FPGA control module writes described descending BD ring information and described up BD ring information according to FPGA configuration excitation file to described FPGA module to be measured, so that described FPGA module to be measured is configured, comprises before:

The tester, according to testing requirement, configures described FPGA configuration excitation file by configuration interface, and described FPGA configuration excitation file comprises described descending BD ring information and described up BD ring information.

7. FPGA emulation mode according to claim 5, is characterized in that, described BD administration module, according to update cycle and BD data excitation file, upgrades up BD ring and/or descending BD ring in described memory module, comprises afterwards:

Described BD administration module, according to upgrading result, upgrades descending BD ring information and/or the described up BD ring information in described FPGA module to be measured by described FPGA control module.

8. according to claim 1 or 2 or 3 or 4 or 6 or 7 described FPGA emulation modes, it is characterized in that, described FPGA module to be measured is according to pre-configured descending BD ring information and executing DMA read operation, obtains descending BD and encircle corresponding data content and comprise from described memory module:

Described FPGA module to be measured is according to the BD eye address in described descending BD ring information, and transmission is read first of descending BD and read the BD instruction;

The interface modular converter of described FPGA simulator is read after the BD instruction carries out format conversion described first, sends to the storage control module of described FPGA simulator;

Described storage control module is read the BD instruction according to first after format conversion, obtains the first memory address in described descending BD from described memory module, and sends to described interface modular converter;

Described interface modular converter sends to described FPGA module to be measured after described the first memory address is carried out to format conversion;

Described FPGA module to be measured, according to described the first memory address, sends the read data instruction of reading out data;

Described interface modular converter sends to described storage control module after described read data instruction is carried out to format conversion;

Described storage control module, according to the read data instruction after format conversion, is obtained data content corresponding to described descending BD, and is sent to described interface modular converter the storage space of corresponding described memory module from described the first memory address;

Described interface modular converter after corresponding data content carries out format conversion by described descending BD, sends to described FPGA module to be measured.

9. FPGA emulation mode according to claim 8, it is characterized in that, described FPGA module to be measured is according to pre-configured up BD ring information and executing DMA write operation, described data content write in described memory module to up BD and encircle corresponding storage space and comprise:

Described FPGA module to be measured is according to the BD eye address in described up BD ring information, and transmission is read second of up BD and read the BD instruction;

Described interface modular converter is read after the BD instruction carries out format conversion, to send to described storage control module by described second;

Described storage control module is read the BD instruction according to second after format conversion, reads the second memory address in described up BD, and sends to described interface modular converter;

Described interface modular converter sends to described FPGA module to be measured after described the second memory address is carried out to format conversion;

Described FPGA module to be measured sends the data command of writing of data writing, and the write data instruction comprises described the second memory address and described data content;

Described interface modular converter sends to described storage control module after the write data instruction is carried out to format conversion;

Described storage control module, according to the data command of writing after format conversion, stores described data content in the storage space of described memory module corresponding to described the second memory address.

10. an on-site programmable gate array FPGA simulator, is characterized in that, comprising:

Memory module, encircle corresponding data content for storing descending buffer description BD ring, up BD ring and described descending BD; Described up BD ring refers to for the BD ring to described memory module data writing for FPGA module to be measured; Described descending BD ring refers to for the BD ring from described memory module reading out data for described FPGA module to be measured; Described BD ring refers to the circular linked list consisted of a plurality of BD;

The FPGA control module, be used for to described FPGA module write-enable sign to be measured, to start described FPGA module to be measured, so that described FPGA module to be measured is according to pre-configured descending BD ring information and executing direct memory access DMA read operation, obtain descending BD and encircle corresponding data content from described memory module, and make described FPGA module to be measured according to pre-configured up BD ring information and executing DMA write operation, described data content is written to up BD in described memory module and encircles in corresponding storage space;

11. FPGA simulator according to claim 10, is characterized in that, described BD administration module also, for according to update cycle and BD data excitation file, upgrades up BD ring and/or descending BD ring in described memory module.

12. FPGA simulator according to claim 11, it is characterized in that, described BD administration module is specifically for when the described update cycle arrives, inquire about respectively described descending BD ring and described up BD ring, and in described descending BD ring, exist while by described FPGA module to be measured, carrying out the descending BD that DMA read operation write-back crosses, read a descending BD information from described BD data excitation file, and the descending BD crossed with the described write-back of BD information updating read, and in described up BD ring, exist while by described FPGA module to be measured, carrying out the up BD that DMA write operation write-back crosses, read a up BD information from described BD data excitation file, and the up BD crossed with the described write-back of up BD information updating read.

13. FPGA simulator according to claim 12, it is characterized in that, described FPGA control module also, for according to FPGA configuration excitation file, writes described descending BD ring information and described up BD ring information to described FPGA module to be measured, so that described FPGA module to be measured is configured.

14. FPGA simulator according to claim 13, it is characterized in that, described BD administration module, also for the renewal result according to described descending BD ring and/or described up BD ring, upgrades described descending BD ring information and/or the described up BD ring information in described FPGA module to be measured by described FPGA control module.

15. according to the described FPGA simulator of claim 10-14 any one, it is characterized in that, also comprise: interface modular converter and storage control module;

Described interface modular converter, read the BD instruction and format conversion is carried out in the read data instruction for first of FPGA module transmission will be described to be measured, and send to described storage control module, and carry out sending to described FPGA module to be measured after format conversion for the first memory address and the data content that described storage control module is read; Described first to read the BD instruction be according to the BD eye address in descending BD ring information, the instruction of reading descending BD of transmission by described FPGA module to be measured; Described read data instruction is according to described the first memory address, the instruction of the read data of transmission by described FPGA module to be measured;

Described storage control module, for according to first after format conversion, reading the BD instruction, obtain the first memory address in described descending BD from described memory module, and send to described interface modular converter, and for the read data instruction according to after format conversion, obtain data content corresponding to described descending BD from described the first memory address the storage space of corresponding described memory module, and send to described interface modular converter.

16. FPGA simulator according to claim 15, it is characterized in that, described interface modular converter is also for reading second of described FPGA module transmission to be measured the BD instruction and write data command and carry out format conversion, and send to described storage control module, and carry out sending to described FPGA module to be measured after format conversion for the second memory address that described storage control module is read; Described second to read the BD instruction be according to the BD eye address in described up BD ring information, the instruction of reading up BD of transmission by described FPGA module to be measured; The write data instruction be by described FPGA module to be measured according to described the second memory address, the instruction of writing data of transmission;

Described storage control module is also for reading the BD instruction according to second after format conversion, read the second memory address in described up BD, and send to described interface modular converter, and, for the data command of writing according to after format conversion, described data content is stored in the storage space of described memory module corresponding to described the second memory address.